Nate Begeman
7ed816f900
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
Evan Cheng
169240beb7
- More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc.
...
- Some bug fixes and naming inconsistency fixes.
llvm-svn: 27377
2006-04-03 20:53:28 +00:00
Evan Cheng
875c895b0f
Added missing (any_extend (load ...)) patterns.
...
llvm-svn: 27120
2006-03-25 09:45:48 +00:00
Chris Lattner
ec3f1b5cd1
Fix the encodings of these new instructions, hopefully fixing the JIT
...
failures from last night
llvm-svn: 26981
2006-03-23 16:13:50 +00:00
Nate Begeman
0ec15cd042
Add support for 8 bit immediates with 16/32 bit cmp instructions
...
llvm-svn: 26966
2006-03-23 01:29:48 +00:00
Evan Cheng
8dd794ea70
Use the generic vector register classes VR64 / VR128 rather than V4F32,
...
V8I16, etc.
llvm-svn: 26838
2006-03-18 01:23:20 +00:00
Evan Cheng
ee1a44d5d8
Move some pattern fragments to the right files.
...
llvm-svn: 26831
2006-03-17 19:55:52 +00:00
Evan Cheng
d16fa97974
- Nuke 16-bit SBB instructions. We'll never use them.
...
- Nuke a bogus comment.
llvm-svn: 26815
2006-03-17 02:24:04 +00:00
Evan Cheng
d73d06f052
X86ISD::REP_STOS and X86ISD::REP_MOVS now produces a flag.
...
llvm-svn: 26604
2006-03-07 23:34:23 +00:00
Evan Cheng
2327759419
Enable Dwarf debugging info.
...
llvm-svn: 26581
2006-03-07 02:02:57 +00:00
Chris Lattner
999aa36a04
remove the read/write port/io intrinsics.
...
llvm-svn: 26479
2006-03-03 00:19:58 +00:00
Evan Cheng
995c9806ba
* Allow mul, shl nodes to be codegen'd as LEA (if appropriate).
...
* Add patterns to handle GlobalAddress, ConstantPool, etc.
MOV32ri to materialize these nodes in registers.
ADD32ri to handle %reg + GA, etc.
MOV32mi to handle store GA, etc. to memory.
llvm-svn: 26374
2006-02-25 10:02:21 +00:00
Evan Cheng
cb9fb051a5
- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
...
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
mentioned leaf nodes. Do not mutate and nodes and do not record the
selection in CodeGenMap. These nodes should be safe to duplicate. This is
a performance win.
llvm-svn: 26335
2006-02-23 20:41:18 +00:00
Evan Cheng
2977507828
PIC related bug fixes.
...
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.
llvm-svn: 26324
2006-02-23 02:43:52 +00:00
Evan Cheng
005de9e2bb
Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
...
Fixed some existing bugs (wrong predicates, prefixes) at the same time.
llvm-svn: 26310
2006-02-22 02:26:30 +00:00
Evan Cheng
8ab6294f94
One more round of reorg so sabre doesn't freak out. :-)
...
llvm-svn: 26303
2006-02-21 20:00:20 +00:00
Evan Cheng
f7296d8fa5
A big more cleaning up.
...
llvm-svn: 26302
2006-02-21 19:30:30 +00:00
Evan Cheng
223d3a073a
Moving things to their proper places.
...
llvm-svn: 26301
2006-02-21 19:26:52 +00:00
Evan Cheng
fee17dfff8
Split instruction info into multiple files, one for each of x87, MMX, and SSE.
...
llvm-svn: 26300
2006-02-21 19:13:53 +00:00
Evan Cheng
89553f1e86
Added separate alias instructions for SSE logical ops that operate on non-packed types.
...
llvm-svn: 26297
2006-02-21 02:24:38 +00:00
Evan Cheng
e68325d8aa
Added MMX and XMM packed integer move instructions, movd and movq.
...
llvm-svn: 26296
2006-02-21 01:39:57 +00:00
Evan Cheng
6a9422ce1c
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
...
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
Evan Cheng
b3d9ee74ad
Added fisttp for fp to int conversion.
...
llvm-svn: 26283
2006-02-18 02:36:28 +00:00
Evan Cheng
bf3558a375
x86 / Darwin PIC support.
...
llvm-svn: 26273
2006-02-18 00:15:05 +00:00
Nate Begeman
9c0ab71f4a
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
...
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
Evan Cheng
9de0ad321a
pxor (for FLD0SS) encoding was missing the OpSize prefix.
...
llvm-svn: 26244
2006-02-16 23:59:30 +00:00
Evan Cheng
bf4008c701
1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
...
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
spill / restore FsMOVAPSrr and FsMOVAPDrr.
llvm-svn: 26241
2006-02-16 22:45:17 +00:00
Evan Cheng
af9730a217
MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg.
...
llvm-svn: 26234
2006-02-16 19:34:41 +00:00
Evan Cheng
da095e61c1
cvtsd2ss / cvtss2sd encoding bug.
...
llvm-svn: 26193
2006-02-15 00:31:03 +00:00
Evan Cheng
198d9447d6
movaps, movapd encoding bug.
...
llvm-svn: 26192
2006-02-15 00:11:37 +00:00
Chris Lattner
da4bd5c64e
Eliminate the printCallOperand method, using a 'call' modifier on
...
printOperand instead.
llvm-svn: 26025
2006-02-06 23:41:19 +00:00
Evan Cheng
8fd9fd7866
Remove an unnecessary predicate.
...
llvm-svn: 25954
2006-02-04 02:23:01 +00:00
Evan Cheng
078962656b
Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a
...
flag so it can be flagged to a FST.
llvm-svn: 25953
2006-02-04 02:20:30 +00:00
Evan Cheng
b78bb375c2
Rearrange code to my liking. :)
...
llvm-svn: 25887
2006-02-01 23:01:57 +00:00
Evan Cheng
ef93bdc0cf
- Use xor to clear integer registers (set R, 0).
...
- Added a new format for instructions where the source register is implied
and it is same as the destination register. Used for pseudo instructions
that clear the destination register.
llvm-svn: 25872
2006-02-01 06:13:50 +00:00
Evan Cheng
45ebd632f2
- Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.
...
- Use XORP* to implement fneg.
llvm-svn: 25857
2006-01-31 22:28:30 +00:00
Chris Lattner
5587b270e4
* Fix 80-column violations
...
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.
llvm-svn: 25854
2006-01-31 19:43:35 +00:00
Evan Cheng
49467b6b5b
Added custom lowering of fabs
...
llvm-svn: 25831
2006-01-31 03:14:29 +00:00
Evan Cheng
d2d96373dc
Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
...
conversions. SSE does not have instructions to handle these tasks.
llvm-svn: 25817
2006-01-30 08:02:57 +00:00
Chris Lattner
b66484069a
The FP stack doesn't support UNDEF, ask the legalizer to legalize it
...
instead of lying and saying we have it.
llvm-svn: 25775
2006-01-29 06:44:22 +00:00
Evan Cheng
03aaa82992
AT&T assembly convention: registers are in lower case.
...
llvm-svn: 25714
2006-01-27 22:53:29 +00:00
Evan Cheng
5891f49c47
x86 CPU detection and proper subtarget support
...
llvm-svn: 25679
2006-01-27 08:10:46 +00:00
Chris Lattner
20d4194a0d
PHI and INLINEASM are now built-in instructions provided by Target.td
...
llvm-svn: 25674
2006-01-27 01:46:15 +00:00
Evan Cheng
224e14daa1
Remove the uses of STATUS flag register. Rely on node property SDNPInFlag,
...
SDNPOutFlag, and SDNPOptInFlag instead.
llvm-svn: 25629
2006-01-26 00:29:36 +00:00
Chris Lattner
c078165ea6
Emit the copies out of call return registers *after* the ISD::CALLSEQ_END
...
node, fixing fastcc and the case where a function has a frame pointer due
to dynamic allocas.
llvm-svn: 25580
2006-01-24 05:17:12 +00:00
Evan Cheng
2e4479d4a8
Rename fcmovae to fcmovnb and fcmova to fcmovnbe (following Intel manual).
...
Some assemblers can't recognize the aliases.
llvm-svn: 25494
2006-01-21 02:55:41 +00:00
Evan Cheng
2b24240110
A few more SH{L|R}D peepholes.
...
llvm-svn: 25473
2006-01-20 01:13:30 +00:00
Evan Cheng
e0f6454c5e
Added i16 SH{L|R}D patterns.
...
llvm-svn: 25468
2006-01-19 23:26:24 +00:00
Evan Cheng
cfe9d47379
adc and sbb need an incoming flag to ensure it reads the carry flag
...
from add / sub.
llvm-svn: 25444
2006-01-19 06:53:20 +00:00
Evan Cheng
be2cf5f948
Two peepholes:
...
(or (x >> c) | (y << (32 - c))) ==> (shrd x, y, c)
(or (x << c) | (y >> (32 - c))) ==> (shld x, y, c)
llvm-svn: 25438
2006-01-19 01:56:29 +00:00
Evan Cheng
1e112de44a
Zero extending load from i1 to i8.
...
llvm-svn: 25391
2006-01-17 07:02:46 +00:00
Evan Cheng
3ce28c990a
Bug fixes: fpGETRESULT should produces a flag result and X86ISD::FST should
...
read a flag.
llvm-svn: 25378
2006-01-17 00:19:47 +00:00
Evan Cheng
e678b39014
More typo's
...
llvm-svn: 25375
2006-01-16 23:26:53 +00:00
Evan Cheng
f7c719fe10
Some typo's
...
llvm-svn: 25374
2006-01-16 22:48:46 +00:00
Evan Cheng
de33ca2831
Fix FP_TO_INT**_IN_MEM lowering.
...
llvm-svn: 25368
2006-01-16 21:21:29 +00:00
Evan Cheng
fe83dd85c8
Added patterns for 8-bit multiply
...
llvm-svn: 25338
2006-01-15 10:05:20 +00:00
Nate Begeman
85b2dc0c4e
bswap implementation
...
llvm-svn: 25312
2006-01-14 03:14:10 +00:00
Evan Cheng
d92410b194
A typo.
...
llvm-svn: 25307
2006-01-14 01:18:49 +00:00
Evan Cheng
4d9bab5789
Add truncstore i1 patterns.
...
llvm-svn: 25296
2006-01-13 21:45:19 +00:00
Evan Cheng
794a7cf6fe
Fix sint_to_fp (fild*) support.
...
llvm-svn: 25257
2006-01-12 22:54:21 +00:00
Evan Cheng
169206c67f
Specify transformation from GlobalAddress to TargetGlobalAddress and
...
ExternalSymbol to TargetExternalSymbol.
llvm-svn: 25253
2006-01-12 19:36:31 +00:00
Evan Cheng
978f5581c4
X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be
...
linked together).
llvm-svn: 25247
2006-01-12 08:27:59 +00:00
Evan Cheng
dd45d29b56
* Materialize GlobalAddress and ExternalSym with MOV32ri rather than
...
LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.
llvm-svn: 25246
2006-01-12 07:56:47 +00:00
Evan Cheng
5841005bdf
Added ROTL and ROTR.
...
llvm-svn: 25232
2006-01-11 23:20:05 +00:00
Evan Cheng
66540aa32c
Support for MEMCPY and MEMSET.
...
llvm-svn: 25226
2006-01-11 22:15:48 +00:00
Evan Cheng
e42281bcba
* Add special entry code main() (to set x87 to 64-bit precision).
...
* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
call parmater passing.
llvm-svn: 25207
2006-01-11 06:09:51 +00:00
Evan Cheng
9adc8e5a3d
SSE cmov support.
...
llvm-svn: 25190
2006-01-11 00:33:36 +00:00
Evan Cheng
0cb5e32cda
* fp to sint patterns.
...
* fiadd, fisub, etc.
llvm-svn: 25189
2006-01-10 22:22:02 +00:00
Evan Cheng
8504673bb2
FP_TO_INT*_IN_MEM and x87 FP Select support.
...
llvm-svn: 25188
2006-01-10 20:26:56 +00:00
Evan Cheng
154cef5ccb
* Added undef patterns.
...
* Some reorg.
llvm-svn: 25163
2006-01-09 23:10:28 +00:00
Evan Cheng
d3babfe458
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS.
...
llvm-svn: 25158
2006-01-09 18:33:28 +00:00
Evan Cheng
66355df170
Addd (shl x, 1) ==> (shl x, x) peepholes.
...
llvm-svn: 25123
2006-01-06 02:31:59 +00:00
Evan Cheng
1e0d7b98f3
* Fast call support.
...
* FP cmp, setcc, etc.
llvm-svn: 25117
2006-01-06 00:43:03 +00:00
Evan Cheng
6c86cf3a5f
Added ConstantFP patterns.
...
llvm-svn: 25108
2006-01-05 02:08:37 +00:00
Evan Cheng
2329411038
DAG based isel call support.
...
llvm-svn: 25103
2006-01-05 00:27:02 +00:00
Evan Cheng
231b11ba87
Added field noResults to Instruction.
...
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
Evan Cheng
d87688fe72
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
...
* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag operand (return void is not
lowered so it does not have a flag operand.)
llvm-svn: 24997
2005-12-23 22:14:32 +00:00
Evan Cheng
995503fc91
More X86 floating point patterns.
...
llvm-svn: 24990
2005-12-23 07:31:11 +00:00
Evan Cheng
e458553c73
Bye bye HACKTROCITY.
...
llvm-svn: 24935
2005-12-22 02:26:21 +00:00
Evan Cheng
fb6413e05a
* Fix a GlobalAddress lowering bug.
...
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.
llvm-svn: 24921
2005-12-21 23:05:39 +00:00
Evan Cheng
add305de26
Oops. Accidentally deleted RET pattern. It's still needed for return void;
...
llvm-svn: 24920
2005-12-21 22:22:16 +00:00
Evan Cheng
6f15189a77
* Added support for X86 RET with an additional operand to specify number of
...
bytes to pop off stack.
* Added support for X86 SETCC.
llvm-svn: 24917
2005-12-21 20:21:51 +00:00
Chris Lattner
347c6eedae
This was meant to go in
...
llvm-svn: 24900
2005-12-21 07:50:26 +00:00
Chris Lattner
884def40f4
Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns
...
that were overloaded to work before and after the stackifier runs. With the
new clean world, it is possible to write patterns for these instructions: woo!
This also adds a few simple patterns here and there, though there are a lot
still missing. These should be easy to add though. :)
See the comments under "Floating Point Stack Support" for more details on
the new world order.
This patch as absolutely no effect on the generated code, woo!
llvm-svn: 24899
2005-12-21 07:47:04 +00:00
Chris Lattner
ee15b5393f
Wrap some long lines: no functionality change
...
llvm-svn: 24898
2005-12-21 05:34:58 +00:00
Evan Cheng
0226113ed5
* Added lowering hook for external weak global address. It inserts a load
...
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
value (or store / fld / copy to ST(0) for floating point value). This
eliminate the need to write C++ code to handle RET with variable number
of operands.
llvm-svn: 24888
2005-12-21 02:39:21 +00:00
Evan Cheng
ace8f1fafa
SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns.
...
llvm-svn: 24886
2005-12-20 22:59:51 +00:00
Evan Cheng
1c3ea75ffc
Added X86 readport patterns.
...
llvm-svn: 24879
2005-12-20 07:38:38 +00:00
Evan Cheng
bb34a50cb0
X86 conditional branch support.
...
llvm-svn: 24870
2005-12-19 23:12:38 +00:00
Chris Lattner
399dfec939
eliminate some redundancy
...
llvm-svn: 24781
2005-12-17 19:47:05 +00:00
Evan Cheng
6a94c77c55
Added anyext, modelled as zext on X86.
...
llvm-svn: 24759
2005-12-17 01:47:57 +00:00
Evan Cheng
5d90b26707
Added support for cmp, test, and conditional move instructions.
...
llvm-svn: 24756
2005-12-17 01:24:02 +00:00
Evan Cheng
43152cb8b6
* Promote all 1 bit entities to 8 bit.
...
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.
llvm-svn: 24726
2005-12-15 19:49:23 +00:00
Evan Cheng
f72e7055c0
Added frameindex, constpool, globaladdr, and externalsym as root nodes of
...
leaaddr.
llvm-svn: 24724
2005-12-15 08:31:04 +00:00
Evan Cheng
576b826f71
Use MOV8rm to load 1 bit value.
...
llvm-svn: 24721
2005-12-15 00:59:17 +00:00
Evan Cheng
3b094e89fb
Added sext and zext patterns.
...
llvm-svn: 24705
2005-12-14 02:22:27 +00:00
Evan Cheng
ad1e2fd14a
Add load + store folding srl and sra patterns.
...
llvm-svn: 24696
2005-12-13 07:24:22 +00:00
Evan Cheng
63f60d3edb
Beautify a few patterns.
...
llvm-svn: 24690
2005-12-13 02:40:18 +00:00
Evan Cheng
95d46be9e6
Some shl patterns which do load + store folding.
...
llvm-svn: 24689
2005-12-13 02:34:51 +00:00
Evan Cheng
6beadf1c29
A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility.
...
llvm-svn: 24688
2005-12-13 01:57:51 +00:00
Evan Cheng
d233c28d29
Add and, or, and xor patterns which fold load + stores.
...
llvm-svn: 24687
2005-12-13 01:41:36 +00:00
Evan Cheng
62999d6c5d
Add inc + dec patterns which fold load + stores.
...
llvm-svn: 24686
2005-12-13 01:02:47 +00:00
Evan Cheng
7f9fb7b095
Add neg and not patterns which fold load + stores.
...
llvm-svn: 24685
2005-12-13 00:54:44 +00:00
Evan Cheng
240071c011
Missed a couple redundant explicit type casts.
...
llvm-svn: 24684
2005-12-13 00:25:07 +00:00
Evan Cheng
e80ec06aaf
Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc.
...
llvm-svn: 24683
2005-12-13 00:14:11 +00:00
Evan Cheng
ea7f208813
* Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands.
...
This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.
llvm-svn: 24682
2005-12-13 00:01:09 +00:00
Evan Cheng
0ee9dc460a
Add some integer mul patterns.
...
llvm-svn: 24681
2005-12-12 23:47:46 +00:00
Evan Cheng
6c9f9ea7ec
Add some sub patterns.
...
llvm-svn: 24675
2005-12-12 21:54:05 +00:00
Evan Cheng
145318aefb
Add a few more add / store patterns. e.g. ADD32mi8.
...
llvm-svn: 24670
2005-12-12 19:45:23 +00:00
Evan Cheng
56f62789d7
* Added X86 store patterns.
...
* Added X86 dec patterns.
llvm-svn: 24654
2005-12-10 00:48:20 +00:00
Evan Cheng
6610545b7e
Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al
...
llvm-svn: 24648
2005-12-09 22:48:48 +00:00
Evan Cheng
6eb25df63a
Added explicit type field to ComplexPattern.
...
llvm-svn: 24637
2005-12-08 02:15:07 +00:00
Evan Cheng
1712ee5ab9
* Added intelligence to X86 LEA addressing mode matching routine so it returns
...
false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.
llvm-svn: 24635
2005-12-08 02:01:35 +00:00
Evan Cheng
60cc8da341
Remove unnecessary let hasCtrlDep=1 now it can be inferred.
...
llvm-svn: 24611
2005-12-05 23:09:43 +00:00
Chris Lattner
3583f5337b
Several things:
...
1. Remove redundant type casts now that PR673 is implemented.
2. Implement the OUT*ir instructions correctly. The port number really
*is* a 16-bit value, but the patterns should only match if the number
is 0-255. Update the patterns so they now match.
3. Fix patterns for shifts to reflect that the shift amount is always an
i8, not an i16 as they were believed to be before. This previous fib
stopped working when we started knowing that CL has type i8.
4. Change use of i16i8imm in SH*ri patterns to all be imm.
llvm-svn: 24599
2005-12-05 02:40:25 +00:00
Evan Cheng
1ce02890ce
Added isel patterns for RET, JMP, and WRITEPORT.
...
llvm-svn: 24588
2005-12-04 08:19:43 +00:00
Evan Cheng
f1352fa7d6
Proper support for shifts with register shift value.
...
llvm-svn: 24559
2005-12-01 00:43:55 +00:00
Nate Begeman
84be54b731
No longer track value types for asm printer operands, and remove them as
...
an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
llvm-svn: 24541
2005-11-30 18:54:35 +00:00
Chris Lattner
fdc786b18f
Fix a bug in a recent patch that broke shifts
...
llvm-svn: 24526
2005-11-30 05:11:18 +00:00
Evan Cheng
f412b7ba0c
Add more X86 ISel patterns.
...
llvm-svn: 24520
2005-11-29 19:38:52 +00:00
Chris Lattner
5d9ecff961
encode rdtsc correctly
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llvm-svn: 24435
2005-11-20 22:13:18 +00:00
Andrew Lenharth
a369904fc5
The second patch of X86 support for read cycle counter.
...
llvm-svn: 24430
2005-11-20 21:41:10 +00:00
Chris Lattner
af79013023
Teach the x86 backend about the register constraints of its addressing mode.
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Patch by Evan Cheng
llvm-svn: 24423
2005-11-19 07:01:30 +00:00
Chris Lattner
72fa26a85b
add more patterns, patch by Evan Cheng.
...
llvm-svn: 24406
2005-11-18 01:04:42 +00:00
Chris Lattner
f829636c6b
Add patterns for some 16-bit immediate instructions, patch contributed by
...
Evan Cheng.
llvm-svn: 24384
2005-11-17 02:01:55 +00:00
Chris Lattner
fec54e57a0
Add patterns for several simple instructions that take i32 immediates.
...
Patch contributed by Evan Cheng!
llvm-svn: 24382
2005-11-16 22:59:19 +00:00
Nate Begeman
3b6c2df603
Properly split f32 and f64 into separate register classes for scalar sse fp
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fixing a bunch of nasty hackery
llvm-svn: 23735
2005-10-14 22:06:00 +00:00
Chris Lattner
54139f0b83
give all operands names
...
llvm-svn: 23356
2005-09-14 21:10:24 +00:00
Chris Lattner
d7bd59d77e
add a few missing cases
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llvm-svn: 22891
2005-08-19 00:41:29 +00:00
Chris Lattner
f62a66a21c
Give ADJCALLSTACKDOWN/UP the correct operands.
...
Give a whole bunch of other stuff variable operands, particularly FP. The
FP stackifier is playing fast and loose with operands here, so we have to
mark them all as variable. This will have to be fixed before we can dag->dag
the X86 backend. The solution is for the pre-stackifier and post-stackifier
instructions to all be disjoint.
llvm-svn: 22890
2005-08-19 00:38:22 +00:00
Nate Begeman
6cd034da8e
Scalar SSE: load +0.0 -> xorps/xorpd
...
Scalar SSE: a < b ? c : 0.0 -> cmpss, andps
Scalar SSE: float -> i16 needs to be promoted
llvm-svn: 22637
2005-08-03 23:26:28 +00:00
Nate Begeman
957e0e7c9e
Get closer to fully working scalar FP in SSE regs. This gets singlesource
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working, and Olden/power.
llvm-svn: 22441
2005-07-15 00:38:55 +00:00
Nate Begeman
e5314eb2c2
First round of support for doing scalar FP using the SSE2 ISA extension and
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XMM registers. There are many known deficiencies and fixmes, which will be
addressed ASAP. The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.
The x86 backend will still default to x87 style FP. To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.
An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
Sum += P[i]; return Sum; }
The inner loop looks like the following:
x87:
.LBB_foo_1: # no_exit
fldl (%esp)
faddl (%eax,%ecx,8)
fstpl (%esp)
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
SSE2:
addsd (%eax,%ecx,8), %xmm0
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
llvm-svn: 22340
2005-07-06 18:59:04 +00:00
Nate Begeman
032a94775d
Initial set of .td file changes necessary to get scalar fp in xmm registers
...
working. The instruction selector changes will hopefully be coming later
this week once they are debugged. This is necessary to support the darwin
x86 FP model, and is recommended by intel as the replacement for x87. As
a bonus, the register allocator knows how to deal with these registers
across basic blocks, unliky the FP stackifier. This leads to significantly
better codegen in several cases.
llvm-svn: 22300
2005-06-27 21:20:31 +00:00
Chris Lattner
7327c042b4
Add markers in the asm file for tail calls, add a new ADJSTACKPTRri
...
sorta-pseudo-instruction
llvm-svn: 22042
2005-05-15 03:10:37 +00:00
Chris Lattner
64232a8480
Yes, calltarget is the operand of the day.
...
llvm-svn: 22040
2005-05-15 01:10:30 +00:00
Chris Lattner
37e226fa9b
Add some new instructions
...
llvm-svn: 22036
2005-05-14 23:35:21 +00:00
Chris Lattner
83d7e55471
add 'ret imm' instruction
...
llvm-svn: 21945
2005-05-13 17:56:48 +00:00
Chris Lattner
7ba0699b05
Fix the syntax of the i/o instructions, these are obviously unused.
...
llvm-svn: 21829
2005-05-09 20:49:20 +00:00
Chris Lattner
236cef3563
Add some new X86 instrs, patch contributed by Morten Ofstad
...
llvm-svn: 21608
2005-04-28 21:50:05 +00:00
Chris Lattner
ba7cdbebb1
add signed versions of the extra precision multiplies
...
llvm-svn: 21106
2005-04-06 04:19:22 +00:00
Chris Lattner
71434aa2dd
add an fabs instr
...
llvm-svn: 21006
2005-04-02 04:31:56 +00:00
Chris Lattner
a024984017
Fix spelling, patch contributed by Gabor Greif!
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llvm-svn: 20343
2005-02-27 06:18:25 +00:00
Chris Lattner
34757ff939
Add rotate instructions.
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llvm-svn: 19690
2005-01-19 07:50:03 +00:00
Chris Lattner
9d5ee289d7
Improve coverage of the X86 instruction set by adding 16-bit shift doubles.
...
llvm-svn: 19687
2005-01-19 07:31:24 +00:00
Chris Lattner
c03f360215
Teach the code generator that shrd/shld is commutable if it has an immediate.
...
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
llvm-svn: 19686
2005-01-19 07:11:01 +00:00
Chris Lattner
65d007ab62
Add conditional moves for the parity flag.
...
llvm-svn: 19437
2005-01-10 22:09:33 +00:00
Chris Lattner
1aaf8cccb2
ADC and IMUL are also commutable.
...
llvm-svn: 19264
2005-01-03 01:27:59 +00:00
Chris Lattner
0d6f03e52b
Two changes here:
...
1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP.
2. Set the isCommutable and isPromotableTo3Address bits on several
instructions.
llvm-svn: 19246
2005-01-02 02:35:46 +00:00
John Criswell
402e338f11
Correct the name of stosd for the AT&T syntax:
...
It's stosl (l for long == 32 bit).
llvm-svn: 17658
2004-11-10 04:48:15 +00:00
Chris Lattner
82aa8544a5
Remove debugging code, fix encoding problem. This fixes the problems
...
the JIT had last night.
llvm-svn: 16766
2004-10-06 14:31:50 +00:00
Chris Lattner
acd213fba3
Add some new instructions. Fix the asm string for sbb32rr
...
llvm-svn: 16759
2004-10-06 04:01:02 +00:00
Chris Lattner
5959f4a108
Convert some missed patterns to support AT&T style
...
llvm-svn: 16645
2004-10-04 07:23:07 +00:00
Chris Lattner
a05d9f53bb
Apparently the GNU assembler has a HUGE hack to be compatible with really
...
old and broken AT&T syntax assemblers. The problem with this hack is that
*SOME* forms of the fdiv and fsub instructions have the 'r' bit inverted.
This was a real pain to figure out, but is trivially easy to support: thus
we are now bug compatible with gas and gcc.
llvm-svn: 16644
2004-10-04 07:08:46 +00:00
Chris Lattner
08098895db
Fix incorrect suffix
...
llvm-svn: 16642
2004-10-04 05:20:16 +00:00
Chris Lattner
c2fc9597bd
Fix some more missed suffixes and swapped operands
...
llvm-svn: 16641
2004-10-04 01:38:10 +00:00
Chris Lattner
7b15a84728
Add missing suffixes to FP instructions for AT&T mode
...
llvm-svn: 16640
2004-10-04 00:43:31 +00:00
Chris Lattner
94780713a8
Add support to the instruction patterns for AT&T style output, which will
...
hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also
includes changes to wrap the whole file to 80 columns! Woot! :)
Note that the AT&T style output has not been tested at all.
llvm-svn: 16638
2004-10-03 20:35:00 +00:00
Alkis Evlogimenos
4d2b0a2b5b
Use a shorter form to express implicit use/defs in FpGETRESULT and
...
FpSETRESULT.
llvm-svn: 16247
2004-09-08 18:29:31 +00:00
Alkis Evlogimenos
3540de9ea6
A call instruction should implicitely define ST0 since the return
...
value is returned in that register. The pseudo instructions
FpGETRESULT and FpSETRESULT shold also have an implicity use and def
of ST0 repsecitvely.
llvm-svn: 16246
2004-09-08 16:54:54 +00:00
Chris Lattner
5e7e9b6c26
Remove a bunch of ad-hoc target-specific flags that were only used by the
...
old asmprinter.
llvm-svn: 15660
2004-08-11 07:12:04 +00:00
Chris Lattner
3cef2f82ff
Add asmprintergen support for the last X86 instruction that needs it: pcrelative calls.
...
llvm-svn: 15657
2004-08-11 06:59:12 +00:00
Chris Lattner
9c171be048
Scrunch memoperands, add a few more for floating point memops
...
Eliminate the FPI*m classes, converting them to use FPI instead.
llvm-svn: 15655
2004-08-11 06:50:10 +00:00
Chris Lattner
b287047c3f
Make FPI take asm string and operand list
...
llvm-svn: 15653
2004-08-11 05:54:16 +00:00
Chris Lattner
c304bf7e03
Nuke the Im*i* patterns, by asmprintergenifying all users.
...
llvm-svn: 15652
2004-08-11 05:31:07 +00:00
Chris Lattner
65ab459759
X86 instructions that read-modify-write memory are not LLVM two-address instructions.
...
llvm-svn: 15651
2004-08-11 05:07:25 +00:00
Chris Lattner
384711a69c
Get rid of the Im8, Im16, Im32 classes, converting more instructions over to
...
asmprintergeneration
llvm-svn: 15650
2004-08-11 04:31:00 +00:00
Chris Lattner
b66b9cd4a9
Convert asmprinter to new style of instruction printer
...
Start asmprintergen'ifying machine instrs with memory operands.
llvm-svn: 15646
2004-08-11 02:25:00 +00:00
Chris Lattner
5cf0a20d4f
This is purely a formatting patch that gets us closer to the mecca of fitting
...
X86InstrInfo.td into 80 columns
llvm-svn: 15629
2004-08-10 21:21:30 +00:00
Chris Lattner
f6c4de46e0
Drop the first argument of FPI, and asmprinterify fxch
...
llvm-svn: 15628
2004-08-10 21:02:13 +00:00
Chris Lattner
97abe28059
This purely mechanical patch gives the "I" tblgen class operand list and asm
...
string operands, and adjusts all users to pass them in instead of using II.
llvm-svn: 15624
2004-08-10 20:17:41 +00:00
Chris Lattner
332fa9be1c
Convert Ii32 instructions over to use the asmprinter generator
...
llvm-svn: 15621
2004-08-10 19:06:36 +00:00
Chris Lattner
068209661a
Convert the Ii16 instructions over
...
llvm-svn: 15606
2004-08-10 16:22:02 +00:00
Chris Lattner
315782f0ac
Convert all Ii8 instructions over to the autogenerated asmprinter.
...
llvm-svn: 15605
2004-08-10 16:09:54 +00:00
Chris Lattner
df7c9d0339
Convert all I<> instructions to asmformat.
...
Delete the 'name' field of all instructions that have asmformats.
llvm-svn: 15403
2004-08-01 09:52:59 +00:00
Chris Lattner
90a4b737dd
Eliminate 3 of the X86 printImplicit* flags.
...
llvm-svn: 15398
2004-08-01 08:23:17 +00:00
Chris Lattner
0c5ab21dcd
Convert more instructions over to the asmprinter
...
llvm-svn: 15396
2004-08-01 08:13:11 +00:00
Chris Lattner
6c596faddb
Switch more instructions over to using the asmprinter. Fix bugs in the emission
...
of in/out instructions (missing %'s on registers).
llvm-svn: 15393
2004-08-01 07:44:35 +00:00
Chris Lattner
9a7b050ebb
Specify an asm string and operands lists for a bunch of instructions.
...
This only really covers no-operand instructions so far.
llvm-svn: 15387
2004-08-01 06:01:00 +00:00
Chris Lattner
9bce44c8cc
Entirely eliminate all patterns and expanders from this file. We shall go
...
with an incremental approach rather than a revolutionary approach.
llvm-svn: 15379
2004-08-01 03:25:01 +00:00
Chris Lattner
9a23ab1e63
Mark barrier instructions. Execution does not fall through uncond branches
...
or return intructions.
llvm-svn: 15356
2004-07-31 02:10:53 +00:00
Chris Lattner
7d8093efb1
No really, these are dead now
...
llvm-svn: 14145
2004-06-11 04:50:14 +00:00
Chris Lattner
a8e603b719
Now that compare instructions aren't lumped in with the other twoargfp instructions,
...
we can get rid of the FpUCOM/FpUCOMi pseudo instructions, which makes stuff simpler
and faster.
llvm-svn: 14144
2004-06-11 04:49:02 +00:00
Chris Lattner
b050f778ca
Introduce a new FP instruction type to separate the compare cases from the
...
twoarg cases.
llvm-svn: 14143
2004-06-11 04:41:24 +00:00
Chris Lattner
4c8b57ea31
Add support for the setp instructions
...
llvm-svn: 14140
2004-06-11 04:30:06 +00:00
Chris Lattner
15ac62827e
Add immediate forms of in/out. Use let to shorten lines
...
llvm-svn: 12895
2004-04-13 17:19:31 +00:00
Chris Lattner
43f754339a
Fix issues that the local allocator has dealing with instructions that implicitly use ST(0)
...
llvm-svn: 12855
2004-04-12 03:02:48 +00:00
Chris Lattner
9cdc472518
No really, fix printing for LLC. I gotta get a way for CVS to whine at me if
...
I have unsaved emacs buffers, geeze...
llvm-svn: 12854
2004-04-12 01:52:04 +00:00
Chris Lattner
f1d59be0e8
Correct printing for LLC and the encoding for the JIT
...
llvm-svn: 12853
2004-04-12 01:50:04 +00:00
Chris Lattner
cfb7144bf1
Add two new instructions
...
llvm-svn: 12850
2004-04-12 01:38:55 +00:00
Chris Lattner
dda382531e
Add some new instructions
...
llvm-svn: 12838
2004-04-11 20:24:15 +00:00
John Criswell
8740c3767d
Changes recommended by Chris:
...
InstSelectSimple.cpp:
Change the checks for proper I/O port address size into an exit() instead
of an assertion. Assertions aren't used in Release builds, and handling
this error should be graceful (not that this counts as graceful, but it's
more graceful).
Modified the generation of the IN/OUT instructions to have 0 arguments.
X86InstrInfo.td:
Added the OpSize attribute to the 16 bit IN and OUT instructions.
llvm-svn: 12786
2004-04-08 22:39:13 +00:00
John Criswell
f6b16ea70b
Added the llvm.readport and llvm.writeport intrinsics for x86. These do
...
I/O port instructions on x86. The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output. This required adjustment to some
methods so that a leading comma would or would not be printed.
llvm-svn: 12782
2004-04-08 20:31:47 +00:00
Chris Lattner
993d6106c7
Fix incorrect encoding of some ADC and SBB instuctions
...
llvm-svn: 12710
2004-04-06 19:20:32 +00:00
Chris Lattner
e84f12a165
The sbb instructions really ARE sbb's, not adc's
...
llvm-svn: 12682
2004-04-06 02:02:11 +00:00
Alkis Evlogimenos
85e007a6dc
Fix type in comments
...
llvm-svn: 12611
2004-04-02 16:02:50 +00:00
Alkis Evlogimenos
20b074682c
Add more ADC and SBB variants
...
llvm-svn: 12607
2004-04-02 07:11:10 +00:00
Chris Lattner
e4fa3010db
Add FP conditional move instructions, which annoyingly have special properties
...
that require the asmwriter to be extended (printing implicit uses before the
explicit operands)
llvm-svn: 12574
2004-03-31 22:02:13 +00:00
Chris Lattner
57968a98df
Fix some serious bugs in the cmov descriptions, which didn't cause a problem because
...
we never generated them
Make indentation a bit more consistent
llvm-svn: 12549
2004-03-30 20:18:02 +00:00
Alkis Evlogimenos
6ac147a7fb
Add LAHF instruction
...
llvm-svn: 12424
2004-03-15 17:20:14 +00:00