RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 12:33:33 +02:00
Code Issues Projects Releases Wiki Activity
59,415 Commits 4 Branches 5 Tags 704 MiB
4cdb545401
Commit Graph

490 Commits

Author SHA1 Message Date
Bob Wilson
0cf2be2466 Generate Neon VTBL and VTBX instructions from the corresponding intrinsics. 
llvm-svn: 78835
 2009-08-12 20:51:55 +00:00
Chris Lattner
aa0dbe5764 now that these are in file-check format, we can merge them together 
into one bigger test (which runs faster)

llvm-svn: 78672
 2009-08-11 15:54:17 +00:00
Bob Wilson
2195d82b90 Convert more Neon tests to use FileCheck. 
llvm-svn: 78648
 2009-08-11 05:51:19 +00:00
Bob Wilson
d64e304671 Use vAny type to get rid of Neon intrinsics that differed only in whether 
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.

If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.

llvm-svn: 78646
 2009-08-11 05:39:44 +00:00
Bob Wilson
1c75a23299 Use new EVT::vAny type to combine Neon intrinsics for VPADD. 
llvm-svn: 78632
 2009-08-11 01:15:26 +00:00
David Goodwin
fcb59a8a30 Use FileCheck. 
llvm-svn: 78614
 2009-08-10 23:14:14 +00:00
David Goodwin
151235d75d Use FileCheck... its good for you... 
llvm-svn: 78613
 2009-08-10 23:06:57 +00:00
David Goodwin
7c0b4485d1 Fix test. 
llvm-svn: 78611
 2009-08-10 22:58:08 +00:00
David Goodwin
2e2fe66e85 Fix test. 
llvm-svn: 78606
 2009-08-10 22:31:04 +00:00
David Goodwin
36a5b02e4f Use NEON for single-precision int<->FP conversions. 
llvm-svn: 78604
 2009-08-10 22:17:39 +00:00
Dan Gohman
fe048746c2 Add nounwind keywords. 
llvm-svn: 78568
 2009-08-10 16:48:40 +00:00
Chris Lattner
cc70d578be Make the big switch: Change MCSectionMachO to represent a section *semantically* 
instead of syntactically as a string.  This means that it keeps track of the 
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and 
"attribute(section)", so we should now start getting errors about invalid 
section attributes from the compiler instead of the assembler on darwin.

Still todo: 
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
   S_GB_ZEROFILL segment type?

llvm-svn: 78547
 2009-08-10 01:39:42 +00:00
Bob Wilson
8b13d5c8e3 Add tests for Neon VZIP and VUZP instructions. 
llvm-svn: 78529
 2009-08-09 06:48:29 +00:00
Bob Wilson
06b61e2598 Add a test for Neon VTRN instructions. 
llvm-svn: 78528
 2009-08-09 06:30:46 +00:00
Bob Wilson
a2913fe5f5 Convert more Neon tests to use FileCheck. 
llvm-svn: 78433
 2009-08-07 23:45:02 +00:00
David Goodwin
c0fe95d8ce Make NEON single-precision FP support the default for cortex-a8 (again). 
llvm-svn: 78430
 2009-08-07 23:32:33 +00:00
Anton Korobeynikov
9b52601704 2 more vdup.32 cases 
llvm-svn: 78419
 2009-08-07 22:36:50 +00:00
Bob Wilson
bd7627b23e Implement Neon VST[234] operations. 
llvm-svn: 78330
 2009-08-06 18:47:44 +00:00
Bob Wilson
5cbc89337b Fix incorrect intrinsic declarations. 
llvm-svn: 78329
 2009-08-06 18:46:26 +00:00
Bob Wilson
6fb1102b9a Add tests for new NEON vld instructions. 
llvm-svn: 78264
 2009-08-06 00:38:31 +00:00
Bob Wilson
a12289f373 Convert more Neon tests to FileCheck. 
llvm-svn: 78261
 2009-08-05 23:51:20 +00:00
Anton Korobeynikov
07ce0611d9 Missed pieces for ARM HardFP ABI. 
Patch by Sandeep Patel!

llvm-svn: 78225
 2009-08-05 19:04:42 +00:00
Bob Wilson
36d2cedfcb Convert more Neon tests to use FileCheck. 
llvm-svn: 78111
 2009-08-04 22:01:41 +00:00
Bob Wilson
423086a047 Convert a few Neon tests to use FileCheck. 
llvm-svn: 78108
 2009-08-04 21:33:22 +00:00
Jakob Stoklund Olesen
5edb25cd45 Clean up the handling of two-address operands in RegScavenger. 
This fixes PR4528.

llvm-svn: 78107
 2009-08-04 21:30:30 +00:00
David Goodwin
648590849c Add NEON single-precision FP support for fabs and fneg. 
llvm-svn: 78101
 2009-08-04 20:39:05 +00:00
David Goodwin
5efde448fa Match common pattern for FNMAC. Add NEON SP support. 
llvm-svn: 78085
 2009-08-04 18:44:29 +00:00
David Goodwin
e034df4626 Improve tests. 
llvm-svn: 78083
 2009-08-04 18:11:59 +00:00
David Goodwin
99adffe5f2 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. 
llvm-svn: 78081
 2009-08-04 17:53:06 +00:00
Evan Cheng
d840bf2eac Fix PR4528. This scavenger assertion is too strict. The two-address value is 
killed by another operand.

There is probably a better fix. Either 1) scavenger can look at other operands, or
2) livevariables can be smarter about kill markers. Patches welcome.

llvm-svn: 78072
 2009-08-04 16:52:44 +00:00
Bob Wilson
eb3b616a7e Lower CONCAT_VECTOR during legalization instead of matching it during isel. 
Add a testcase.

llvm-svn: 77992
 2009-08-03 20:36:38 +00:00
Jakob Stoklund Olesen
1b274fd5f0 Fix Bug 4657: register scavenger asserts with subreg lowering 
When LowerSubregsInstructionPass::LowerInsert eliminates an INSERT_SUBREG
instriction because it is an identity copy, make sure that the same registers
are alive before and after the elimination.

When the super-register is marked <undef> this requires inserting an
IMPLICIT_DEF instruction to make sure the super register is live.

Fix a related bug where a kill flag on the inserted sub-register was not transferred properly.

Finally, clear the undef flag in MachineInstr::addRegisterKilled. Undef implies dead and kill implies live, so they cant both be valid.

llvm-svn: 77989
 2009-08-03 20:08:18 +00:00
Chris Lattner
1e3d2247ba switch to filecheck format 
llvm-svn: 77841
 2009-08-02 00:32:26 +00:00
Evan Cheng
fabbd6219a Add VFP3 D registers to the DPR register class. 
llvm-svn: 77521
 2009-07-29 23:03:41 +00:00
Bob Wilson
355e0b70e0 Change Neon VLDn intrinsics to return multiple values instead of really 
wide vectors.  Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct.  Adjust tests accordingly.

llvm-svn: 77468
 2009-07-29 16:39:22 +00:00
Bob Wilson
ec256c8938 Add support for ARM Neon VREV instructions. 
Patch by Anton Korzh, with some modifications from me.

llvm-svn: 77101
 2009-07-26 00:39:34 +00:00
Evan Cheng
4a77f28c47 Use getTargetConstant instead of getConstant since it's meant as an constant operand. 
llvm-svn: 76803
 2009-07-22 22:03:29 +00:00
Evan Cheng
88dbc00ca7 Ignore undef uses. 
llvm-svn: 76799
 2009-07-22 21:51:42 +00:00
Evan Cheng
949c2404a2 Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. 
llvm-svn: 76520
 2009-07-21 00:31:12 +00:00
Evan Cheng
919f5c5559 Forgot this test earlier. 
llvm-svn: 76485
 2009-07-20 21:46:42 +00:00
Chris Lattner
499fe29f12 fix an arm codegen bug (the same as PR4482 on ppc) where available_externally 
symbols were not getting stubs.  While I'm at it, add a big testcase for
stub generation to make sure I don't break anything.

llvm-svn: 75737
 2009-07-15 04:12:33 +00:00
Evan Cheng
4249ad4c00 Remove a bogus assertion. 
llvm-svn: 75206
 2009-07-10 00:23:48 +00:00
Bob Wilson
f5f52fa9d6 Handle 'a' modifier on inline assembly operands. 
This is part of the fix for pr4521.

llvm-svn: 75201
 2009-07-09 23:54:51 +00:00
Lang Hames
ceb80b14d3 Improved tracking of value number kills. VN kills are now represented 
as an (index,bool) pair. The bool flag records whether the kill is a
PHI kill or not. This code will be used to enable splitting of live
intervals containing PHI-kills.

A slight change to live interval weights introduced an extra spill
into lsr-code-insertion (outside the critical sections). The test 
condition has been updated to reflect this.

llvm-svn: 75097
 2009-07-09 03:57:02 +00:00
Bob Wilson
8d4a8b9370 Implement NEON vst1 instruction. 
llvm-svn: 75037
 2009-07-08 20:32:02 +00:00
Bob Wilson
3809b333de Implement NEON vld1 instructions. 
llvm-svn: 75019
 2009-07-08 18:11:30 +00:00
Chris Lattner
2939f0a318 Change these tests to use [fi]cmp+sext instead of v[fi]cmp. No 
functionality change.

llvm-svn: 74979
 2009-07-08 00:46:57 +00:00
Evan Cheng
5a279bb4b2 Add bfc to armv6t2. 
llvm-svn: 74868
 2009-07-06 22:23:46 +00:00
Evan Cheng
2570d8b541 Added ARM::mls for armv6t2. 
llvm-svn: 74866
 2009-07-06 22:05:45 +00:00
Evan Cheng
f20e4fba49 Add thumb2 sign / zero extend with rotate instructions. 
llvm-svn: 74755
 2009-07-03 01:43:10 +00:00
Evan Cheng
e6989735a6 CommuteChangesDestination() should check if to-be-commuted instruction defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp). 
llvm-svn: 74602
 2009-07-01 08:29:08 +00:00
Evan Cheng
7d78cb531e Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def. 
Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.

llvm-svn: 74601
 2009-07-01 08:19:36 +00:00
Evan Cheng
37503e9671 Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. 
llvm-svn: 74580
 2009-07-01 01:59:31 +00:00
Evan Cheng
28b9e77f19 Temporarily restore the scavenger implicit_def checking code. MachineOperand isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.). 
llvm-svn: 74519
 2009-06-30 09:19:42 +00:00
Evan Cheng
c6c942b70f Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. 
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.

llvm-svn: 74518
 2009-06-30 08:49:04 +00:00
Evan Cheng
093adf3ff9 Implement Thumb2 ldr. 
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420
 2009-06-29 07:51:04 +00:00
David Goodwin
b2c485c6bd ORN and BIC tests. 
llvm-svn: 74289
 2009-06-26 16:20:06 +00:00
Evan Cheng
7883ae3121 Fix tests: Count -> count. 
llvm-svn: 74282
 2009-06-26 07:05:57 +00:00
Evan Cheng
da10be895c Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's looking for duplicates. 
llvm-svn: 74276
 2009-06-26 05:59:16 +00:00
Evan Cheng
4ac765118d Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used. 
llvm-svn: 74228
 2009-06-25 23:34:10 +00:00
Evan Cheng
0cced3daa8 ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS. 
llvm-svn: 74200
 2009-06-25 20:59:23 +00:00
Evan Cheng
b4139189b0 Move thumb and thumb2 tests into separate directories. 
llvm-svn: 74068
 2009-06-24 06:36:07 +00:00
Evan Cheng
eaad82627b Proper patterns for thumb2 shift and rotate instructions. 
llvm-svn: 73987
 2009-06-23 19:39:13 +00:00
Bob Wilson
6db76aaf10 Add support for ARM's Advanced SIMD (NEON) instruction set. 
This is still a work in progress but most of the NEON instruction set
is supported.

llvm-svn: 73919
 2009-06-22 23:27:02 +00:00
Evan Cheng
2814371831 It's coalescer, not coaleser. 
llvm-svn: 73902
 2009-06-22 21:09:17 +00:00
Bob Wilson
0c2c5f65e2 For Darwin on ARMv6 and newer, make register r9 available for use as a 
caller-saved register.

llvm-svn: 73901
 2009-06-22 21:01:46 +00:00
Evan Cheng
2410955c62 Fix another register coalescer crash: forgot to check if the instruction being updated has already been coalesced. 
llvm-svn: 73898
 2009-06-22 20:49:32 +00:00
Evan Cheng
b37e7e24d0 hasFP should return true if frame address is taken. 
llvm-svn: 73893
 2009-06-22 18:38:48 +00:00
Evan Cheng
b45918e5bb Fix PR4419: handle defs of partial uses. 
llvm-svn: 73816
 2009-06-20 04:34:51 +00:00
Evan Cheng
f18de63563 Enable arm pre-allocation load / store multiple optimization pass. 
llvm-svn: 73791
 2009-06-19 23:17:27 +00:00
Eli Friedman
003abaa60d Mark a few Thumb instructions commutable; just happened to spot this 
while experimenting.  I'm reasonably sure this is correct, but please 
tell me if these instructions have some strange property which makes this
change unsafe.

llvm-svn: 73746
 2009-06-19 01:43:08 +00:00
Anton Korobeynikov
7fd29c57a8 Initial support for some Thumb2 instructions. 
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

llvm-svn: 73622
 2009-06-17 18:13:58 +00:00
Anton Korobeynikov
d6004a164c Make the test target-neutral 
llvm-svn: 73547
 2009-06-16 20:25:25 +00:00
Anton Korobeynikov
a74b8323d0 GNU as refuses to assemble "pop {}" instruction. Do not emit such 
(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).

llvm-svn: 73529
 2009-06-16 18:49:08 +00:00
Evan Cheng
a98ff05fca If a val# is defined by an implicit_def and it is being removed, all of the copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead. 
TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block.

llvm-svn: 73478
 2009-06-16 07:12:58 +00:00
Evan Cheng
4b77794613 ifcvt should ignore cfg where true and false successors are the same. 
llvm-svn: 73423
 2009-06-15 21:24:34 +00:00
Evan Cheng
3219c7fbe5 Part 1. 
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.

llvm-svn: 73381
 2009-06-15 08:28:29 +00:00
Evan Cheng
d0a66e438f Add a ARM specific pre-allocation pass that re-schedule loads / stores from 
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.

llvm-svn: 73291
 2009-06-13 09:12:55 +00:00
Evan Cheng
98216808fe If killed register is defined by implicit_def, do not clear it since it's live range may overlap another def of same register. 
llvm-svn: 73255
 2009-06-12 21:34:26 +00:00
Evan Cheng
2f784781aa Mark some pattern-less instructions as neverHasSideEffects. 
llvm-svn: 73252
 2009-06-12 20:46:18 +00:00
Anton Korobeynikov
c82243e658 Add testcase for register scanveger assertion fix in r72755 
(double def due to livevars)

llvm-svn: 73096
 2009-06-08 22:54:15 +00:00
Evan Cheng
ea31ec569b Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then. 
llvm-svn: 72955
 2009-06-05 19:08:58 +00:00
Dan Gohman
5f6f8101d5 Split the Add, Sub, and Mul instruction opcodes into separate 
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt

llvm-svn: 72897
 2009-06-04 22:49:04 +00:00
Evan Cheng
8a6c448ab0 A value defined by an implicit_def can be liven to a use BB. This is unfortunate. But register allocator still has to add it to the live-in set of the use BB. 
llvm-svn: 72888
 2009-06-04 20:25:48 +00:00
Evan Cheng
e3a05e6690 Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface. 
llvm-svn: 72826
 2009-06-04 01:15:28 +00:00
Evan Cheng
82f8fa333e Temporarily revert 72756 for now. 
llvm-svn: 72757
 2009-06-03 07:40:47 +00:00
Evan Cheng
5afbef29fa Fold preceding / trailing base inc / dec into the single load / store as well. 
llvm-svn: 72756
 2009-06-03 06:14:58 +00:00
Bob Wilson
c6726ecca5 Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and 
the stack.  Patch by Sandeep Patel.

llvm-svn: 72106
 2009-05-19 10:02:36 +00:00
Bob Wilson
ec676a76e7 Fix pr4091: Add support for "m" constraint in ARM inline assembly. 
llvm-svn: 72105
 2009-05-19 05:53:42 +00:00
Dan Gohman
904f081ce7 Add nounwind to a few tests. 
llvm-svn: 72002
 2009-05-18 15:16:49 +00:00
Bob Wilson
16f684a429 Fix pr4195: When iterating through predecessor blocks, break out of the loop 
after finding the (unique) layout predecessor.  Sometimes a block may be listed
more than once, and processing it more than once in this loop can lead to
inconsistent values for FtTBB/FtFBB, since the AnalyzeBranch method does not
clear these values.  There's no point in continuing the loop regardless.
The testcase for this is reduced from the 2003-05-02-DependentPHI SingleSource
test.

llvm-svn: 71536
 2009-05-12 03:48:10 +00:00
Bob Wilson
d61f4e70d8 Fix pr4100. Do not remove no-op copies when they are dead. The register 
scavenger gets confused about register liveness if it doesn't see them.
I'm not thrilled with this solution, but it only comes up when there are dead
copies in the code, which is something that hopefully doesn't happen much.

Here is what happens in pr4100: As shown in the following excerpt from the
debug output of llc, the source of a move gets reloaded from the stack,
inserting a new load instruction before the move.  Since that source operand
is a kill, the physical register is free to be reused for the destination
of the move.  The move ends up being a no-op, copying R3 to R3, so it is
deleted.  But, it leaves behind the load to reload %reg1028 into R3, and
that load is not updated to show that it's destination operand (R3) is dead.
The scavenger gets confused by that load because it thinks that R3 is live.

Starting RegAlloc of: %reg1025<def,dead> = MOVr %reg1028<kill>, 14, %reg0, %reg0
  Regs have values: 
  Reloading %reg1028 into R3
  Last use of R3[%reg1028], removing it from live set
  Assigning R3 to %reg1025
  Register R3 [%reg1025] is never used, removing it from live set

Alternative solutions might be either marking the load as dead, or zapping
the load along with the no-op copy.  I couldn't see an easy way to do
either of those, though.

llvm-svn: 71196
 2009-05-07 23:47:03 +00:00
Evan Cheng
0ee6696fd8 Do not use register as base ptr of pre- and post- inc/dec load / store nodes. 
llvm-svn: 71098
 2009-05-06 18:25:01 +00:00
Dan Gohman
a79cce4aef Previously, RecursivelyDeleteDeadInstructions provided an option 
of returning a list of pointers to Values that are deleted. This was
unsafe, because the pointers in the list are, by nature of what
RecursivelyDeleteDeadInstructions does, always dangling. Replace this
with a simple callback mechanism. This may eventually be removed if
all clients can reasonably be expected to use CallbackVH.

Use this to factor out the dead-phi-cycle-elimination code from LSR
utility function, and generalize it to use the
RecursivelyDeleteTriviallyDeadInstructions utility function.

This makes LSR more aggressive about eliminating dead PHI cycles;
adjust tests to either be less trivial or to simply expect fewer
instructions.

llvm-svn: 70636
 2009-05-02 18:29:22 +00:00
Bob Wilson
b3e4773035 Rename file to have the correct suffix. 
llvm-svn: 69380
 2009-04-17 20:40:20 +00:00
Bob Wilson
b8756b00cd Use CallConvLower.h and TableGen descriptions of the calling conventions 
for ARM.  Patch by Sandeep Patel.

llvm-svn: 69371
 2009-04-17 19:07:39 +00:00
Dan Gohman
98aa1d9693 Expand GEPs in ScalarEvolution expressions. SCEV expressions can now 
have pointer types, though in contrast to C pointer types, SCEV
addition is never implicitly scaled. This not only eliminates the
need for special code like IndVars' EliminatePointerRecurrence
and LSR's own GEP expansion code, it also does a better job because
it lets the normal optimizations handle pointer expressions just
like integer expressions.

Also, since LLVM IR GEPs can't directly index into multi-dimensional
VLAs, moving the GEP analysis out of client code and into the SCEV
framework makes it easier for clients to handle multi-dimensional
VLAs the same way as other arrays.

Some existing regression tests show improved optimization.
test/CodeGen/ARM/2007-03-13-InstrSched.ll in particular improved to
the point where if-conversion started kicking in; I turned it off
for this test to preserve the intent of the test.

llvm-svn: 69258
 2009-04-16 03:18:22 +00:00
Dale Johannesen
862ade6f10 Use the output of the asm so the optimizer won't 
delete it.

llvm-svn: 69018
 2009-04-14 01:51:40 +00:00
Chris Lattner
42b8e431b6 move a target-specific test into its directory so it isn't run if you 
don't configure the ARM target in.

llvm-svn: 68843
 2009-04-10 23:58:38 +00:00
Bob Wilson
c53238dff1 Fix pr3954. The register scavenger asserts for inline assembly with 
register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

llvm-svn: 68714
 2009-04-09 17:16:43 +00:00
Bob Wilson
e0e4a070da Add testcase for PR3795. 
llvm-svn: 68620
 2009-04-08 18:00:55 +00:00
Duncan Sands
d0e186d90f Soft float support for FREM. 
llvm-svn: 68614
 2009-04-08 16:20:57 +00:00
Duncan Sands
ee34b0d05d Soft float support for undef. Reported by Xerxes Rånby. 
llvm-svn: 68607
 2009-04-08 13:33:37 +00:00
Bob Wilson
39c7bec188 Handle 'a' modifier in ARM inline assembly. 
Patch by Richard Pennington.

llvm-svn: 68464
 2009-04-06 21:46:51 +00:00
Bob Wilson
5b42ebe6a9 Fix PR3862: Recognize some ARM-specific constraints for immediates in inline 
assembly.

llvm-svn: 68218
 2009-04-01 17:58:54 +00:00
Evan Cheng
b3196f1298 Do not emit comments unless -asm-verbose. 
llvm-svn: 67580
 2009-03-24 00:17:40 +00:00
Chris Lattner
a5368fd283 add no-unwind, remove duplicate run line. 
llvm-svn: 66775
 2009-03-12 05:56:37 +00:00
Evan Cheng
3c9a084a1b ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types. 
llvm-svn: 66429
 2009-03-09 19:15:00 +00:00
Evan Cheng
67ccd79e39 Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly. 
llvm-svn: 66365
 2009-03-08 04:02:49 +00:00
Evan Cheng
483ece4d2e If a MI uses the same register more than once, only mark one of them as 'kill'. 
llvm-svn: 66363
 2009-03-08 03:58:35 +00:00
Evan Cheng
9c3ce7905e Last commit accidentially deleted this code. 
llvm-svn: 65679
 2009-02-28 06:02:14 +00:00
Evan Cheng
86fc9440db The last commit was overly conservative. It's ok to reuse value that's already marked livein. 
llvm-svn: 65498
 2009-02-26 03:02:21 +00:00
Evan Cheng
41687ff389 If a use operand is marked isKill, don't forget to add kill to its live interval as well. 
llvm-svn: 65279
 2009-02-22 08:35:56 +00:00
Evan Cheng
2e0cf05ad2 A couple of places where reused use operands should be marked kill. This is exposed by recent availability fallthrough changes. 
llvm-svn: 64745
 2009-02-17 06:41:03 +00:00
Evan Cheng
19a1ba3680 Replace one of burr scheduling heuristic with something more sensible. Now calcMaxScratches simply compute the number of true data dependencies. This actually improve a couple of tests in dejagnu suite as many tests in llvm nightly test suite. 
llvm-svn: 64369
 2009-02-12 08:59:45 +00:00
Evan Cheng
5be1afd928 Fix PR3457: Ignore control successors when looking for closest scheduled successor. A control successor doesn't read result(s) produced by the scheduling unit being evaluated. 
llvm-svn: 64210
 2009-02-10 08:30:11 +00:00
Evan Cheng
3f98669da2 Re-enable machine sinking pass now that the coalescer bugs and the AnalyzeBrnach bug are fixed. 
llvm-svn: 64126
 2009-02-09 08:45:39 +00:00
Bill Wendling
4ed0306d6f Revert r63999. It was breaking self-hosting builds. 
llvm-svn: 64062
 2009-02-08 00:58:05 +00:00
Evan Cheng
62694a52fe Enable machine sinking pass in non-fast mode. 
llvm-svn: 63999
 2009-02-07 01:57:46 +00:00
Evan Cheng
b36e3e34e7 Turn on machine LICM in non-fast mode. 
llvm-svn: 63855
 2009-02-05 08:46:33 +00:00
Rafael Espindola
0aba6c9435 Add the private linkage. 
llvm-svn: 62279
 2009-01-15 20:18:42 +00:00
Evan Cheng
5c92d425a9 Clean up some ARM GV asm printing out; minor fixes to match what gcc does. 
llvm-svn: 60621
 2008-12-06 02:00:55 +00:00
Evan Cheng
2805dcc9a0 - Register scavenger should use MachineRegisterInfo and internal map to find the first use of a register after a given machine instruction. 
- When scavenging a register, in addition to the spill, insert a restore before the first use.
- Abort if client is looking to scavenge a register even when a previously scavenged register is still live.

llvm-svn: 59697
 2008-11-20 02:32:35 +00:00
Evan Cheng
145b3db050 Register scavenger should process early clobber defs first. A dead early clobber def should not interfere with a normal def which happens one slot later. 
llvm-svn: 59559
 2008-11-18 22:28:38 +00:00
Evan Cheng
59112bc108 Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls. 
llvm-svn: 58725
 2008-11-04 22:19:55 +00:00
Evan Cheng
45496b349f Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes. 
llvm-svn: 58714
 2008-11-04 19:57:48 +00:00
Devang Patel
47a504c87c Implement function notes as function attributes. 
llvm-svn: 56716
 2008-09-26 23:51:19 +00:00
Evan Cheng
d3225118a6 Unallocatable registers do not have live intervals. 
llvm-svn: 56287
 2008-09-17 18:36:25 +00:00
Dan Gohman
f38d63884f Re-enable SelectionDAG CSE for calls. It matters in the case of 
libcalls, as in this testcase on ARM.

llvm-svn: 56226
 2008-09-15 19:46:03 +00:00
Evan Cheng
db1693cb14 Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#. 
llvm-svn: 56199
 2008-09-15 06:28:41 +00:00
Evan Cheng
ba11945234 Legalizer was missing code that expand fpow to a libcall. 
llvm-svn: 56028
 2008-09-09 23:02:14 +00:00
Evan Cheng
4708df4776 It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool. 
llvm-svn: 54519
 2008-08-08 06:56:16 +00:00
Anton Korobeynikov
52d0ff92cc Print section flags ok on platforms, which use '@' as comment string. Fix test. 
llvm-svn: 54460
 2008-08-07 09:55:06 +00:00
Owen Anderson
4c7ea0c270 This check is unnecessary, and getting rid of it removes a use of -disable-correct-folding. 
llvm-svn: 54355
 2008-08-05 17:52:54 +00:00
Owen Anderson
7fca48d0bd Remove the need for -disable-correct-folding from this test. 
llvm-svn: 54354
 2008-08-05 17:49:52 +00:00
Owen Anderson
231111faf9 Update these tests to work by disabling the new correct CFG generation. This flag should ONLY be used to for tests like these. 
llvm-svn: 54334
 2008-08-04 23:55:29 +00:00
Evan Cheng
d4eb684258 Teach ARM isLegalAddressingMode to handle unknown type without crashing. This fixes pr2589. 
llvm-svn: 54004
 2008-07-25 00:55:17 +00:00
Duncan Sands
ef45c602b6 Softfloat support for FDIV. Patch by 
Richard Pennington.

llvm-svn: 53773
 2008-07-18 21:18:48 +00:00
Gabor Greif
807c2df887 sabre brings to my attention that the 'tr' suffix is also obsolete 
llvm-svn: 51349
 2008-05-20 21:00:03 +00:00
Gabor Greif
d8a4dbb5da Rename the last test with .llx extension to .ll, resolve duplicate test by renaming to isnan2. Now that no test has llx ending there is no need to search for them from dg.exp too. 
llvm-svn: 51328
 2008-05-20 19:52:04 +00:00
Evan Cheng
55e3957c96 More local spiller complexity! 
If local spiller optimization turns some instruction into an identity copy, it will be removed. If the output register happens to be dead (and source is obviously killed), transfer the kill / dead information to last use / def in the same MBB.

llvm-svn: 51306
 2008-05-20 08:13:21 +00:00
Evan Cheng
408425f0e0 Don't spill dead def. 
llvm-svn: 51305
 2008-05-20 08:10:37 +00:00
Evan Cheng
6e52146f16 If a PHI node has a single implicit_def source, replace it with an implicit_def instead of a copy. 
llvm-svn: 49543
 2008-04-11 17:54:45 +00:00
Evan Cheng
56ca7e285a New test. 
llvm-svn: 49514
 2008-04-10 23:49:09 +00:00
Evan Cheng
d7d1c94e67 1. IMPLICIT_DEF can *re-define* any register. 
2. Coalescer can now create an interesting situation where a register def can
   reaches itself without being killed.

llvm-svn: 49246
 2008-04-05 01:27:09 +00:00
Evan Cheng
c2f298f318 More soft fp fixes. 
llvm-svn: 49016
 2008-04-01 02:18:22 +00:00
Evan Cheng
a38ae9c502 Unbreak ARM / Thumb soft FP support. 
llvm-svn: 49012
 2008-04-01 01:50:16 +00:00
Evan Cheng
5f74d1a8dc Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI. 
llvm-svn: 48024
 2008-03-07 20:12:54 +00:00
Evan Cheng
9c77211639 Constant fold SIGN_EXTEND_INREG with ashr not lshr. 
llvm-svn: 47992
 2008-03-06 08:20:51 +00:00
Bill Wendling
246237f14f DCE'ed this testcase. 
llvm-svn: 47760
 2008-02-29 19:28:11 +00:00
Bill Wendling
d0f85a5ca3 If we reload a virtual register that's already been assigned, we want to mark 
that instruction as its "last use". This fixes PR1925.

llvm-svn: 47758
 2008-02-29 18:52:01 +00:00
Tanya Lattner
03755061ae Remove llvm-upgrade. 
llvm-svn: 47238
 2008-02-17 20:02:20 +00:00
Evan Cheng
6b03a1aeb9 It's PR1925, not PR1609. 
llvm-svn: 46825
 2008-02-06 22:07:17 +00:00
Evan Cheng
2091d9a2e8 Fix a number of local register allocator issues: PR1609. 
llvm-svn: 46821
 2008-02-06 19:16:53 +00:00
Chris Lattner
26a8116f49 Update this test. Due to dag combiner improvements, we now compile 
f7/f11 to:

_f7:
	eor r0, r0, #2, 2 @ -2147483648
	bx lr
_f11:
	bic r0, r0, #2, 2 @ -2147483648
	bx lr

instead of:

_f7:
	fmsr s0, r0
	fnegs s0, s0
	fmrs r0, s0
	bx lr

_f11:
	fmsr s0, r0
	fabss s0, s0
	fmrs r0, s0
	bx lr

llvm-svn: 46423
 2008-01-27 23:26:37 +00:00
Evan Cheng
18c39c03a7 Remove xfail. This is fixed. 
llvm-svn: 45254
 2007-12-20 02:25:21 +00:00
Evan Cheng
d53f72dfb1 Turning simple splitting on. Start testing new coalescer heuristics as new llcbeta. 
llvm-svn: 44660
 2007-12-06 08:54:31 +00:00
Evan Cheng
1d289d0146 Fix for PR1831: if all defs of an interval are re-materializable, then it's a preferred spill candiate. 
llvm-svn: 44644
 2007-12-06 00:01:56 +00:00
Evan Cheng
1aa45b56a3 Update tests. 
llvm-svn: 44435
 2007-11-29 10:03:54 +00:00
Chris Lattner
a9dc7d650b update this test after the fmrrd fix 
llvm-svn: 44393
 2007-11-28 05:27:07 +00:00
Tanya Lattner
c33660d278 Fix bug in regression tests that ignored stderr output in RUN lines. Updated tests and fixed broken run lines. 
XFAILed 3 arm regressions (will file bugs)

llvm-svn: 44389
 2007-11-28 04:57:00 +00:00
Chris Lattner
98fe074d3d commit testcase I forgot to svn add. 
llvm-svn: 44383
 2007-11-27 22:43:37 +00:00
Lauro Ramos Venancio
d8f2190c19 [ARM] Implement __builtin_thread_pointer. 
llvm-svn: 43892
 2007-11-08 17:20:05 +00:00
Lauro Ramos Venancio
f5081ba980 [ARM] Fix code generation for: 
static __thread struct {
    int a;
    int b;
} teste = {0, 0};

llvm-svn: 43722
 2007-11-05 18:33:37 +00:00
Evan Cheng
252d9ddb4d Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4. 
llvm-svn: 43234
 2007-10-22 22:11:27 +00:00
Chris Lattner
a7666b08ad new testcase 
llvm-svn: 42953
 2007-10-13 06:56:18 +00:00
Evan Cheng
66bccf335b Disable if-conversion for this test. 
llvm-svn: 42170
 2007-09-20 18:06:22 +00:00
Evan Cheng
ae2dbcb25f -enable-arm-if-conversion is gone. 
llvm-svn: 42169
 2007-09-20 18:03:23 +00:00
Dale Johannesen
f9ca7b6094 Change all floating constants that are not exactly 
representable to use hex format.

llvm-svn: 41722
 2007-09-05 17:50:36 +00:00
Duncan Sands
2e32997f97 Testcases for PR1628. 
llvm-svn: 41719
 2007-09-05 11:53:04 +00:00
Lauro Ramos Venancio
9f9e5b3971 Implement FPOWI ExpandOp. 
Fix PR1287.

llvm-svn: 41112
 2007-08-15 22:13:27 +00:00
Evan Cheng
46b797bbed Test case for PR1609. 
llvm-svn: 41110
 2007-08-15 20:30:10 +00:00
Dan Gohman
74e688fce1 This test used "wc | grep ..."; convert it to use the count script. 
llvm-svn: 41101
 2007-08-15 13:55:47 +00:00
Dan Gohman
34263074cb Convert tests using "grep -c ... | grep ..." to use the count script. 
llvm-svn: 41100
 2007-08-15 13:49:33 +00:00
Dan Gohman
794fa1f8f7 Convert tests using "| wc -l | grep ..." to use the count script. 
llvm-svn: 41097
 2007-08-15 13:36:28 +00:00
Evan Cheng
92df220df4 New test. 
llvm-svn: 41087
 2007-08-14 23:34:50 +00:00
Lauro Ramos Venancio
1ef30713de Expand unaligned loads/stores when the target doesn't support them. (PR1548) 
llvm-svn: 40682
 2007-08-01 19:34:21 +00:00
Reid Spencer
44d34e9b61 For PR1553: 
Change the keywords for the zext and sext parameter attributes to be 
zeroext and signext so they don't conflict with the keywords for the
instructions of the same name. This gets around the ambiguity.

llvm-svn: 40069
 2007-07-19 23:13:04 +00:00
Dan Gohman
b73f9e21e9 Add explicit triples to these tests so that llc behaves as expected on 
non-Apple hosts.

llvm-svn: 38455
 2007-07-09 13:42:32 +00:00
John Criswell
57e5ed4b5a Convert .cvsignore files 
llvm-svn: 37801
 2007-06-29 16:35:07 +00:00
Dan Gohman
ad9cbaba40 Fix an assertion failure in legalizing bitcast operators on targets where 
vectors are split down to single elements as part of legalization.

llvm-svn: 37785
 2007-06-29 00:09:08 +00:00
Evan Cheng
e139181e1c Fix tests. 
llvm-svn: 37693
 2007-06-21 18:22:42 +00:00
Evan Cheng
56938a1fd8 New tests. 
llvm-svn: 37686
 2007-06-21 07:40:00 +00:00
Evan Cheng
d9dca9363c Added some if-conversion tests. 
llvm-svn: 37672
 2007-06-20 18:26:15 +00:00
Lauro Ramos Venancio
afcdd2546e Add a test for PR1424. 
llvm-svn: 37372
 2007-05-31 18:36:07 +00:00
Evan Cheng
e69eb98312 Add a new test case. 
llvm-svn: 37317
 2007-05-24 02:31:15 +00:00
Dale Johannesen
53a2f3b4e4 new testcases for -enable-tail-merge default handling 
llvm-svn: 37287
 2007-05-22 17:19:23 +00:00
Chris Lattner
cba64c6a47 testcase that crashes llc 
llvm-svn: 37059
 2007-05-15 01:13:42 +00:00
Evan Cheng
bdc4c1ebc5 Test for PR1406. 
llvm-svn: 37051
 2007-05-14 21:12:43 +00:00
Lauro Ramos Venancio
c6d71fb584 Enable aliases on arm-linux. 
llvm-svn: 37042
 2007-05-14 18:32:56 +00:00
Dale Johannesen
3099de1972 Another test for tail mergeing 
llvm-svn: 36967
 2007-05-10 01:04:28 +00:00
Evan Cheng
d70be3bdee Can't fold bit_convert into truncating store. 
llvm-svn: 36963
 2007-05-09 21:54:34 +00:00
Dale Johannesen
e6b2d045cc testcase for CodeGenPrepare bug fixed yesterday 
llvm-svn: 36940
 2007-05-08 17:44:36 +00:00
Chris Lattner
63ddb501d3 move this out of Codegen/Generic, because it requires the ARM backend to be 
linked into llc

llvm-svn: 36919
 2007-05-08 02:19:56 +00:00
Evan Cheng
cd3d36aaa6 Fix tests. 
llvm-svn: 36913
 2007-05-07 21:50:07 +00:00
Evan Cheng
8a0c9364bc Add some tests for (conv (load x)) -> (load (conv*)x) xform. 
llvm-svn: 36912
 2007-05-07 21:49:35 +00:00
Lauro Ramos Venancio
236cf4a51b Fix PR1390. 
Don't spill extra register to align the stack.

llvm-svn: 36814
 2007-05-05 23:44:41 +00:00
Chris Lattner
9808f834ba remove xfailed testcase (attached to pr) 
llvm-svn: 36797
 2007-05-05 21:57:34 +00:00
Evan Cheng
d5ddb11361 Test load global in static mode. 
llvm-svn: 36719
 2007-05-04 00:29:34 +00:00
Evan Cheng
f408ed9976 New test case. 
llvm-svn: 36717
 2007-05-03 23:53:36 +00:00
Dale Johannesen
d28d0bac2a Evan's patch to avoid FPreg->intreg copy for cvt; store to mem 
llvm-svn: 36693
 2007-05-03 20:54:42 +00:00
Chris Lattner
c777983d43 match a reassociated form of fnmul 
llvm-svn: 36659
 2007-05-03 00:31:40 +00:00
Evan Cheng
5793434ac3 Test a dag combiner crasher. 
llvm-svn: 36605
 2007-05-01 00:40:38 +00:00
Reid Spencer
6045236615 For PR1370: 
Rearrange some tests so that if PowerPC is not being built we don't try to
run PowerPC specific tests.

llvm-svn: 36587
 2007-04-30 05:11:58 +00:00
Chris Lattner
287a590e95 update syntax 
llvm-svn: 36531
 2007-04-28 06:03:12 +00:00
Lauro Ramos Venancio
8226832ec6 fix the test tls1. 
llvm-svn: 36517
 2007-04-27 21:23:17 +00:00
Lauro Ramos Venancio
0917ab8b29 add TLS tests. 
llvm-svn: 36516
 2007-04-27 21:08:48 +00:00
Lauro Ramos Venancio
f9641d332a In Thumb mode, the frame register must be R7. 
llvm-svn: 36512
 2007-04-27 17:58:03 +00:00
Lauro Ramos Venancio
d922b8ca9b remember to emit weak reference in one more case. 
llvm-svn: 36438
 2007-04-25 14:50:40 +00:00
Lauro Ramos Venancio
f8b49e5ee0 Implement PIC for arm-linux. 
llvm-svn: 36324
 2007-04-22 00:04:12 +00:00
Reid Spencer
6dbda77071 Use the llvm_supports_target function to prevent running of tests for 
targets that LLVM is not configured to support.

llvm-svn: 36315
 2007-04-21 20:41:27 +00:00
Evan Cheng
1f054dca9e Fix test. 
llvm-svn: 36150
 2007-04-16 18:55:46 +00:00
Reid Spencer
df17fa8ef9 For PR1319: 
Remove && from the end of the lines to prevent tests from throwing run
lines into the background. Also, clean up places where the same command
is run multiple times by using a temporary file.

llvm-svn: 36142
 2007-04-16 17:36:08 +00:00
Lauro Ramos Venancio
806f696b15 Fix hello.ll test. 
llvm-svn: 36141
 2007-04-16 17:08:00 +00:00
Lauro Ramos Venancio
de6ca2dfe1 Fix align test. 
llvm-svn: 36140
 2007-04-16 16:57:47 +00:00
Reid Spencer
d93b834b52 For PR1319: 
Fix test syntax per new rules.

llvm-svn: 36133
 2007-04-16 15:15:52 +00:00
Reid Spencer
8f0fe6f2cf For PR1336: 
XFAIL tests covered by the PR. These will be un-XFAILed as they are fixed.

llvm-svn: 36093
 2007-04-15 23:00:46 +00:00
Reid Spencer
47d1aeeb51 For PR1319: Upgrade to new test harness. 
llvm-svn: 36086
 2007-04-15 20:48:50 +00:00
Reid Spencer
b6fe525070 For PR1319: Upgrade to use new test harness 
llvm-svn: 36076
 2007-04-15 19:11:47 +00:00
Chris Lattner
87995a803b fix test for linux hosts. 
llvm-svn: 36026
 2007-04-14 23:04:30 +00:00
Chris Lattner
cbe92494fd xfail this for now 
llvm-svn: 35973
 2007-04-13 22:20:27 +00:00
Chris Lattner
ef78f89fa5 new lsr testcase 
llvm-svn: 35971
 2007-04-13 20:38:14 +00:00
Reid Spencer
56b310ae49 Make the llvm-runtest function much more amenable by eliminating all the 
global variables that needed to be passed in. This makes it possible to
add new global variables with only a couple changes (Makefile and llvm-dg.exp)
instead of touching every single dg.exp file.

llvm-svn: 35918
 2007-04-11 19:56:59 +00:00
Chris Lattner
e557a69c34 this got better 
llvm-svn: 35908
 2007-04-11 16:12:27 +00:00
Chris Lattner
e827f7dfe6 new testcases for integer abs function 
llvm-svn: 35880
 2007-04-11 05:02:57 +00:00
Evan Cheng
89768803e7 Better still. 
llvm-svn: 35663
 2007-04-04 08:49:40 +00:00
Evan Cheng
8cd7d8dc77 Fix test case. 
llvm-svn: 35662
 2007-04-04 07:41:33 +00:00
Evan Cheng
3af3f8e696 These got better. 
llvm-svn: 35661
 2007-04-04 07:41:15 +00:00
Evan Cheng
5bd266a791 New asm test case. 
llvm-svn: 35641
 2007-04-04 00:15:17 +00:00
Evan Cheng
8a281b1e57 New test case. 
llvm-svn: 35636
 2007-04-03 23:40:54 +00:00
Evan Cheng
f9da057ef8 New test case. 
llvm-svn: 35628
 2007-04-03 21:38:03 +00:00
Chris Lattner
caf2381689 new testcase, where we should use a negative stride 
llvm-svn: 35608
 2007-04-03 00:13:16 +00:00
Evan Cheng
b114ed90de New test case. 
llvm-svn: 35599
 2007-04-02 18:47:13 +00:00
Chris Lattner
c597fc9196 new testcase. 
llvm-svn: 35591
 2007-04-02 06:33:10 +00:00
Lauro Ramos Venancio
7e21418680 - Divides the comparisons in two types: comparisons that only use N and Z 
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).

llvm-svn: 35573
 2007-04-02 01:30:03 +00:00
Evan Cheng
aca424091b Missing '&&' 
llvm-svn: 35519
 2007-03-30 22:03:49 +00:00
Evan Cheng
5e161b7fb5 Test case for PR1279 (part 2). 
llvm-svn: 35511
 2007-03-30 20:15:22 +00:00
Reid Spencer
50ee6b8557 Remove use of implementation keyword. 
llvm-svn: 35412
 2007-03-28 02:38:26 +00:00
Evan Cheng
7fc3f900a2 Added a test case for PR1279. 
llvm-svn: 35398
 2007-03-28 01:32:57 +00:00
Evan Cheng
ce2097be73 Test case for PR1266. 
llvm-svn: 35367
 2007-03-26 22:58:35 +00:00
Evan Cheng
9992bbc5a0 Another test case. 
llvm-svn: 35255
 2007-03-22 01:55:16 +00:00
Evan Cheng
1a651088b1 Test case for PR1257 
llvm-svn: 35253
 2007-03-22 01:52:57 +00:00
Evan Cheng
ecfd152e0d New test case. 
llvm-svn: 35240
 2007-03-21 20:14:56 +00:00
Lauro Ramos Venancio
11d7d3fcaf bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218
 2007-03-20 17:57:23 +00:00
Reid Spencer
c124adcc12 For PR1258: 
Revise numeric value references to accommodate collapsed type planes.

llvm-svn: 35170
 2007-03-19 18:27:35 +00:00
Evan Cheng
283468b827 GEP index sink test case. 
llvm-svn: 35131
 2007-03-17 03:18:32 +00:00
Evan Cheng
1464c63d5d ARM isel should match ldr x +/- x * (2^n) to ldr [x, +/- x, lsl #log2(n)]. 
llvm-svn: 35114
 2007-03-14 23:26:40 +00:00
Evan Cheng
0fe7224a46 New test. 
llvm-svn: 35091
 2007-03-13 23:31:47 +00:00
Evan Cheng
8685e7d770 Test inline asm modifier 'c'. 
llvm-svn: 35036
 2007-03-08 22:45:31 +00:00
Evan Cheng
511c8f6a24 Fix test case. 
llvm-svn: 35029
 2007-03-08 19:27:32 +00:00