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Author SHA1 Message Date
Duncan Sands
4d240b1e9e Useful script for finding regressions in the nightly testsuite. 
I think it was written by Pawel Worach.

llvm-svn: 128268
 2011-03-25 07:17:44 +00:00
Bill Wendling
fbff8d1e52 Remove redundant compression option. 
llvm-svn: 128267
 2011-03-25 06:43:59 +00:00
Andrew Trick
651a3701f9 Fix for -pre-RA-sched=source. 
Yet another case of unchecked NULL node (for physreg copy).
May fix PR9509.

llvm-svn: 128266
 2011-03-25 06:40:55 +00:00
Nick Lewycky
3772213010 No functionality change, just adjust some whitespace for coding style compliance. 
llvm-svn: 128257
 2011-03-25 06:05:50 +00:00
Nick Lewycky
66eaeb513a No functionality change. Fix up some whitespace and switch out "" for '' when 
printing a single character.

llvm-svn: 128256
 2011-03-25 06:04:26 +00:00
Jakob Stoklund Olesen
e20f22be07 Ignore special ARM allocation hints for unexpected register classes. 
Add an assertion to linear scan to prevent it from allocating registers outside
the register class.

<rdar://problem/9183021>

llvm-svn: 128254
 2011-03-25 01:48:18 +00:00
Johnny Chen
1f29c2775d Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed), 
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.

llvm-svn: 128252
 2011-03-25 01:09:48 +00:00
Johnny Chen
a4f73530a5 delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that. 
llvm-svn: 128249
 2011-03-25 00:17:42 +00:00
Johnny Chen
4a55a733b8 The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since 
the change to ("tLDMIA", "tLDMIA_UPD").  Update the conflict resolution code and add
test cases for that.

llvm-svn: 128247
 2011-03-24 23:42:31 +00:00
Johnny Chen
6345e6a882 The ARM disassembler was confused with the 16-bit tSTMIA instruction. 
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.

llvm-svn: 128246
 2011-03-24 23:21:14 +00:00
Devang Patel
c6ed54c434 Move test in x86 specific area. 
llvm-svn: 128245
 2011-03-24 22:39:09 +00:00
Matt Beaumont-Gay
7e9b4f0934 Suppress an unused variable warning in -asserts builds 
llvm-svn: 128244
 2011-03-24 22:05:48 +00:00
Johnny Chen
9672fe0126 Handle the added VBICiv*i* NEON instructions, too. 
llvm-svn: 128243
 2011-03-24 22:04:39 +00:00
Eric Christopher
d0fd06aeda Testcase for llvm-gcc commit r128230. 
llvm-svn: 128242
 2011-03-24 21:59:03 +00:00
Johnny Chen
69bc7c288b Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer! 
llvm-svn: 128241
 2011-03-24 21:42:55 +00:00
Johnny Chen
1fc160fa19 T2 Load/Store Multiple: 
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add a test case.

llvm-svn: 128240
 2011-03-24 21:36:56 +00:00
Benjamin Kramer
a9c4afdeec Plug a leak in the arm disassembler and put the tests back. 
llvm-svn: 128238
 2011-03-24 21:14:28 +00:00
Bruno Cardoso Lopes
a5de5df6d8 Add asm parsing support w/ testcases for strex/ldrex family of instructions 
llvm-svn: 128236
 2011-03-24 21:04:58 +00:00
Johnny Chen
ef99d9b9eb Remove these two test files as they cause llvm-i686-linux-vg_leak build to fail 'test-llvm'. 
These two are test cases which should result in 'invalid instruction encoding' from running llvm-mc -disassemble.

llvm-svn: 128235
 2011-03-24 20:56:23 +00:00
Johnny Chen
ae5d27987a ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled. 
Set the encoding bits to {0,?,?,0}, not 0.  Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.

llvm-svn: 128234
 2011-03-24 20:42:48 +00:00
Devang Patel
4909f41ec5 Keep track of directory namd and fIx regression caused by Rafael's patch r119613. 
A better approach would be to move source id handling inside MC.

llvm-svn: 128233
 2011-03-24 20:30:50 +00:00
Jim Grosbach
213800d44b Clean up assembly statement separator support. 
The MC asm lexer wasn't honoring a non-default (anything but ';') statement
separator. Fix that, and generalize a bit to support multi-character
statement separators.

llvm-svn: 128227
 2011-03-24 18:46:34 +00:00
Johnny Chen
f6655e82b3 The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the 
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function.  Add a test case.

llvm-svn: 128226
 2011-03-24 18:40:38 +00:00
Johnny Chen
154393018f Add comments to the handling of opcode CPS3p to reject invalid instruction encoding, 
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.

llvm-svn: 128220
 2011-03-24 17:04:22 +00:00
Andrew Trick
a50ee2e148 revert r128199 until it can be made to work with Frontend/dependency-gen.c. 
llvm-svn: 128218
 2011-03-24 16:43:37 +00:00
Cameron Zwarich
1991677a8e Debug intrinsics must be skipped at the beginning and ends of blocks, lest they 
affect the generated code.

llvm-svn: 128217
 2011-03-24 16:34:59 +00:00
Jay Foad
008631e572 Fix typo in comment. 
llvm-svn: 128216
 2011-03-24 16:18:19 +00:00
Chris Lattner
3385be615f fix description, PR9542 
llvm-svn: 128214
 2011-03-24 16:13:31 +00:00
Cameron Zwarich
c2a32b3c5c It is enough for the CallInst to have no uses to be made a tail call with a ret 
void; it doesn't need to have a void type.

llvm-svn: 128212
 2011-03-24 15:54:11 +00:00
Devang Patel
f432e2c2df s/UpdateDT/ModifiedDT/g 
llvm-svn: 128211
 2011-03-24 15:35:25 +00:00
NAKAMURA Takumi
cabdaca3c7 Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets. 
FIXME: Some cleanups would be needed.
llvm-svn: 128206
 2011-03-24 07:07:00 +00:00
NAKAMURA Takumi
cb3235ade0 llvm-stub.cpp: mingw-w64 tweak. 
llvm-svn: 128205
 2011-03-24 07:06:45 +00:00
Evan Cheng
9d660cc8b7 Add comment to clarify what MachineConstantPoolEntry::isMachineConstantPoolEntry() means. 
llvm-svn: 128204
 2011-03-24 06:28:45 +00:00
Evan Cheng
1502266aba Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntry 
entries being compared may not be ARMConstantPoolValue. Without checking
whether they are ARMConstantPoolValue first, and if the stars and moons
are aligned properly, the equality test may return true (when the first few
words of two Constants' values happen to be identical) and very bad things can
happen.

rdar://9125354

llvm-svn: 128203
 2011-03-24 06:20:03 +00:00
Michael J. Spencer
3314c920a5 Remove all uses of PATH_MAX and MAXPATHLEN from PathV2. 
llvm-svn: 128199
 2011-03-24 05:23:40 +00:00
Cameron Zwarich
4d1c5fe9ae Do early taildup of ret in CodeGenPrepare for potential tail calls that have a 
void return type. This fixes PR9487.

llvm-svn: 128197
 2011-03-24 04:52:10 +00:00
Cameron Zwarich
6c983bf746 Use an early return instead of a long if block. 
llvm-svn: 128196
 2011-03-24 04:52:07 +00:00
Cameron Zwarich
6862665125 When UpdateDT is set, DT is invalid, which could cause problems when trying to 
use it later. I couldn't make a test that hits this with the current code.

llvm-svn: 128195
 2011-03-24 04:52:04 +00:00
Cameron Zwarich
6633f15fad Check for TLI so that -codegenprepare can be used from opt. 
llvm-svn: 128194
 2011-03-24 04:51:51 +00:00
Johnny Chen
e61d22bde8 CPS3p: Let's reject impossible imod values by returning false from the DisassembleMiscFrm() function. 
Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing)

Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

Before:
	cpsUnknown imod operand
UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123!

After:
/Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding
0x93 0x1c 0x2 0xf1
^

llvm-svn: 128192
 2011-03-24 02:24:36 +00:00
Johnny Chen
404fb6c07f Load/Store Multiple: 
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add two test cases.

llvm-svn: 128191
 2011-03-24 01:40:42 +00:00
Johnny Chen
0d55ce3734 STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821). 
We now tag them as IndexModePost.

llvm-svn: 128189
 2011-03-24 01:07:26 +00:00
Johnny Chen
f8507c96f1 The r128103 fix to cope with the removal of addressing modes from the MC instructions 
were incomplete.  The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.

llvm-svn: 128186
 2011-03-24 00:28:38 +00:00
Jim Grosbach
f13cc12ddb Runtime dylib simple ARM 24-bit branch relocation support. 
llvm-svn: 128184
 2011-03-23 23:35:17 +00:00
Devang Patel
2cea16e9bb Enable GlobalMerge on darwin. 
llvm-svn: 128183
 2011-03-23 23:34:19 +00:00
Jim Grosbach
06d4707c37 Fix comments. 
llvm-svn: 128182
 2011-03-23 23:32:48 +00:00
Andrew Trick
80893981d6 Revert r128175. 
I'm backing this out for the second time. It was supposed to be fixed by r128164, but the mingw self-host must be defeating the fix.

llvm-svn: 128181
 2011-03-23 23:11:02 +00:00
Evan Cheng
6e799c3c58 Cmp peephole optimization isn't always safe for signed arithmetics. 
int tries = INT_MAX;    
while (tries > 0) {
      tries--;
}

The check should be:
        subs    r4, #1
        cmp     r4, #0
        bgt     LBB0_1

The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop
canonicalization apparently does in this case). cmp #0 would have cleared
it while not changing the N and Z bits. Since BGT is dependent on the V
bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0.

rdar://9172742

llvm-svn: 128179
 2011-03-23 22:52:04 +00:00
Eli Friedman
76fcfaab12 PR9535: add support for splitting and scalarizing vector ISD::FP_ROUND. 
Also cleaning up some duplicated code while I'm here.

llvm-svn: 128176
 2011-03-23 22:18:48 +00:00
Andrew Trick
a7b48f34b1 Reapply Eli's r127852 now that the pre-RA scheduler can spill EFLAGS. 
(target-specific branchless method for double-width relational comparisons on x86)

llvm-svn: 128175
 2011-03-23 22:16:02 +00:00