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Commit Graph

2191 Commits

Author SHA1 Message Date
Evan Cheng
4e3c0e66f7 Eliminate unused instruction classes.
llvm-svn: 97617
2010-03-03 00:43:15 +00:00
Johnny Chen
7be11bea79 Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy for
disassembly only.

llvm-svn: 97614
2010-03-03 00:16:28 +00:00
Johnny Chen
96f78fcb96 Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only.
llvm-svn: 97595
2010-03-02 22:11:06 +00:00
Johnny Chen
dc6ad68a6d Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as from
the opc string passed in, since it's a given from the class inheritance of T2sI.
The fixed the extra 's' in adcss & sbcss when disassembly printing.

llvm-svn: 97582
2010-03-02 19:38:59 +00:00
Johnny Chen
88f05c26a5 Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.

llvm-svn: 97573
2010-03-02 18:14:57 +00:00
Johnny Chen
9b5f5645e4 AL is an optional mnemonic extension for always, except in IT instructions.
Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing.

Ref: A8.3 Conditional execution
llvm-svn: 97571
2010-03-02 17:57:15 +00:00
Johnny Chen
ddbf29a06c Change some asm shift opcode strings to lowercase.
llvm-svn: 97567
2010-03-02 17:03:18 +00:00
Xerxes Ranby
8f57e7907a fix typo add missing (
llvm-svn: 97565
2010-03-02 13:42:03 +00:00
Xerxes Ranby
1adef1fad2 Unbreak llvm-arm-linux buildbot and fix PR5309.
llvm-svn: 97564
2010-03-02 13:26:18 +00:00
Chris Lattner
1707a88a2c Sink InstructionSelect() out of each target into SDISel, and rename it
DoInstructionSelection.  Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.

Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.

 17 files changed, 114 insertions(+), 430 deletions(-)

llvm-svn: 97555
2010-03-02 06:34:30 +00:00
Eric Christopher
ca6b8de375 Only save vector registers if we've defined for the vector registers.
Fixes PR5309.

llvm-svn: 97554
2010-03-02 06:25:00 +00:00
Bill Wendling
5990930d72 Remove dead parameter passing.
llvm-svn: 97536
2010-03-02 01:55:18 +00:00
Johnny Chen
37f3172799 Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the W
bit should be set to 0 instead of 1.

llvm-svn: 97481
2010-03-01 19:22:00 +00:00
Dan Gohman
99c6bcbc13 The mayHaveSideEffects flag is no longer used.
llvm-svn: 97348
2010-02-27 23:47:46 +00:00
Johnny Chen
0f20ffea08 Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]

llvm-svn: 97276
2010-02-26 22:04:29 +00:00
Johnny Chen
47fd2a4774 Added the following 32-bit Thumb instructions for disassembly only: SMC, RFE,
and SRS.

llvm-svn: 97164
2010-02-25 20:25:24 +00:00
Johnny Chen
8737e46553 Added the 32-bit Thumb instructions (BXJ) for disassembly only.
llvm-svn: 97163
2010-02-25 19:05:29 +00:00
Johnny Chen
b05edcba36 Added the 32-bit Thumb instructions (MRS and MSR) for disassembly only.
llvm-svn: 97159
2010-02-25 18:46:43 +00:00
Johnny Chen
30a910f458 Added the following 16-bit Thumb instructions for disassembly only: YIELD, WFE,
WFI, SEV, SETEND.

llvm-svn: 97149
2010-02-25 17:51:03 +00:00
Johnny Chen
bbe3592817 Added tNOP for disassembly only.
llvm-svn: 97105
2010-02-25 03:28:51 +00:00
Johnny Chen
13b9bd479f Added tSVC and tTRAP for disassembly only.
llvm-svn: 97098
2010-02-25 02:21:11 +00:00
Jakob Stoklund Olesen
2b93d17560 Create a stack frame on ARM when
- Function uses all scratch registers AND
- Function does not use any callee saved registers AND
- Stack size is too big to address with immediate offsets.

In this case a register must be scavenged to calculate the address of a stack
object, and the scavenger needs a spare register or emergency spill slot.

llvm-svn: 97071
2010-02-24 22:43:17 +00:00
Bob Wilson
4ffb88d388 Check for comparisons of +/- zero when optimizing less-than-or-equal and
greater-than-or-equal SELECT_CCs to NEON vmin/vmax instructions.  This is
only allowed when UnsafeFPMath is set or when at least one of the operands
is known to be nonzero.

llvm-svn: 97065
2010-02-24 22:15:53 +00:00
Johnny Chen
41ab970549 Added Vector Swap (VSWPd and VSWPq) instructions for disassembly only.
A8.6.405

llvm-svn: 97052
2010-02-24 20:06:07 +00:00
Jakob Stoklund Olesen
249caada0e Stay away from str <undef> in ARMLoadStoreOpt. This pass does not understand
<undef> operands, and can cause scavenger failures when it translates
<kill,undef> to <kill>.

llvm-svn: 97046
2010-02-24 18:57:08 +00:00
Johnny Chen
71bf8b1466 Fixed typo of opcodestr, should be "vst1", not "vld1".
llvm-svn: 97044
2010-02-24 18:00:40 +00:00
Chandler Carruth
541c3f0bcc Remove an unused variable. Was this intentional?
llvm-svn: 97022
2010-02-24 06:09:03 +00:00
Johnny Chen
c31a44dd8b Added for disassembly VST1 (multiple single elements) which stores elements to
memory from three or four registers and VST2 (multiple two-element structures)
which stores to memory from two double-spaced registers.

A8.6.391 & A8.6.393

llvm-svn: 97018
2010-02-24 02:57:20 +00:00
Jim Grosbach
3eacf455a0 handle very large call frames when require SPAdj != 0 for Thumb1
llvm-svn: 97013
2010-02-24 02:15:43 +00:00
Jim Grosbach
6f72657d6e LowerCall() should always do getCopyFromReg() to reference the stack pointer.
Machine instruction selection is much happier when operands are in virtual
registers.

llvm-svn: 97012
2010-02-24 01:43:03 +00:00
Johnny Chen
7e4227c8e1 Added for disassembly VLD1 (multiple single elements) which loads memory into
three or four registers and VLD2 (multiple two-element structures) which loads
memory into two double-spaced registers.

A8.6.307 & A8.6.310

llvm-svn: 96980
2010-02-23 20:51:23 +00:00
Jim Grosbach
0525cd8596 Spelling. s/suppor /support /
llvm-svn: 96954
2010-02-23 17:16:27 +00:00
Johnny Chen
9077a6f901 Added versions of VCGE, VCGT, VCLE, and VCLT NEON instructions which compare to
(immediate #0) for disassembly only.

A8.6.283, A8.6.285, A8.6.287, A8.6.290

llvm-svn: 96856
2010-02-23 01:42:58 +00:00
Johnny Chen
b35408e8df Added VCEQ (immediate #0) NEON instruction for disassembly only.
A8.6.281

llvm-svn: 96838
2010-02-23 00:33:12 +00:00
Jim Grosbach
c4ab116a90 Updated version of r96634 (which was reverted due to failing 176.gcc and
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.

llvm-svn: 96822
2010-02-22 23:10:38 +00:00
Jim Grosbach
4aea6e93c8 Clean up a bit and fix for when SPAdj != 0
llvm-svn: 96818
2010-02-22 22:54:55 +00:00
Jim Grosbach
8ae3bf1f1e The predicate index isn't fixed, so scan for it to make sure we get the proper
value.

Thumb2 uses the tADJCALLSTACK* instructions, and doesn't need t2 versions, so
remove the FIXME entry.

llvm-svn: 96817
2010-02-22 22:47:46 +00:00
Johnny Chen
0e6c232f0e Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD,
for disassembly only.

llvm-svn: 96806
2010-02-22 21:50:40 +00:00
Johnny Chen
bdb1fdccfb Added a bunch of instructions for disassembly only:
o signed/unsigned add/subtract
o signed/unsigned halving add/subtract
o unsigned sum of absolute difference [and accumulate]
o signed/unsigned saturate
o signed multiply accumulate/subtract [long] dual

llvm-svn: 96795
2010-02-22 18:50:54 +00:00
Johnny Chen
abea29dc85 Undo r96654. The printing of ARM shift instructions in canonical forms can be
handled in ARMInstPrinter.cpp.

And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only.

llvm-svn: 96719
2010-02-21 04:42:01 +00:00
Bob Wilson
df432a30b2 Revert 96634. It causes assertion failures for 126.gcc and 176.gcc in
the armv6 nightly tests.

llvm-svn: 96691
2010-02-19 18:59:53 +00:00
Johnny Chen
2a3db5ee3d Added entries for ASR, LSL, LSR, ROR, and RRX so that the disassembler prints
out the canonical form (A8.6.98) instead of the pseudo-instruction as provided
via MOVs.

DBG_ARM_DISASM=YES llvm-mc -triple=arm-unknown-unknown --disassemble
0xc0 0x00 0xa0 0xe1
Opcode=29 Name=ASR Format=ARM_FORMAT_LDMISCFRM
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	asr	r0, r0, #1

llvm-svn: 96654
2010-02-19 02:12:06 +00:00
Jim Grosbach
53ef05fa82 Radar 7636153. In the presence of large call frames, it's not sufficient
for ARM to just check if a function has a FP to determine if it's safe
to simplify the stack adjustment pseudo ops prior to eliminating frame
indices. Allow targets to override the default behavior and does so for ARM
and Thumb2.

llvm-svn: 96634
2010-02-19 00:16:24 +00:00
Johnny Chen
8d67f1d58d Added LDRD_PRE/POST & STRD_PRE/POST for disassembly only.
llvm-svn: 96619
2010-02-18 22:31:18 +00:00
Bob Wilson
84fc0200bd Use NEON vmin/vmax instructions for floating-point selects.
Radar 7461718.

llvm-svn: 96572
2010-02-18 06:05:53 +00:00
Johnny Chen
2ef74d0ad2 Added LDRSBT, LDRHT, LDRSHT for disassembly only. And fixed encoding errors
of AI3ldsbpo, AI3ldhpo, and AI3ldshpo in ARMInstrFormats.td in the process.

llvm-svn: 96565
2010-02-18 03:27:42 +00:00
Johnny Chen
7f0bf276c2 Added for disassembly only the variants of DMB, DSB, and ISB.
llvm-svn: 96540
2010-02-18 00:19:08 +00:00
Bob Wilson
400e59ba21 Remove the NEON N2VSInt instruction class: it's only used in one place and
since it has no pattern, there's not much point in distinguishing an "N2VS"
class for intrinsics anyway.

llvm-svn: 96525
2010-02-17 22:42:54 +00:00
Johnny Chen
69bbc8c81b Added CLREX (Clear-Exclusive) for disassembly only.
A8.6.30

llvm-svn: 96523
2010-02-17 22:37:58 +00:00
Bob Wilson
ea55421ec2 More cleanup for NEON:
* Use "S" abbreviation for scalar single FP registers in class and pattern
names, instead of keeping the "D" (for "double") abbreviation and tacking on
an "s" elsewhere in the name.
* Move the scalar single FP register classes and patterns to be more
consistent with other definitions in the file.
* Rename "VNEGf32d" definition to "VNEGfd" for consistency.
* Deleted the N2VDIntsPat pattern; N2VSPat is good enough.

llvm-svn: 96521
2010-02-17 22:23:11 +00:00