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Commit Graph

219013 Commits

Author SHA1 Message Date
Gulfem Savrun Yeniceri
4e540995b1 [profile] Add binary id into profiles
This patch adds binary id into profiles to easily associate binaries
with the corresponding profiles. There is an RFC that discusses
the motivation, design and implementation in more detail:
https://lists.llvm.org/pipermail/llvm-dev/2021-June/151154.html

Differential Revision: https://reviews.llvm.org/D102039
2021-07-23 00:19:12 +00:00
Hongtao Yu
03b82baf95 [CSSPGO] Fix a typo in SampleContextTracker
Fixing a typo in SampleContextTracker to use debug name when debug linkage name is no present. This should only affect C programs.

Saw 0.6% perf win on Cinder which is mostly C code.

Reviewed By: wenlei, wmi

Differential Revision: https://reviews.llvm.org/D106599
2021-07-22 16:44:50 -07:00
Nico Weber
5e2439abcf [gn build] (manually) port f8c6515554cc (libLLVMDWP) 2021-07-22 19:38:50 -04:00
Mara Sophie Grosch
f0b7862d3f Add llvm-readobj and binutils symlinks to LLVM_TOOLCHAIN_TOOLS
This patch adds llvm-readobj and the binutils symlink for readelf to
LLVM_TOOLCHAIN_TOOLS.

Tvoid *thread, void *attr,hey are required by some (most?)
autoconf-built libraries, adding these allows me to build newlib with
the toolchain generated this way.

Also opened an issue for that some days ago, see
https://bugs.llvm.org/show_bug.cgi?id=50698

Reviewed By: sbc100

Differential Revision: https://reviews.llvm.org/D104957
2021-07-22 16:33:51 -07:00
Mircea Trofin
081fb59169 [MLGO] Strip TF_PIP cmake variable
This should fix build breaks for 'development' mode. The other modes
were unaffected - 'release' because it doesn't use TFUtils.cpp, and the
mixed mode because the AOT compiled code brings in the necessary include
dirs anyway.
2021-07-22 16:28:13 -07:00
Florian Mayer
b276efa2ab [hwasan] Use stack safety analysis.
This avoids unnecessary instrumentation.

Reviewed By: eugenis, vitalybuka

Differential Revision: https://reviews.llvm.org/D105703
2021-07-22 16:20:27 -07:00
Mircea Trofin
cbaf468075 [docs] Add the compiler-rt requirement to the test suite doc
Differential Revision: https://reviews.llvm.org/D101467
2021-07-22 16:03:45 -07:00
Eli Friedman
299e6ad121 [AArch64] Regenerate test arm64-ccmp.ll 2021-07-22 15:03:05 -07:00
Roman Lebedev
78acee8f2c [SimplifyCFG] SimplifyCondBranchToTwoReturns(): really only deal with different ret blocks
This function is called when some predecessor of an empty return block
ends with a conditional branch, with both successors being empty ret blocks.

Now, because of the way SimplifyCFG works, it might happen to simplify
one of the blocks in a way that makes a conditional branch
into an unconditional one, since it's destinations are now identical,
but it might not have actually simplified said conditional branch
into an unconditional one yet.

So, we have to check that ourselves first,
especially now that SimplifyCFG aggressively tail-merges
all ret and resume blocks.

Even if it was an unconditional branch already,
`SimplifyCFGOpt::simplifyReturn()` doesn't call `FoldReturnIntoUncondBranch()`
by default.
2021-07-23 00:36:59 +03:00
Roman Lebedev
81ab17a5de [NFC][LoopDeletion] Autogenerate checlines in simplify-then-delete.ll test 2021-07-23 00:36:59 +03:00
Roman Lebedev
7bfed10a78 [NFC][SimplifyCFG] Add test for SimplifyCondBranchToTwoReturns() mishandling 2021-07-23 00:36:59 +03:00
Alexander Yermolovich
a827bbdfea [DWP] Refactoring llvm-dwp in to a library part 2
This is follow up to https://reviews.llvm.org/D106198 where llvm-dwp was refactored in to multiple files.
In this patch moving them in to lib/include directories.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D106493
2021-07-22 14:23:29 -07:00
Nick Fitzgerald
f7deab5277 Reland: "[WebAssembly] Deduplicate imports of the same module name, field name, and type"
When two symbols import the same thing, only one import should be
emitted in the Wasm file.

Fixes https://bugs.llvm.org/show_bug.cgi?id=50938

Reverted in: 16aac493e59519377071e900d119ba2e7e5b525d.

Reviewed By: sbc100

Differential Revision: https://reviews.llvm.org/D105519
2021-07-22 14:16:05 -07:00
Mircea Trofin
a7e679b2fb [MLGO] Correct protobuf path 2021-07-22 13:24:55 -07:00
Paulo Matos
e8be0ee828 [WebAssembly] Implementation of global.get/set for reftypes in LLVM IR
Reland of 31859f896.

This change implements new DAG notes GLOBAL_GET/GLOBAL_SET, and
lowering methods for load and stores of reference types from IR
globals. Once the lowering creates the new nodes, tablegen pattern
matches those and converts them to Wasm global.get/set.

Reviewed By: tlively

Differential Revision: https://reviews.llvm.org/D104797
2021-07-22 22:07:24 +02:00
Mircea Trofin
294f763d01 [NFC][MLGO] Fix vector sizing
The bots only build release mode, and the use of `reserve` instead of
`resize`, while not causing invalid memory accesses, is incorrect.
2021-07-22 13:06:00 -07:00
Roman Lebedev
fb2a58c6ab [NFCI][TLI] prepare[US]REMEqFold(): don't add nonsensical 'exact' flag to rotates created
As pointed out by Craig Topper.
2021-07-22 23:02:58 +03:00
Eric Astor
fa28271fe9 [ms] [llvm-ml] Fix macro case-insensitivity
We previously had issues identifying macros not registered with a lowercase name.

Reviewed By: mstorsjo, thakis

Differential Revision: https://reviews.llvm.org/D106453
2021-07-22 15:50:52 -04:00
Nikita Popov
001cdeb281 [LICM][SCCP] Regenerate test checks (NFC) 2021-07-22 21:37:21 +02:00
Roman Lebedev
42833bc33b [SimplifyCFG] FoldTwoEntryPHINode(): bailout on inverted logical and/or (PR51149)
The logical (select) form of and/or will now be a source of problems.
We don't really account for it's inverted form, yet it exists,
and presumably we should treat it just like non-inverted form:
https://alive2.llvm.org/ce/z/BU9AXk

https://bugs.llvm.org/show_bug.cgi?id=51149 reports a reportedly-serious
perf regression that will hopefully be mitigated by this.
2021-07-22 22:19:34 +03:00
Roman Lebedev
c256072b86 [NFC][SimplifyCFG] Add some more tests w/ two-entry PHI nodes and 2021-07-22 22:19:34 +03:00
Jon Chesterfield
0493801fb2 [nfc] Fix typo in comment, s/node/note 2021-07-22 20:16:53 +01:00
Simon Pilgrim
c4477aac03 [CostModel][X86] Adjust shift SSE4 legalized costs based on llvm-mca reports.
Update shl/lshr/ashr costs based on the worst case costs from the script in D103695 - many of the 128-bit shifts (usually where integer multiplies aren't used) have similar behaviour to AVX1 so we can merge them.
2021-07-22 20:07:32 +01:00
Simon Pilgrim
b82c6c9bf3 [CostModel][X86] Fix funnel shift check prefixes
We'd lost AVX1 test coverage due to bulldozer (XOP) trying to use the same check prefixes - we really need to fix the update script to avoid this!
2021-07-22 20:07:31 +01:00
LLVM GN Syncbot
6f2b14a5c2 [gn build] Port 3959c95deb11 2021-07-22 18:41:45 +00:00
Simon Pilgrim
815b215830 [X86] Fix SLM FP<->INT throughputs.
Noticed while trying to clean up the shift costs model for SSE4 targets using the script in D10369 - SLM double-pumps all the 128-bit vector conversion ops and only use FP0 pipe - numbers taken from Intel AOM + Agner.
2021-07-22 19:39:04 +01:00
Thomas Johnson
60773756e3 [ARC] Add disassembly for the conditioned RSUB immediate instruction
Differential Revision: https://reviews.llvm.org/D106497
2021-07-22 11:34:39 -07:00
Fangrui Song
fe2cf61945 [Matrix] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off build after D106457. NFC 2021-07-22 11:33:02 -07:00
Adam Nemet
cf091349e0 [Matrix] Fix miscompile for NT matmul if the transpose has other use
We should only add the fake lowering entry for the matrix remark if the
transpose is not lowered on its own.  `MapVector::insert` is used to insert
the entry during proper lowering which does not overwrite the fake entry in
the map.

We actually had test coverage for this but the reference output code was
wrong; it was storing undef rather than the transposed column.

Also add an assert that would have caught this.

Differential Revision: https://reviews.llvm.org/D106457
2021-07-22 10:45:56 -07:00
Krishna Kariya
54bb3c6144 [InstCombine][test] add coverage for possible fabs folds; NFC
This goes with D101727 (adds FMF to the select).

Differential Revision: https://reviews.llvm.org/D106563
2021-07-22 13:22:56 -04:00
David Green
f13ef26613 [AArch64] Adjust the cost of integer sum reductions
This changes the cost to (LT.first-1) * cost(add) + 2, where the cost of
an add is assumed to be 1. This brings it inline with the other
reductions.

Differential Revision: https://reviews.llvm.org/D106240
2021-07-22 18:19:54 +01:00
Simon Pilgrim
8371f55768 [CostModel][X86] Adjust shift SSE legalized costs based on llvm-mca reports.
Update shl/lshr/ashr costs based on the worst case costs from the script in D103695.
2021-07-22 18:12:49 +01:00
Shilei Tian
04b998f247 [OpenMPOpt] Add support for BooleanStateWithSetVector
D101977 added `BooleanStateWithPtrSetVector` to store pointers to a set meanwhile
tracking boolean state. One of the limitation is that it can only store pointer.
We might want it to store other types of values, such as integer for parallel
level. This patch generalizes the idea and create `BooleanStateWithSetVector`.
`BooleanStateWithPtrSetVector` therefore becomes a type alias of `BooleanStateWithSetVector`.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106149
2021-07-22 13:12:29 -04:00
Fangrui Song
86e8114938 [test] Add llvm-stress to LLVM_TEST_DEPENDS and lit substitutions
D106430 added a test which needs LLVM_TEST_DEPENDS and lit substitution.
2021-07-22 09:37:01 -07:00
Victor Huang
017f21fed1 [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility
This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch adds the builtin and intrinsic for "__stbcx".

Reviewed By: nemanjai, #powerpc

Differential revision: https://reviews.llvm.org/D106484
2021-07-22 10:48:46 -05:00
Alexey Bataev
fd1d10a20f [OPENMP]Fix PR49787: Codegen for calling __tgt_target_teams_nowait_mapper has too few arguments.
Added missed arguments in
__tgt_target_teams_nowait_mapper/__tgt_target_nowait_mapper runtime
functions calls.

Differential Revision: https://reviews.llvm.org/D106542
2021-07-22 08:44:37 -07:00
Alexey Bataev
6351ecd4dc Revert "[OPENMP]Fix PR49787: Codegen for calling __tgt_target_teams_nowait_mapper has too few arguments."
This reverts commit b455f7f22564a096c043b02fa159ab16669c121c to fix
buildbots.
2021-07-22 08:06:29 -07:00
Alexey Bataev
0261373c6d [OPENMP]Fix PR49787: Codegen for calling __tgt_target_teams_nowait_mapper has too few arguments.
Added missed arguments in
__tgt_target_teams_nowait_mapper/__tgt_target_nowait_mapper runtime
functions calls.

Differential Revision: https://reviews.llvm.org/D106542
2021-07-22 07:53:37 -07:00
Cullen Rhodes
5202ca9718 [AArch64][SME] Improve diagnostic for vector select register
Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D106540
2021-07-22 13:46:40 +00:00
Kazu Hirata
19374d4da0 [Transforms] Remove getOrCreateInitFunction (NFC)
The last use was removed on Jan 16, 2019 in commit
81101de5853b4ed64640220a086a67b16f36f153.
2021-07-22 06:30:39 -07:00
Nico Weber
54dea701e7 [gn build] (manually) port 78bda894129 from 2012 because 924d62ca4a85 added it to check-llvm 2021-07-22 09:11:54 -04:00
Caroline Concatto
2a337676d3 [LoopVectorize] Fix crash for predicated instruction with scalable VF
This patch avoids computing discounts for predicated instructions  when the
VF is scalable.
There is no support for vectorization of loops with division because the
vectorizer cannot guarantee that zero divisions will not happen.

This loop now does not use VF scalable

```
for (long long i = 0; i < n; i++)
    if (cond[i])
      a[i] /= b[i];
```

Differential Revision: https://reviews.llvm.org/D101916
2021-07-22 12:48:27 +01:00
Paulo Matos
ceddd7eb41 Add support for zero-sized Scalars as a LowLevelType
Opaque values (of zero size) can be stored in memory with the
implemention of reference types in the WebAssembly backend. Since
MachineMemOperand uses LLTs we need to be able to support
zero-sized scalars types in LLTs.

Differential Revision: https://reviews.llvm.org/D105423
2021-07-22 13:47:19 +02:00
Florian Mayer
152a339cb1 Revert "[hwasan] Use stack safety analysis."
This reverts commit bde9415fef25e9ff6e10595a2f4f5004dd62f10a.
2021-07-22 12:16:16 +01:00
Dawid Jurczak
60d27bc367 [LoopIdiom] Transform memmove-like loop into memmove (PR46179)
The purpose of patch is to learn Loop idiom recognition pass how to recognize simple memmove patterns
in similar way like GCC: https://godbolt.org/z/fh95e83od
LoopIdiomRecognize already has machinery for memset and memcpy recognition, patch tries to extend exisiting capabilities with minimal effort.

Differential Revision: https://reviews.llvm.org/D104464
2021-07-22 13:05:43 +02:00
Florian Mayer
fa5973a54d [hwasan] Use stack safety analysis.
This avoids unnecessary instrumentation.

Reviewed By: eugenis, vitalybuka

Differential Revision: https://reviews.llvm.org/D105703
2021-07-22 12:04:54 +01:00
Simon Pilgrim
8531d202cf [InstCombine] Fold (gep (oneuse(gep Ptr, Idx0)), Idx1) -> (gep Ptr, (add Idx0, Idx1)) (PR51069)
As noticed on D106352, after we've folded "(select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0))" if the inner Ptr was also a (now one use) gep we could then merge the geps, using the sum of the indices instead.

I've limited this to basic 2-op geps - a more general case further down InstCombinerImpl.visitGetElementPtrInst doesn't have the one-use limitation but only creates the add if it can be created via SimplifyAddInst.

https://alive2.llvm.org/ce/z/f8pLfD (Thanks Roman!)

Differential Revision: https://reviews.llvm.org/D106450
2021-07-22 10:58:51 +01:00
Simon Tatham
bc23ee33a0 [clang] Use i64 for the !srcloc metadata on asm IR nodes.
This is part of a patch series working towards the ability to make
SourceLocation into a 64-bit type to handle larger translation units.

!srcloc is generated in clang codegen, and pulled back out by llvm
functions like AsmPrinter::emitInlineAsm that need to report errors in
the inline asm. From there it goes to LLVMContext::emitError, is
stored in DiagnosticInfoInlineAsm, and ends up back in clang, at
BackendConsumer::InlineAsmDiagHandler(), which reconstitutes a true
clang::SourceLocation from the integer cookie.

Throughout this code path, it's now 64-bit rather than 32, which means
that if SourceLocation is expanded to a 64-bit type, this error report
won't lose half of the data.

The compiler will tolerate both of i32 and i64 !srcloc metadata in
input IR without faulting. Test added in llvm/MC. (The semantic
accuracy of the metadata is another matter, but I don't know of any
situation where that matters: if you're reading an IR file written by
a previous run of clang, you don't have the SourceManager that can
relate those source locations back to the original source files.)

Original version of the patch by Mikhail Maltsev.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D105491
2021-07-22 10:24:52 +01:00
David Green
3712bffb3b [AArch64] Add and update reduction and shuffle costs. NFC 2021-07-22 10:22:42 +01:00
Fraser Cormack
4c884f4ac3 [RISCV] Fix a crash when lowering split float arguments
Lowering certain float vectors without legal vector types could cause a
crash due to a bad interaction between passing floats via GPRs and
argument splitting. Split vector floats appear just like scalar floats.
Under certain situations we choose to pass these float arguments via
GPRs and use an XLenVT location and set the 'BCvt' info to track how
they must be converted back to floating-point values. However, later
logic for handling split arguments may take over, in which case we lose
the previous information and set the 'Indirect' info, thus incorrectly
lowering to integer types.

I don't believe that we would have come across the notion of split
floating-point arguments before. This patch addresses the issue by
updating the lowering so that split arguments are only passed indirectly
when they are scalar integer types.

This has some change to how we lower some larger illegal float vectors,
as can be seen in 'fastcc-float.ll' where the vector is now passed
partly in registers and partly on the stack.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D102852
2021-07-22 09:55:26 +01:00