1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-01 16:33:37 +01:00
Commit Graph

79103 Commits

Author SHA1 Message Date
Benjamin Kramer
503550b85a Simplify code. No functionality change.
Using DenseMap iterators isn't free as they have to check for empty
buckets. Dominator queries are common so this gives a minor speedup.

llvm-svn: 147544
2012-01-04 20:20:08 +00:00
Sebastian Pop
4f82b3a13f use getHostTriple instead of getDefaultTargetTriple in getClosestTargetForJIT
Get back getHostTriple.

For JIT compilation, use the host triple instead of the default
target: this fixes some JIT testcases that used to fail when the
compiler has been configured as a cross compiler.

llvm-svn: 147542
2012-01-04 19:47:22 +00:00
Akira Hatanaka
226cdda2c3 Enable -soft-float for MIPS.
llvm-svn: 147541
2012-01-04 19:29:11 +00:00
Nick Lewycky
44fbcb95ba Remove pointless asserts.
llvm-svn: 147529
2012-01-04 09:42:30 +00:00
Nick Lewycky
d6260dc3cb Teach instcombine all sorts of great stuff about shifts that have exact, nuw or
nsw bits on them.

llvm-svn: 147528
2012-01-04 09:28:29 +00:00
Craig Topper
98a7d766e3 Allow vector shuffle normalizing to use concat vector even if the sources are commuted in the shuffle mask.
llvm-svn: 147527
2012-01-04 09:23:09 +00:00
Craig Topper
16ee6a6196 Implement VECTOR_SHUFFLE canonicalizations during DAG combine.
llvm-svn: 147525
2012-01-04 08:07:43 +00:00
NAKAMURA Takumi
6ebbc05c9d test/CodeGen/X86/jump_sign.ll: Add -mcpu=pentiumpro for non-x86 hosts. It uses "cmov".
llvm-svn: 147521
2012-01-04 03:52:23 +00:00
Akira Hatanaka
4585b90e3b Rename immLUiOpnd.
llvm-svn: 147519
2012-01-04 03:09:26 +00:00
Akira Hatanaka
1c63f32318 - Define base classes for Jump-and-link instructions and make 32-bit and 64-bit
versions derive from them.
- JALR64 is not needed since N64 does not emit jal. 
- Add template parameter to BranchLink that sets the rt field. 
- Fix the set of temporary registers for O32 and N64.

llvm-svn: 147518
2012-01-04 03:02:47 +00:00
Akira Hatanaka
fdcba196ca Have getRegForInlineAsmConstraint return the correct register class when target
is Mips64.

llvm-svn: 147516
2012-01-04 02:45:01 +00:00
Evan Cheng
4e60b65bc6 Fix more places which should be checking for iOS, not darwin.
llvm-svn: 147513
2012-01-04 01:55:04 +00:00
Evan Cheng
caba5d2fc2 For x86, canonicalize max
(x > y) ? x : y
=>
(x >= y) ? x : y

So for something like
(x - y) > 0 : (x - y) ? 0
It will be
(x - y) >= 0 : (x - y) ? 0

This makes is possible to test sign-bit and eliminate a comparison against
zero. e.g.
subl   %esi, %edi
testl  %edi, %edi
movl   $0, %eax
cmovgl %edi, %eax
=>
xorl   %eax, %eax
subl   %esi, $edi
cmovsl %eax, %edi

rdar://10633221

llvm-svn: 147512
2012-01-04 01:41:39 +00:00
Kostya Serebryany
c69557e758 [asan] one more test for asan instrumentation: (*a)++ should be instrumented only once.
llvm-svn: 147509
2012-01-04 01:02:14 +00:00
Chris Lattner
a655d4ba69 Turn a few more inline asm errors into "emitErrors" instead of fatal errors.
Before we'd get:

$ clang t.c 
fatal error: error in backend: Invalid operand for inline asm constraint 'i'!

Now we get:

$ clang t.c
t.c:16:5: error: invalid operand for inline asm constraint 'i'!
    "movq         (%4), %%mm0\n"
    ^

Which at least gets us the inline asm that is the problem.

llvm-svn: 147502
2012-01-03 23:51:01 +00:00
Chris Lattner
4f5ba31205 generalize LLVMContext::emitError to take a twine instead of a StringRef.
llvm-svn: 147501
2012-01-03 23:47:05 +00:00
Chad Rosier
74a3944974 Fix 80-column violations.
llvm-svn: 147495
2012-01-03 23:19:12 +00:00
Jakob Stoklund Olesen
5a959fda3b Don't use enums larger than 1 << 31 for target features.
Patch by Andy Zhang!

llvm-svn: 147491
2012-01-03 23:04:28 +00:00
Jakob Stoklund Olesen
993997b659 Revert r146997, "Heed spill slot alignment on ARM."
This patch caused a miscompilation of oggenc because a frame pointer was
suddenly needed halfway through register allocation.

<rdar://problem/10625436>

llvm-svn: 147487
2012-01-03 22:34:35 +00:00
Jakob Stoklund Olesen
2c2f5b0b2b Assert when reserved registers have been assigned.
This can only happen if the set of reserved registers changes during
register allocation.

<rdar://problem/10625436>

llvm-svn: 147486
2012-01-03 22:34:31 +00:00
Nadav Rotem
79f1692fe0 Revert 147426 because it caused pr11696.
llvm-svn: 147485
2012-01-03 22:19:42 +00:00
Nadav Rotem
cc49c4d74d Fix incorrect widening of the bitcast sdnode in case the incoming operand is integer-promoted.
llvm-svn: 147484
2012-01-03 22:12:28 +00:00
Chad Rosier
afcaa8f38a Enhance DAGCombine for transforming 128->256 casts into a vmovaps, rather
then a vxorps + vinsertf128 pair if the original vector came from a load.
rdar://10594409

llvm-svn: 147481
2012-01-03 21:05:52 +00:00
Nick Lewycky
ba84a9652a Conform to the style guide; remove 'else' after 'return'. Also remove an extra
if-statement by turning it into an assert. No functionality change.

llvm-svn: 147474
2012-01-03 20:33:00 +00:00
Owen Anderson
8326b459f7 Remove the restriction that target intrinsics can only involve legal types. Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations.
llvm-svn: 147472
2012-01-03 20:09:02 +00:00
Lang Hames
57893457a4 Clarified assert text.
llvm-svn: 147471
2012-01-03 20:05:57 +00:00
Stepan Dyatkovskiy
7d03628e1e Fix for PR11652: assertion failures when Type.cpp is compiled with -Os
llvm-svn: 147470
2012-01-03 20:04:35 +00:00
Matt Beaumont-Gay
4896c33378 Fix malformed assert.
If anybody has strong feelings about 'default: assert(0 && "blah")' vs
'default: llvm_unreachable("blah")', feel free to regularize the instances of
each in this file.

llvm-svn: 147459
2012-01-03 19:03:59 +00:00
Eric Christopher
173e9e8cf2 Fix typo.
llvm-svn: 147456
2012-01-03 18:38:37 +00:00
Nick Lewycky
d791228af6 Fix typo in ruler. No functionality change.
llvm-svn: 147454
2012-01-03 18:22:43 +00:00
Devang Patel
131611237d Intel style asm variant does not need '%' prefix.
llvm-svn: 147453
2012-01-03 18:22:10 +00:00
Stepan Dyatkovskiy
7d6561f886 Type: replaced usage of ID with getTypeID().
llvm-svn: 147446
2012-01-03 14:05:04 +00:00
Elena Demikhovsky
40f2c3077f Fixed a bug in SelectionDAG.cpp.
The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.

The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.

I added a special test that checks vector shuffle on win32.

llvm-svn: 147445
2012-01-03 11:59:04 +00:00
Andrew Trick
6839d66ab3 Fix SCEVExpander to handle loops with no preheader when LSR gives it a
"phony" insertion point.

Fixes rdar://10619599: "SelectionDAGBuilder shouldn't visit PHI nodes!" assert

llvm-svn: 147439
2012-01-02 21:25:10 +00:00
Duncan Sands
ec8ede7bf4 Correct spelling.
llvm-svn: 147435
2012-01-02 16:55:01 +00:00
Chandler Carruth
a2027ac404 Undo the hack in r147427 and move this unittest to a better home. This
is testing the bitcode reader's functionality, not VMCore's. Add the
what is a hope sufficient build system mojo to build and run a new
unittest.

Also clean up some of the test's naming. The goal for the file should be
to unittest the Bitcode Reader, and this is just one particular test
among potentially many in the future. Also, reverse my position and
relegate the PR# to a comment, but stash the comment on the same line as
the test name so it doesn't get lost. This makes the code more
self-documenting hopefully w/o losing track of the PR number.

llvm-svn: 147431
2012-01-02 09:19:48 +00:00
Craig Topper
dbc281bcbe Miscellaneous shuffle lowering cleanup. No functional changes. Primarily converting the indexing loops to unsigned to be consistent across functions.
llvm-svn: 147430
2012-01-02 09:17:37 +00:00
Craig Topper
69e0a09d8f Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection.
llvm-svn: 147428
2012-01-02 08:46:48 +00:00
Chandler Carruth
4ccca7b229 Fix unittest makefile after r147425. This should unbreak the makefile
build. This didn't show up in the CMake build because the CMake build
for the unittests is rather poorly factored.

This probably isn't the correct fix. This should be a bitcode reader
unittest not a VMCore unittest. I'll move it and clean various parts of
the unittest up in a follow-up patch, but I wanted to unbreak the bots.

llvm-svn: 147427
2012-01-02 08:40:40 +00:00
Nadav Rotem
6929a8868b Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit.
llvm-svn: 147426
2012-01-02 08:05:46 +00:00
Rafael Espindola
7ab0861d5f Materialize functions whose basic blocks are used by global variables. Fixes
PR11677.

llvm-svn: 147425
2012-01-02 07:49:53 +00:00
Craig Topper
f7c9bf17dd Allow CRC32 instructions to be selected when AVX is enabled.
llvm-svn: 147411
2012-01-01 19:51:58 +00:00
Craig Topper
d8ae2d9f27 Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers.
llvm-svn: 147409
2012-01-01 19:40:22 +00:00
Benjamin Kramer
210900f7c2 X86Disassembler: Fix undefined behavior found by GCC 4.6
llvm-svn: 147404
2012-01-01 17:55:36 +00:00
Benjamin Kramer
fba4e88bc2 PatternMatch: Introduce a matcher for instructions with the "exact" bit. Use it to simplify a few matchers.
llvm-svn: 147403
2012-01-01 17:55:30 +00:00
Benjamin Kramer
450513861d PatternMatch: Simplify code by reusing the Operator class.
llvm-svn: 147402
2012-01-01 17:55:23 +00:00
Rafael Espindola
1cb17796db Revert 147399. It broke CodeGen/ARM/vext.ll.
llvm-svn: 147400
2012-01-01 17:36:23 +00:00
Elena Demikhovsky
9b74049783 Fixed a bug in SelectionDAG.cpp.
The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.

The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.

I added a special test that checks vector shuffle on win32.

llvm-svn: 147399
2012-01-01 16:22:47 +00:00
NAKAMURA Takumi
ad71e57658 Happy new year 2012!
llvm-svn: 147395
2012-01-01 08:16:56 +00:00
Craig Topper
ef59fe1ad4 Merge X86 SHUFPS and SHUFPD node types.
llvm-svn: 147394
2011-12-31 23:50:21 +00:00