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Author SHA1 Message Date
Craig Topper
0311c45aed Add patterns for integer forms of SHUFPD/VSHUFPD with a memory load. 
llvm-svn: 147393
 2011-12-31 23:24:49 +00:00
Craig Topper
c01ce759d7 Fix typo in a SHUFPD and VSHUFPD pattern that prevented SHUFPD/VSHUFPD with a load from being selected. 
llvm-svn: 147392
 2011-12-31 23:15:11 +00:00
Nick Lewycky
c7e12f7dbf Make use of the exact bit when optimizing '(X >>exact 3) << 1' to eliminate the 
'and' that would zero out the trailing bits, and to produce an exact shift
ourselves.

llvm-svn: 147391
 2011-12-31 21:30:22 +00:00
Dylan Noblesmith
06b6c587e8 VMCore: add assert for miscompile 
See PR11652. Trying to add this assert to
setSubclassData() itself actually prevented
the miscompile entirely, so it has to be here.

This makes the source of the bug more obvious
than the other asserts triggering later on did.

llvm-svn: 147390
 2011-12-31 13:58:58 +00:00
Bruno Cardoso Lopes
4ed60a4736 Cleanup Mips code and rename some variables. Patch by Jack Carter 
llvm-svn: 147383
 2011-12-30 21:09:41 +00:00
Bruno Cardoso Lopes
7de2b7652d Improve Mips JIT. 
Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue
for jmptarget and brtarget Mips tablegen operand types in the code emitter
for old-style JIT. Rename the pc relative relocation for branches - new
name is Mips::reloc_mips_pc16.

Patch by Sasa Stankovic

llvm-svn: 147382
 2011-12-30 21:04:30 +00:00
Nick Lewycky
ed7856bd5b Remove extraneous ".get()->" which is just "->". No functionality change. 
llvm-svn: 147379
 2011-12-30 19:17:23 +00:00
Craig Topper
4065311852 Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. 
llvm-svn: 147369
 2011-12-30 07:16:00 +00:00
Craig Topper
b4db8689ee Add disassembler support for VPERMIL2PD and VPERMIL2PS. 
llvm-svn: 147368
 2011-12-30 06:23:39 +00:00
Craig Topper
089be4fefa Add FMA4 instructions to disassembler. 
llvm-svn: 147367
 2011-12-30 05:20:36 +00:00
Craig Topper
44a5136fac Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. 
llvm-svn: 147366
 2011-12-30 04:48:54 +00:00
Craig Topper
97ba7b38eb Combine FMA4 SS/SD patterns with the instruction definitions. 
llvm-svn: 147365
 2011-12-30 03:33:59 +00:00
Craig Topper
bdcc86a43c Combine FMA4 PS/PD patterns with the instruction definitions. 
llvm-svn: 147364
 2011-12-30 03:17:15 +00:00
Craig Topper
33091db89a Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms. 
llvm-svn: 147361
 2011-12-30 02:18:36 +00:00
Craig Topper
e066262284 Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere. 
llvm-svn: 147360
 2011-12-30 01:49:53 +00:00
Hal Finkel
4a09216dfb Cleanup stack/frame register define/kill states. This fixes two bugs: 
1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test).

2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this.

llvm-svn: 147359
 2011-12-30 00:34:00 +00:00
Rafael Espindola
db7319d272 Implement cfi_restore. Patch by Brian Anderson! 
llvm-svn: 147356
 2011-12-29 21:43:03 +00:00
Rafael Espindola
bc8c3d0ca0 Rename Remember and Restore to RememberState and RestoreState for consistency. 
llvm-svn: 147354
 2011-12-29 21:09:08 +00:00
Craig Topper
97e84c23a1 Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions. 
llvm-svn: 147353
 2011-12-29 20:43:40 +00:00
Rafael Espindola
27298c6f33 Implement .cfi_escape. Patch by Brian Anderson! 
llvm-svn: 147352
 2011-12-29 20:24:47 +00:00
Craig Topper
bcfd070378 Expose FMA3 instructions to the disassembler. 
llvm-svn: 147351
 2011-12-29 20:03:14 +00:00
Craig Topper
9d664349d6 Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled. 
llvm-svn: 147349
 2011-12-29 19:46:19 +00:00
Craig Topper
21029d1f81 Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit. 
llvm-svn: 147348
 2011-12-29 19:25:56 +00:00
Craig Topper
93d614dd3a Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339. 
llvm-svn: 147347
 2011-12-29 18:47:31 +00:00
Craig Topper
ba73cefabb Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet. 
llvm-svn: 147345
 2011-12-29 18:08:36 +00:00
Craig Topper
63bb77ebe7 Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms. 
llvm-svn: 147344
 2011-12-29 18:00:08 +00:00
Craig Topper
04b3b369de Remove the separate explicit AES instruction patterns. They are equivalent to the patterns specified by the instructions. Also remove unnecessary bitconverts from the AES patterns. 
llvm-svn: 147342
 2011-12-29 17:41:56 +00:00
Craig Topper
3ff20898e9 Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A. 
llvm-svn: 147339
 2011-12-29 15:51:45 +00:00
Craig Topper
0ff84d82cc Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL for v16i16 and v32i8. 
llvm-svn: 147337
 2011-12-29 03:34:54 +00:00
Craig Topper
cb884f28d9 Remove some elses after returns. 
llvm-svn: 147336
 2011-12-29 03:20:51 +00:00
Craig Topper
4cbe88ceba Remove trailing spaces. Fix an assert to use && instead of || before string. Add same assert on similar code path. 
llvm-svn: 147335
 2011-12-29 03:09:33 +00:00
Rafael Espindola
1935193ab7 Fix grammar error noticed by Duncan. 
llvm-svn: 147333
 2011-12-29 02:15:06 +00:00
Nick Lewycky
7425820374 Change CaptureTracking to pass a Use* instead of a Value* when a value is 
captured. This allows the tracker to look at the specific use, which may be
especially interesting for function calls.

Use this to fix 'nocapture' deduction in FunctionAttrs. The existing one does
not iterate until a fixpoint and does not guarantee that it produces the same
result regardless of iteration order. The new implementation builds up a graph
of how arguments are passed from function to function, and uses a bottom-up walk
on the argument-SCCs to assign nocapture. This gets us nocapture more often, and
does so rather efficiently and independent of iteration order.

llvm-svn: 147327
 2011-12-28 23:24:21 +00:00
Eli Friedman
db54b4b68f Fix type-checking for load transformation which is not legal on floating-point types. PR11674. 
llvm-svn: 147323
 2011-12-28 21:24:44 +00:00
Bob Wilson
152a507523 Update OCaml bindings for the new half float type. 
Patch by Jonathan Ragan-Kelley!

llvm-svn: 147314
 2011-12-28 18:51:08 +00:00
Rafael Espindola
510f9d49fb Add support for mipsel in configure. Fixes PR11669. Patch by Sylvestre Ledru. 
llvm-svn: 147312
 2011-12-28 17:08:00 +00:00
Nadav Rotem
d8c4880903 PR11662. 
Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage.

llvm-svn: 147309
 2011-12-28 13:08:20 +00:00
Elena Demikhovsky
9b4613ff14 Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. 
Matching MOVLP mask for AVX (265-bit vectors) was wrong.
The failure was detected by conformance tests.

llvm-svn: 147308
 2011-12-28 08:14:01 +00:00
Nick Lewycky
17d4e8dae6 Demystify this comment. 
llvm-svn: 147307
 2011-12-28 06:57:32 +00:00
Rafael Espindola
2ecba45e58 PR11642 has been fixed, enable -fvisibility-inlines-hidden everywhere. 
llvm-svn: 147296
 2011-12-27 21:37:11 +00:00
Benjamin Kramer
77f9c9f719 Switch StringMap from an array of structures to a structure of arrays. 
- -25% memory usage of the main table on x86_64 (was wasted in struct padding).
- no significant performance change.

llvm-svn: 147294
 2011-12-27 20:35:07 +00:00
Nick Lewycky
4c5662bae0 Use false not zero, as a bool. 
llvm-svn: 147292
 2011-12-27 18:27:22 +00:00
Nick Lewycky
f4c21901a3 Turn cos(-x) into cos(x). Patch by Alexander Malyshev! 
llvm-svn: 147291
 2011-12-27 18:25:50 +00:00
Benjamin Kramer
c64fcf4a95 Clean up some Release build warnings. 
llvm-svn: 147289
 2011-12-27 11:41:05 +00:00
Craig Topper
9c07745da9 Add handling of x86_avx2_pmovmskb to computeMaskedBitsForTargetNode for consistency. Add comments and an assert for BMI instructions to PerformXorCombine since the enabling of the combine is conditional on it, but the function itself isn't. 
llvm-svn: 147287
 2011-12-27 06:27:23 +00:00
Nick Lewycky
295e397220 Teach simplifycfg to recompute branch weights when merging some branches, and 
to discard weights when appropriate. Still more to do (and a new TODO), but
it's a start!

llvm-svn: 147286
 2011-12-27 04:31:52 +00:00
Nick Lewycky
b3f57c8028 Using Inst->setMetadata(..., NULL) should be safe to remove metadata even when 
there is non of that type to remove. This fixes a crasher in the particular
case where the instruction has metadata but no metadata storage in the context
(this is only possible if the instruction has !dbg but no other metadata info).

llvm-svn: 147285
 2011-12-27 01:17:40 +00:00
Rafael Espindola
d448dfaa25 Fix warning. 
llvm-svn: 147284
 2011-12-26 23:12:42 +00:00
Eli Friedman
064187912e Make sure DAGCombiner doesn't introduce multiple loads from the same memory location. PR10747, part 2. 
llvm-svn: 147283
 2011-12-26 22:49:32 +00:00
Nick Lewycky
56e04db381 Update the branch weight metadata when reversing the order of a branch. 
llvm-svn: 147280
 2011-12-26 20:54:14 +00:00