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Commit Graph

91891 Commits

Author SHA1 Message Date
Rafael Espindola
041d6c79e2 Add empty release notes for 3.4.
The idea is that docs/ReleaseNotes.rst is 3.3 and will be copied to the
branch by the release manager just before creating the release
candidates.

This ReleaseNotes_34.rst will then be moved over ReleaseNotes.rst after
the 3.3 release.

llvm-svn: 181349
2013-05-07 20:26:16 +00:00
Matt Arsenault
cd8cfb37f7 Fix vselect when getSetCCResultType returns a different type from the operands
llvm-svn: 181348
2013-05-07 20:24:18 +00:00
Preston Gurd
ed3b81e028 Corrected Atom latencies for SSE SQRT instructions.
llvm-svn: 181346
2013-05-07 19:57:34 +00:00
Jyotsna Verma
37863260ff Hexagon: Fix Small Data support to handle -G 0 correctly.
llvm-svn: 181344
2013-05-07 19:53:00 +00:00
David Blaikie
22d24b013e Debug Info: Fix for break due to r181271
Apparently we didn't keep an association of Compile Unit metadata nodes
to DIEs so looking up that parental context failed & thus caused no
DW_TAG_imported_modules to be emitted at the CU scope. Fix this by
adding the mapping & sure up the test case to verify this.

llvm-svn: 181339
2013-05-07 17:57:13 +00:00
Hal Finkel
1725b5191f Cleanup PPCInstrInfo::optimizeCompareInstr
Implement suggestions by Bill Schmidt in post-commit review. No functionality
change intended.

llvm-svn: 181338
2013-05-07 17:49:55 +00:00
Andrew Trick
424ae1d00a Add two points to release notes about recent command line library changes.
Patch by Dan Liew!

llvm-svn: 181335
2013-05-07 17:34:35 +00:00
Jyotsna Verma
5307666fe8 Reverting r181331.
Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt.

llvm-svn: 181334
2013-05-07 17:12:35 +00:00
Jyotsna Verma
af0c734e1b Hexagon: Fix Small Data support to handle -G 0 correctly.
llvm-svn: 181331
2013-05-07 16:42:15 +00:00
Richard Sandiford
7607d0628b Mention SystemZ in the release notes
llvm-svn: 181328
2013-05-07 15:52:32 +00:00
Jyotsna Verma
71c6bf55f2 Hexagon: Set accessSize and addrMode on all load/store instructions.
llvm-svn: 181324
2013-05-07 15:06:29 +00:00
Michael Kuperstein
25056babb2 Re-enable AVX detection on x64 platforms.
llvm-svn: 181313
2013-05-07 14:05:33 +00:00
Richard Sandiford
a9580c775a [SystemZ] Fix InitMCCodeGenInfo call
createSystemZMCCodeGenInfo was not passing the optimization level to
InitMCCodeGenInfo(), so -O0 would be ignored.  Fixes DebugInfo/namespace.ll
after the changes in r181271.

llvm-svn: 181312
2013-05-07 12:56:31 +00:00
Rafael Espindola
dd63d2006f Note that EH is now supported in MCJIT.
llvm-svn: 181305
2013-05-07 12:29:17 +00:00
Timur Iskhodzhanov
5640405cee Fix the VS2010 build broken by r181271
llvm-svn: 181296
2013-05-07 07:47:47 +00:00
Tim Northover
f29ea28532 Correct logical shift documentation
llvm-svn: 181290
2013-05-07 06:17:14 +00:00
Arnold Schwaighofer
f95f087afb LoopVectorize: getConsecutiveVector must respect signed arithmetic
We were passing an i32 to ConstantInt::get where an i64 was needed and we must
also pass the sign if we pass negatives numbers. The start index passed to
getConsecutiveVector must also be signed.

Should fix PR15882.

llvm-svn: 181286
2013-05-07 04:37:05 +00:00
David Blaikie
b40dfb39c7 DebugInfo: Support imported modules in lexical blocks
llvm-svn: 181271
2013-05-06 23:33:07 +00:00
Tom Stellard
3a335f24af R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181269
2013-05-06 23:02:19 +00:00
Tom Stellard
57e8e4e921 R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemask
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181268
2013-05-06 23:02:15 +00:00
Tom Stellard
d2ec929c52 R600/SI: Add intrinsic for texture image loading
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181267
2013-05-06 23:02:12 +00:00
Tom Stellard
4ed2501894 R600/SI: Add pattern for uint_to_fp
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181266
2013-05-06 23:02:07 +00:00
Tom Stellard
7d53018f9b R600/SI: Add patterns for integer maxima / minima
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181265
2013-05-06 23:02:04 +00:00
Tom Stellard
2c5ed6e6ce R600/SI: Add pattern for AMDGPU.trunc intrinsic
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181263
2013-05-06 23:02:00 +00:00
Krzysztof Parzyszek
b05e065c7b Print IR from Hexagon MI passes with -print-before/after-all.
llvm-svn: 181255
2013-05-06 21:58:00 +00:00
Andrew Trick
66c37e7321 Implemented public interface for modifying registered (not positional or sink options) command line options at runtime.
Patch by Dan Liew!

llvm-svn: 181254
2013-05-06 21:56:35 +00:00
Andrew Trick
7cf2347306 Support command line option categories.
Patch by Dan Liew!

llvm-svn: 181253
2013-05-06 21:56:23 +00:00
Krzysztof Parzyszek
1f0992737e Cleanup of the HexagonTargetMachine setup.
llvm-svn: 181250
2013-05-06 21:25:45 +00:00
David Majnemer
68574fa9e6 InstCombine: (X ^ signbit) + C -> X + (signbit ^ C)
llvm-svn: 181249
2013-05-06 21:21:31 +00:00
Eric Christopher
3cc2bddd41 Hoist boundary condition out of loop header.
llvm-svn: 181248
2013-05-06 21:19:44 +00:00
Eric Christopher
eb2243ca76 Untabify.
llvm-svn: 181247
2013-05-06 21:19:41 +00:00
Bill Wendling
0c1e625af5 Reduce attributes.
llvm-svn: 181245
2013-05-06 20:57:23 +00:00
Rafael Espindola
d896db3c7d Split Alignment out of the Section Characteristics.
The alignment is just a byte in the middle of Characteristics, not an
independent flag. Making it an independent field in the yaml
representation makes it more yamlio friendly.

llvm-svn: 181243
2013-05-06 20:11:21 +00:00
Jyotsna Verma
0ec07a2dbc Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
llvm-svn: 181235
2013-05-06 18:49:23 +00:00
Jean-Luc Duprat
bf543366fd Test results verified using FileCheck rather than grep | count
llvm-svn: 181234
2013-05-06 18:45:16 +00:00
Krzysztof Parzyszek
afd38d8a5a Make references to HexagonTargetMachine "const".
llvm-svn: 181233
2013-05-06 18:38:37 +00:00
Rafael Espindola
6f9d0b4521 Remove some redundant includes in llvm-mc.cpp.
Patch by Jun Koi!

llvm-svn: 181231
2013-05-06 18:19:24 +00:00
Andrew Trick
5d13ab6ea6 Rotate multi-exit loops even if the latch was simplified.
Test case by Michele Scandale!

Fixes PR10293: Load not hoisted out of loop with multiple exits.

There are few regressions with this patch, now tracked by
rdar:13817079, and a roughly equal number of improvements. The
regressions are almost certainly back luck because LoopRotate has very
little idea of whether rotation is profitable. Doing better requires a
more comprehensive solution.

This checkin is a quick fix that lacks generality (PR10293 has
a counter-example). But it trivially fixes the case in PR10293 without
interfering with other cases, and it does satify the criteria that
LoopRotate is a loop canonicalization pass that should avoid
heuristics and special cases.

I can think of two approaches that would probably be better in
the long run. Ultimately they may both make sense.

(1) LoopRotate should check that the current header would make a good
loop guard, and that the loop does not already has a sufficient
guard. The artifical SimplifiedLoopLatch check would be unnecessary,
and the design would be more general and canonical. Two difficulties:

- We need a strong guarantee that we won't endlessly rotate, so the
  analysis would need to be precise in order to avoid the
  SimplifiedLoopLatch precondition.

- Analysis like this are usually based on SCEV, which we don't want to
  rely on.

(2) Rotate on-demand in late loop passes. This could even be done by
shoving the loop back on the queue after the optimization that needs
it. This could work well when we find LICM opportunities in
multi-branch loops. This requires some work, and it doesn't really
solve the problem of SCEV wanting a loop guard before the analysis.

llvm-svn: 181230
2013-05-06 17:58:18 +00:00
Tom Stellard
740d847e2c R600: Remove dead code from the CodeEmitter v2
v2:
  - Replace switch statement with TSFlags query

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181229
2013-05-06 17:50:57 +00:00
Tom Stellard
fb8e73f3af R600: Emit config values in register / value pairs
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181228
2013-05-06 17:50:51 +00:00
Eric Christopher
c179ac43fa Remove unnecessary instance variable and rework logic accordingly.
llvm-svn: 181227
2013-05-06 17:50:50 +00:00
Eric Christopher
5bf0cdb91a Grammar.
llvm-svn: 181226
2013-05-06 17:50:46 +00:00
Tom Stellard
6c3f6e1b02 R600: Stop emitting the instruction type byte before each instruction
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181225
2013-05-06 17:50:44 +00:00
Eric Christopher
4cbb105dfc Don't emit .dwo sections unless they exist.
llvm-svn: 181224
2013-05-06 17:50:42 +00:00
Tom Stellard
ebe049fd75 R600: Emit ISA for CALL_FS_* instructions
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181223
2013-05-06 17:50:26 +00:00
Ulrich Weigand
2d456969d5 [SystemZ] Update non-pic DWARF encodings
As pointed out by Rafael Espindola, we should match the DWARF encodings
produced by GCC in both pic and non-pic modes.  This was not the case
for the non-pic case.

This patch changes all DWARF encodings to DW_EH_PE_absptr for the
non-pic case, just like GCC does.  The test case is updated to check
for both variants.

llvm-svn: 181222
2013-05-06 17:28:30 +00:00
Adhemerval Zanella
3b2874423e PowerPC: Fix unimplemented relocation on ppc64
This patch handles the R_PPC64_REL64 relocation type for powerpc64
for mcjit.

llvm-svn: 181220
2013-05-06 17:21:23 +00:00
Jean-Luc Duprat
8911ab2fa9 Fix add4.ll test cmdline so that it passes
llvm-svn: 181219
2013-05-06 17:18:47 +00:00
Jean-Luc Duprat
5607a72e21 Provide InstCombines for the following 3 cases:
A * (1 - (uitofp i1 C)) -> select C, 0, A
B * (uitofp i1 C) -> select C, B, 0
select C, 0, A + select C, B, 0 -> select C, B, A

These come up in code that has been hand-optimized from a select to a linear blend, 
on platforms where that may have mattered. We want to undo such changes 
with the following transform:
A*(1 - uitofp i1 C) + B*(uitofp i1 C) -> select C, A, B

llvm-svn: 181216
2013-05-06 16:55:50 +00:00
Tim Northover
eb518c7918 AArch64: use MCJIT by default and enable related tests.
This just enables some testing I'd missed after implementing MCJIT
support.

llvm-svn: 181215
2013-05-06 16:51:08 +00:00