RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 20:43:44 +02:00
Code Issues Projects Releases Wiki Activity
66,626 Commits 4 Branches 5 Tags 704 MiB
5cd42cb6f4
Commit Graph

790 Commits

Author SHA1 Message Date
Andrew Lenharth
a369904fc5 The second patch of X86 support for read cycle counter. 
llvm-svn: 24430
 2005-11-20 21:41:10 +00:00
Chris Lattner
af79013023 Teach the x86 backend about the register constraints of its addressing mode. 
Patch by Evan Cheng

llvm-svn: 24423
 2005-11-19 07:01:30 +00:00
Chris Lattner
72fa26a85b add more patterns, patch by Evan Cheng. 
llvm-svn: 24406
 2005-11-18 01:04:42 +00:00
Chris Lattner
f829636c6b Add patterns for some 16-bit immediate instructions, patch contributed by 
Evan Cheng.

llvm-svn: 24384
 2005-11-17 02:01:55 +00:00
Chris Lattner
fec54e57a0 Add patterns for several simple instructions that take i32 immediates. 
Patch contributed by Evan Cheng!

llvm-svn: 24382
 2005-11-16 22:59:19 +00:00
Nate Begeman
3b6c2df603 Properly split f32 and f64 into separate register classes for scalar sse fp 
fixing a bunch of nasty hackery

llvm-svn: 23735
 2005-10-14 22:06:00 +00:00
Chris Lattner
54139f0b83 give all operands names 
llvm-svn: 23356
 2005-09-14 21:10:24 +00:00
Chris Lattner
d7bd59d77e add a few missing cases 
llvm-svn: 22891
 2005-08-19 00:41:29 +00:00
Chris Lattner
f62a66a21c Give ADJCALLSTACKDOWN/UP the correct operands. 
Give a whole bunch of other stuff variable operands, particularly FP.  The
FP stackifier is playing fast and loose with operands here, so we have to
mark them all as variable.  This will have to be fixed before we can dag->dag
the X86 backend.  The solution is for the pre-stackifier and post-stackifier
instructions to all be disjoint.

llvm-svn: 22890
 2005-08-19 00:38:22 +00:00
Nate Begeman
6cd034da8e Scalar SSE: load +0.0 -> xorps/xorpd 
Scalar SSE: a < b ? c : 0.0 -> cmpss, andps
Scalar SSE: float -> i16 needs to be promoted

llvm-svn: 22637
 2005-08-03 23:26:28 +00:00
Nate Begeman
957e0e7c9e Get closer to fully working scalar FP in SSE regs. This gets singlesource 
working, and Olden/power.

llvm-svn: 22441
 2005-07-15 00:38:55 +00:00
Nate Begeman
e5314eb2c2 First round of support for doing scalar FP using the SSE2 ISA extension and 
XMM registers.  There are many known deficiencies and fixmes, which will be
addressed ASAP.  The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.

The x86 backend will still default to x87 style FP.  To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.

An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
                        Sum += P[i]; return Sum; }

The inner loop looks like the following:
x87:
.LBB_foo_1:     # no_exit
        fldl (%esp)
        faddl (%eax,%ecx,8)
        fstpl (%esp)
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

SSE2:
        addsd (%eax,%ecx,8), %xmm0
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

llvm-svn: 22340
 2005-07-06 18:59:04 +00:00
Nate Begeman
032a94775d Initial set of .td file changes necessary to get scalar fp in xmm registers 
working.  The instruction selector changes will hopefully be coming later
this week once they are debugged.  This is necessary to support the darwin
x86 FP model, and is recommended by intel as the replacement for x87.  As
a bonus, the register allocator knows how to deal with these registers
across basic blocks, unliky the FP stackifier.  This leads to significantly
better codegen in several cases.

llvm-svn: 22300
 2005-06-27 21:20:31 +00:00
Chris Lattner
7327c042b4 Add markers in the asm file for tail calls, add a new ADJSTACKPTRri 
sorta-pseudo-instruction

llvm-svn: 22042
 2005-05-15 03:10:37 +00:00
Chris Lattner
64232a8480 Yes, calltarget is the operand of the day. 
llvm-svn: 22040
 2005-05-15 01:10:30 +00:00
Chris Lattner
37e226fa9b Add some new instructions 
llvm-svn: 22036
 2005-05-14 23:35:21 +00:00
Chris Lattner
83d7e55471 add 'ret imm' instruction 
llvm-svn: 21945
 2005-05-13 17:56:48 +00:00
Chris Lattner
7ba0699b05 Fix the syntax of the i/o instructions, these are obviously unused. 
llvm-svn: 21829
 2005-05-09 20:49:20 +00:00
Chris Lattner
236cef3563 Add some new X86 instrs, patch contributed by Morten Ofstad 
llvm-svn: 21608
 2005-04-28 21:50:05 +00:00
Chris Lattner
ba7cdbebb1 add signed versions of the extra precision multiplies 
llvm-svn: 21106
 2005-04-06 04:19:22 +00:00
Chris Lattner
71434aa2dd add an fabs instr 
llvm-svn: 21006
 2005-04-02 04:31:56 +00:00
Chris Lattner
a024984017 Fix spelling, patch contributed by Gabor Greif! 
llvm-svn: 20343
 2005-02-27 06:18:25 +00:00
Chris Lattner
34757ff939 Add rotate instructions. 
llvm-svn: 19690
 2005-01-19 07:50:03 +00:00
Chris Lattner
9d5ee289d7 Improve coverage of the X86 instruction set by adding 16-bit shift doubles. 
llvm-svn: 19687
 2005-01-19 07:31:24 +00:00
Chris Lattner
c03f360215 Teach the code generator that shrd/shld is commutable if it has an immediate. 
This allows us to generate this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        shld %EDX, %EDX, 2
        shl %EAX, 2
        ret

instead of this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EDX, %EAX
        shrd %EDX, %ECX, 30
        shl %EAX, 2
        ret

Note the magically transmogrifying immediate.

llvm-svn: 19686
 2005-01-19 07:11:01 +00:00
Chris Lattner
65d007ab62 Add conditional moves for the parity flag. 
llvm-svn: 19437
 2005-01-10 22:09:33 +00:00
Chris Lattner
1aaf8cccb2 ADC and IMUL are also commutable. 
llvm-svn: 19264
 2005-01-03 01:27:59 +00:00
Chris Lattner
0d6f03e52b Two changes here: 
1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP.
2. Set the isCommutable and isPromotableTo3Address bits on several
   instructions.

llvm-svn: 19246
 2005-01-02 02:35:46 +00:00
John Criswell
402e338f11 Correct the name of stosd for the AT&T syntax: 
It's stosl (l for long == 32 bit).

llvm-svn: 17658
 2004-11-10 04:48:15 +00:00
Chris Lattner
82aa8544a5 Remove debugging code, fix encoding problem. This fixes the problems 
the JIT had last night.

llvm-svn: 16766
 2004-10-06 14:31:50 +00:00
Chris Lattner
acd213fba3 Add some new instructions. Fix the asm string for sbb32rr 
llvm-svn: 16759
 2004-10-06 04:01:02 +00:00
Chris Lattner
5959f4a108 Convert some missed patterns to support AT&T style 
llvm-svn: 16645
 2004-10-04 07:23:07 +00:00
Chris Lattner
a05d9f53bb Apparently the GNU assembler has a HUGE hack to be compatible with really 
old and broken AT&T syntax assemblers.  The problem with this hack is that
*SOME* forms of the fdiv and fsub instructions have the 'r' bit inverted.
This was a real pain to figure out, but is trivially easy to support: thus
we are now bug compatible with gas and gcc.

llvm-svn: 16644
 2004-10-04 07:08:46 +00:00
Chris Lattner
08098895db Fix incorrect suffix 
llvm-svn: 16642
 2004-10-04 05:20:16 +00:00
Chris Lattner
c2fc9597bd Fix some more missed suffixes and swapped operands 
llvm-svn: 16641
 2004-10-04 01:38:10 +00:00
Chris Lattner
7b15a84728 Add missing suffixes to FP instructions for AT&T mode 
llvm-svn: 16640
 2004-10-04 00:43:31 +00:00
Chris Lattner
94780713a8 Add support to the instruction patterns for AT&T style output, which will 
hopefully lead to the death of the 'GasBugWorkaroundEmitter'.  This also
includes changes to wrap the whole file to 80 columns! Woot! :)

Note that the AT&T style output has not been tested at all.

llvm-svn: 16638
 2004-10-03 20:35:00 +00:00
Alkis Evlogimenos
4d2b0a2b5b Use a shorter form to express implicit use/defs in FpGETRESULT and 
FpSETRESULT.

llvm-svn: 16247
 2004-09-08 18:29:31 +00:00
Alkis Evlogimenos
3540de9ea6 A call instruction should implicitely define ST0 since the return 
value is returned in that register. The pseudo instructions
FpGETRESULT and FpSETRESULT shold also have an implicity use and def
of ST0 repsecitvely.

llvm-svn: 16246
 2004-09-08 16:54:54 +00:00
Chris Lattner
5e7e9b6c26 Remove a bunch of ad-hoc target-specific flags that were only used by the 
old asmprinter.

llvm-svn: 15660
 2004-08-11 07:12:04 +00:00
Chris Lattner
3cef2f82ff Add asmprintergen support for the last X86 instruction that needs it: pcrelative calls. 
llvm-svn: 15657
 2004-08-11 06:59:12 +00:00
Chris Lattner
9c171be048 Scrunch memoperands, add a few more for floating point memops 
Eliminate the FPI*m classes, converting them to use FPI instead.

llvm-svn: 15655
 2004-08-11 06:50:10 +00:00
Chris Lattner
b287047c3f Make FPI take asm string and operand list 
llvm-svn: 15653
 2004-08-11 05:54:16 +00:00
Chris Lattner
c304bf7e03 Nuke the Im*i* patterns, by asmprintergenifying all users. 
llvm-svn: 15652
 2004-08-11 05:31:07 +00:00
Chris Lattner
65ab459759 X86 instructions that read-modify-write memory are not LLVM two-address instructions. 
llvm-svn: 15651
 2004-08-11 05:07:25 +00:00
Chris Lattner
384711a69c Get rid of the Im8, Im16, Im32 classes, converting more instructions over to 
asmprintergeneration

llvm-svn: 15650
 2004-08-11 04:31:00 +00:00
Chris Lattner
b66b9cd4a9 Convert asmprinter to new style of instruction printer 
Start asmprintergen'ifying machine instrs with memory operands.

llvm-svn: 15646
 2004-08-11 02:25:00 +00:00
Chris Lattner
5cf0a20d4f This is purely a formatting patch that gets us closer to the mecca of fitting 
X86InstrInfo.td into 80 columns

llvm-svn: 15629
 2004-08-10 21:21:30 +00:00
Chris Lattner
f6c4de46e0 Drop the first argument of FPI, and asmprinterify fxch 
llvm-svn: 15628
 2004-08-10 21:02:13 +00:00
Chris Lattner
97abe28059 This purely mechanical patch gives the "I" tblgen class operand list and asm 
string operands, and adjusts all users to pass them in instead of using II.

llvm-svn: 15624
 2004-08-10 20:17:41 +00:00
Chris Lattner
332fa9be1c Convert Ii32 instructions over to use the asmprinter generator 
llvm-svn: 15621
 2004-08-10 19:06:36 +00:00
Chris Lattner
068209661a Convert the Ii16 instructions over 
llvm-svn: 15606
 2004-08-10 16:22:02 +00:00
Chris Lattner
315782f0ac Convert all Ii8 instructions over to the autogenerated asmprinter. 
llvm-svn: 15605
 2004-08-10 16:09:54 +00:00
Chris Lattner
df7c9d0339 Convert all I<> instructions to asmformat. 
Delete the 'name' field of all instructions that have asmformats.

llvm-svn: 15403
 2004-08-01 09:52:59 +00:00
Chris Lattner
90a4b737dd Eliminate 3 of the X86 printImplicit* flags. 
llvm-svn: 15398
 2004-08-01 08:23:17 +00:00
Chris Lattner
0c5ab21dcd Convert more instructions over to the asmprinter 
llvm-svn: 15396
 2004-08-01 08:13:11 +00:00
Chris Lattner
6c596faddb Switch more instructions over to using the asmprinter. Fix bugs in the emission 
of in/out instructions (missing %'s on registers).

llvm-svn: 15393
 2004-08-01 07:44:35 +00:00
Chris Lattner
9a7b050ebb Specify an asm string and operands lists for a bunch of instructions. 
This only really covers no-operand instructions so far.

llvm-svn: 15387
 2004-08-01 06:01:00 +00:00
Chris Lattner
9bce44c8cc Entirely eliminate all patterns and expanders from this file. We shall go 
with an incremental approach rather than a revolutionary approach.

llvm-svn: 15379
 2004-08-01 03:25:01 +00:00
Chris Lattner
9a23ab1e63 Mark barrier instructions. Execution does not fall through uncond branches 
or return intructions.

llvm-svn: 15356
 2004-07-31 02:10:53 +00:00
Chris Lattner
7d8093efb1 No really, these are dead now 
llvm-svn: 14145
 2004-06-11 04:50:14 +00:00
Chris Lattner
a8e603b719 Now that compare instructions aren't lumped in with the other twoargfp instructions, 
we can get rid of the FpUCOM/FpUCOMi pseudo instructions, which makes stuff simpler
and faster.

llvm-svn: 14144
 2004-06-11 04:49:02 +00:00
Chris Lattner
b050f778ca Introduce a new FP instruction type to separate the compare cases from the 
twoarg cases.

llvm-svn: 14143
 2004-06-11 04:41:24 +00:00
Chris Lattner
4c8b57ea31 Add support for the setp instructions 
llvm-svn: 14140
 2004-06-11 04:30:06 +00:00
Chris Lattner
15ac62827e Add immediate forms of in/out. Use let to shorten lines 
llvm-svn: 12895
 2004-04-13 17:19:31 +00:00
Chris Lattner
43f754339a Fix issues that the local allocator has dealing with instructions that implicitly use ST(0) 
llvm-svn: 12855
 2004-04-12 03:02:48 +00:00
Chris Lattner
9cdc472518 No really, fix printing for LLC. I gotta get a way for CVS to whine at me if 
I have unsaved emacs buffers, geeze...

llvm-svn: 12854
 2004-04-12 01:52:04 +00:00
Chris Lattner
f1d59be0e8 Correct printing for LLC and the encoding for the JIT 
llvm-svn: 12853
 2004-04-12 01:50:04 +00:00
Chris Lattner
cfb7144bf1 Add two new instructions 
llvm-svn: 12850
 2004-04-12 01:38:55 +00:00
Chris Lattner
dda382531e Add some new instructions 
llvm-svn: 12838
 2004-04-11 20:24:15 +00:00
John Criswell
8740c3767d Changes recommended by Chris: 
InstSelectSimple.cpp:
  Change the checks for proper I/O port address size into an exit() instead
  of an assertion.  Assertions aren't used in Release builds, and handling
  this error should be graceful (not that this counts as graceful, but it's
  more graceful).

  Modified the generation of the IN/OUT instructions to have 0 arguments.
X86InstrInfo.td:
  Added the OpSize attribute to the 16 bit IN and OUT instructions.

llvm-svn: 12786
 2004-04-08 22:39:13 +00:00
John Criswell
f6b16ea70b Added the llvm.readport and llvm.writeport intrinsics for x86. These do 
I/O port instructions on x86.  The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output.  This required adjustment to some
methods so that a leading comma would or would not be printed.

llvm-svn: 12782
 2004-04-08 20:31:47 +00:00
Chris Lattner
993d6106c7 Fix incorrect encoding of some ADC and SBB instuctions 
llvm-svn: 12710
 2004-04-06 19:20:32 +00:00
Chris Lattner
e84f12a165 The sbb instructions really ARE sbb's, not adc's 
llvm-svn: 12682
 2004-04-06 02:02:11 +00:00
Alkis Evlogimenos
85e007a6dc Fix type in comments 
llvm-svn: 12611
 2004-04-02 16:02:50 +00:00
Alkis Evlogimenos
20b074682c Add more ADC and SBB variants 
llvm-svn: 12607
 2004-04-02 07:11:10 +00:00
Chris Lattner
e4fa3010db Add FP conditional move instructions, which annoyingly have special properties 
that require the asmwriter to be extended (printing implicit uses before the
explicit operands)

llvm-svn: 12574
 2004-03-31 22:02:13 +00:00
Chris Lattner
57968a98df Fix some serious bugs in the cmov descriptions, which didn't cause a problem because 
we never generated them

Make indentation a bit more consistent

llvm-svn: 12549
 2004-03-30 20:18:02 +00:00
Alkis Evlogimenos
6ac147a7fb Add LAHF instruction 
llvm-svn: 12424
 2004-03-15 17:20:14 +00:00
Alkis Evlogimenos
da990ad8a4 Add support for a wider range of CMOV instructions. 
llvm-svn: 12336
 2004-03-12 17:59:56 +00:00
Alkis Evlogimenos
7c0224327e Differentiate between extended precision floats (80-bit) and double precision floats (64-bit) 
llvm-svn: 12254
 2004-03-09 03:37:54 +00:00
Alkis Evlogimenos
65649a50e9 Add memory operand version of conditional move. 
llvm-svn: 12190
 2004-03-07 03:19:11 +00:00
Alkis Evlogimenos
8d8f872b3d Use correct template for SHLD and SHRD instructions so that the memory 
operand size is correctly specified.

llvm-svn: 11997
 2004-02-29 09:19:40 +00:00
Alkis Evlogimenos
7ecfe0a839 A big X86 instruction rename. The instructions are renamed to make 
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory

llvm-svn: 11995
 2004-02-29 08:50:03 +00:00
Alkis Evlogimenos
0f96b44e0e Use correct template for ADC instruction with memory operands. 
llvm-svn: 11974
 2004-02-29 02:18:17 +00:00
Alkis Evlogimenos
6815402082 SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them 
to denote this fact.

llvm-svn: 11972
 2004-02-28 23:46:44 +00:00
Alkis Evlogimenos
e8dac99a43 Floating point loads/stores act on memory operands. Rename them to 
denote this fact.

llvm-svn: 11971
 2004-02-28 23:42:35 +00:00
Alkis Evlogimenos
1d71a15be9 Rename instruction templates to be easier to the human eye to 
parse. The name is now I (operand size)*. For example:

Im32 -> instruction with 32-bit memory operands.

Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
          operands.

llvm-svn: 11970
 2004-02-28 23:09:03 +00:00
Alkis Evlogimenos
f208a0fd81 Each instruction now has both an ImmType and a MemType. This describes 
the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).

llvm-svn: 11967
 2004-02-28 22:02:05 +00:00
Alkis Evlogimenos
977dbaadf7 Do not generate instructions with mismatched memory/immediate sized 
operands. The X86 backend doesn't handle them properly right now.

llvm-svn: 11944
 2004-02-28 06:01:43 +00:00
Alkis Evlogimenos
84f00e93f7 Further comment updates. 
llvm-svn: 11933
 2004-02-28 03:20:31 +00:00
Alkis Evlogimenos
edbe362160 Update comments. 
llvm-svn: 11932
 2004-02-28 03:12:31 +00:00
Alkis Evlogimenos
0f91ce52a0 My previous commit broke the jit. The shift instructions always take 
an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.

A bug still exists:

def SHLDmri32  : I2A8 <"shld", 0xA4, MRMDestMem>, TB;           // [mem32] <<= [mem32],R32 imm8

The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.

llvm-svn: 11931
 2004-02-28 02:56:26 +00:00
Alkis Evlogimenos
ace6d81654 Fix argument size for SHL, SHR, SAR, SHLD and SHRD families of 
instructions.

llvm-svn: 11923
 2004-02-27 19:46:30 +00:00
Alkis Evlogimenos
839c70f45d Fix encoding of ADD and SUB family of instructions. Also rearrange 
them so that they are consistent with AND, XOR, etc...

llvm-svn: 11922
 2004-02-27 18:57:00 +00:00
Alkis Evlogimenos
56d357aa23 Rename MRMS[0-7]{r,m} to MRM[0-7]{r,m}. 
llvm-svn: 11921
 2004-02-27 18:55:12 +00:00
Alkis Evlogimenos
5ac109957f Add memory operand folding support for the SETcc family of 
instructions.

llvm-svn: 11907
 2004-02-27 16:13:37 +00:00
Alkis Evlogimenos
0742b93bb9 Add memory operand folding support for SHLD and SHRD instructions. 
llvm-svn: 11905
 2004-02-27 15:03:18 +00:00
Alkis Evlogimenos
b1f67f6741 Add memory operand folding support for SHL, SHR and SAR, SHLD instructions. 
llvm-svn: 11903
 2004-02-27 09:28:43 +00:00
Alkis Evlogimenos
cf49d13ed2 Rename SHL, SHR, SAR, SHLD and SHLR instructions to make them 
consistent with the rest and also pepare for the addition of their
memory operand variants.

llvm-svn: 11902
 2004-02-27 06:57:05 +00:00
Chris Lattner
f9acb33dfd Add a new cmove instruction 
llvm-svn: 11722
 2004-02-23 01:16:05 +00:00
Alkis Evlogimenos
7ec1bad952 Fix argument size for MOVSX and MOVZX instructions. 
llvm-svn: 11576
 2004-02-18 16:20:40 +00:00
Alkis Evlogimenos
c6f0651e5c These store to memory too. 
llvm-svn: 11558
 2004-02-17 17:53:48 +00:00
Chris Lattner
88271db3bc These store to memory, not read from it. 
llvm-svn: 11556
 2004-02-17 17:46:50 +00:00
Alkis Evlogimenos
b815fd46ec Add TEST and XCHG memory operand support. 
llvm-svn: 11550
 2004-02-17 15:48:42 +00:00
Alkis Evlogimenos
32a5b0fd6c Add OR and XOR memory operand support. 
llvm-svn: 11549
 2004-02-17 15:33:14 +00:00
Alkis Evlogimenos
135c4faa55 Add memory operand folding support for MUL, DIV, IDIV, NEG, NOT, 
MOVSX, and MOVZX.

llvm-svn: 11546
 2004-02-17 09:14:23 +00:00
Alkis Evlogimenos
d7e3cc8d65 Add CMP{rm,mr,mi}{8,16,32}, INCm{8,16,32} and DECm{8,16,32} instructions. 
llvm-svn: 11544
 2004-02-17 08:49:00 +00:00
Alkis Evlogimenos
638db7b5aa Add SUB{rm,mr,mi}{8,16,32} instructions. 
llvm-svn: 11543
 2004-02-17 08:17:40 +00:00
Alkis Evlogimenos
28691e063b Add support for ADC{rm.mr}32 and SBB{rm,mr}32. 
llvm-svn: 11540
 2004-02-17 08:06:31 +00:00
Chris Lattner
d4b2f4ef32 Fix the mneumonics for the mov instructions to have the source and destination 
order in the correct sense!! Arg!

llvm-svn: 11530
 2004-02-17 06:28:19 +00:00
Chris Lattner
5757579731 Fix the last crimes against nature that used the 'ir' ordering to use the 
'ri' ordering instead... no it's not possible to store a register into an
immediate!

llvm-svn: 11529
 2004-02-17 06:24:02 +00:00
Chris Lattner
16666f8bd2 Rename MOVi[mr] instructions to MOV[rm]i 
llvm-svn: 11527
 2004-02-17 06:16:44 +00:00
Chris Lattner
9751eb8ab9 Add mem forms of AND instructions 
llvm-svn: 11521
 2004-02-17 05:25:50 +00:00
Chris Lattner
3c514e8a54 Rename the IMULri* instructions to IMULrri, as they are actually three address 
instructions.  Add forms of these instructions that read from memory

llvm-svn: 11518
 2004-02-17 04:26:43 +00:00
Alkis Evlogimenos
657876c656 Add two more variants of add. Update comments. 
llvm-svn: 11510
 2004-02-16 23:48:42 +00:00
Chris Lattner
d8cc48da34 Add some ADD instructions that take memory operands for Alkis 
llvm-svn: 11502
 2004-02-16 18:19:31 +00:00
Chris Lattner
cc5bf36481 Add support for the 'pop' instruction 
llvm-svn: 11451
 2004-02-14 21:06:02 +00:00
Chris Lattner
c87772961e Urg, right. These need an input value... 
llvm-svn: 11443
 2004-02-14 04:47:23 +00:00
Chris Lattner
6890963e48 add 'rep stos[bwd]' instructions 
llvm-svn: 11441
 2004-02-14 04:45:37 +00:00
Chris Lattner
d1c4f4c833 Add support for the rep movs[bwd] instructions, and emit them when code 
generating the llvm.memcpy intrinsic.

llvm-svn: 11351
 2004-02-12 17:53:22 +00:00
Alkis Evlogimenos
a5458ae146 IMULri* instructions do not require their first two registers operands 
to be the same (IOW they are not two address instructions).

llvm-svn: 11117
 2004-02-04 17:21:04 +00:00
Chris Lattner
7b6e8f1f70 Add the ftst instruction 
llvm-svn: 11095
 2004-02-03 07:27:50 +00:00
Chris Lattner
06f08a26ac No need to declare implicit uses/defs of ST0 
llvm-svn: 11081
 2004-02-02 19:57:45 +00:00
Chris Lattner
71c12c8e0d Generate the fchs instruction to negate a floating point number 
llvm-svn: 11078
 2004-02-02 19:31:38 +00:00
Alkis Evlogimenos
41bd8284e3 Remove floating point killer pass. This is now implemented in the 
instruction selector by adding a new pseudo-instruction
FP_REG_KILL. This instruction implicitly defines all x86 fp registers
and is a terminator so that passes which add machine code at the end
of basic blocks (like phi elimination) do not add instructions between
it and the branch or return instruction.

llvm-svn: 10562
 2003-12-20 16:22:59 +00:00
John Criswell
de34542f41 Added LLVM copyright header. 
llvm-svn: 9321
 2003-10-21 15:17:13 +00:00
Chris Lattner
c4f8226aaf Emit x86 instructions for: A = B op C, where A and B are 16-bit registers, 
C is a constant which can be sign-extended from 8 bits without value loss,
and op is one of: add, sub, imul, and, or, xor.

This allows the JIT to emit the one byte version of the constant instead of
the two or 4 byte version.  Because these instructions are very common, this
can save a LOT of code space.  For example, I sampled two benchmarks, 176.gcc
and 254.gap.

BM        Old     New    Reduction
176.gcc 2673621 2548962  4.89%
254.gap  498261  475104  4.87%

Note that while the percentage is not spectacular, this did eliminate
124.6 _KILOBYTES_ of codespace from gcc.  Not bad.

Note that this doesn't effect the llc version at all, because the assembler
already does this optimization.

llvm-svn: 9284
 2003-10-20 05:53:31 +00:00
Chris Lattner
5a577c0b28 * Rename X86::IMULr16 -> X86::IMULrr16 
* Implement R1 = R2 * C where R1 and R2 are 32 or 16 bits. This avoids an
  extra copy into a register, reducing register pressure.

llvm-svn: 9278
 2003-10-20 03:42:58 +00:00
Chris Lattner
57825f087d Add some new instructions. Wheee 
llvm-svn: 9266
 2003-10-19 19:25:35 +00:00
Chris Lattner
8d79ae7383 Add support for unconditional branches and for emitting JE instructions 
llvm-svn: 7872
 2003-08-15 04:50:49 +00:00
Chris Lattner
be0530bab9 Add basic support for 16 and 32 bit function arguments! 
llvm-svn: 7755
 2003-08-11 21:30:00 +00:00
Chris Lattner
1ecd1818a0 Add (ret int) expander so that we can at least write testcases 
llvm-svn: 7730
 2003-08-11 15:48:00 +00:00
Chris Lattner
3f4b5cf09a Add patterns for multiply, and, or, and xor 
llvm-svn: 7725
 2003-08-11 15:23:25 +00:00
Chris Lattner
83831c66fc add a pattern for RET, immediates no longer need to be explicitly typed 
llvm-svn: 7635
 2003-08-06 15:31:35 +00:00
Chris Lattner
17fc21b5fa This is the real fix for the previous register allocator problem. 
Physical registers should not float around.

llvm-svn: 7587
 2003-08-05 00:48:47 +00:00
Chris Lattner
cf51f31c3e Add patterns for (mov R, R) (mov R, I) and subtracts. The moves are to enable 
testing, the subtracts are because I was in the neighborhood.

llvm-svn: 7581
 2003-08-04 21:18:19 +00:00
Chris Lattner
900d31f5ba Change comments into something that TableGen can read! 
llvm-svn: 7580
 2003-08-04 21:08:29 +00:00
Chris Lattner
0d7b042206 transition to using let instead of set 
llvm-svn: 7564
 2003-08-04 04:59:56 +00:00
Chris Lattner
89b4a26e56 Add new TableGen instruction definitions 
llvm-svn: 7537
 2003-08-03 21:54:21 +00:00