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Commit Graph

218931 Commits

Author SHA1 Message Date
Nikita Popov
5d9c2de528 [SimplifyCFG] Fix if conversion with opaque pointers
We need to make sure that the value types are the same. Otherwise
we both may not have the necessary dereferenceability implication,
nor can we directly form the desired select pattern.

Without opaque pointers this is enforced implicitly through the
pointer comparison.
2021-07-21 22:24:07 +02:00
Nikita Popov
f265bf7812 [SimplifyCFG] Regenerate test checks (NFC) 2021-07-21 22:24:07 +02:00
Stanislav Mekhanoshin
5ee240dc93 [AMDGPU] Move perfhint analysis
This is SCC pass, moving it to the end of SCC PM saves one
Function PM. This needs the analysis to take into account
memory access width since it is now places after the
load/store optimizer (D105651).

Differential Revision: https://reviews.llvm.org/D105652
2021-07-21 13:06:49 -07:00
Jessica Paquette
cb309a9442 [AArch64][GlobalISel] Widen s2 and s4 G_IMPLICIT_DEF + G_FREEZE
These had

```
.clampScalar(0, s1, 64)
.widenScalarToNextPow2(0, 8)
```

If you have s2 or s4, then `widenScalarToNextPow2` does nothing.

This changes the `widenScalarToNextPow2` rule to use s8 as the minimum type
instead, allowing us to correctly widen s2 and s4.

This does not impact s1, since it's marked as legal already.

Differential Revision: https://reviews.llvm.org/D106413
2021-07-21 12:59:20 -07:00
John McCall
9f30d2a5ae Fix a bug in OptimizedStructLayout when filling gaps before
fixed fields with highly-aligned flexible fields.

The code was not considering the possibility that aligning
the current offset to the alignment of a queue might push
us past the end of the gap.  Subtracting the offsets to
figure out the maximum field size for the gap then overflowed,
making us think that we had nearly unbounded space to fill.

Fixes PR 51131.
2021-07-21 15:47:18 -04:00
Stanislav Mekhanoshin
5b3e6630e5 [AMDGPU] Tune perfhint analysis to account access width
A function with less memory instructions but wider access
is the same as a function with more but narrower accesses
in terms of memory boundness. In fact the pass would give
different answers before and after vectorization without
this change.

Differential Revision: https://reviews.llvm.org/D105651
2021-07-21 12:46:10 -07:00
Craig Topper
6a9e481d78 [RISCV] Cleanup comment around vector tail policy handling. NFC
vmv.x.s and reductions don't ignore tail policy anymore.
2021-07-21 12:45:08 -07:00
Sanjay Patel
ffb5e7ee28 [SROA] avoid crash on memset with constant expression length
https://llvm.org/PR50888
2021-07-21 15:20:28 -04:00
Gulfem Savrun Yeniceri
8179b3101d Revert "[profile] Add binary id into profiles"
Revert "[profile] Change linkage type of a compiler-rt func"
This reverts commits f984ac2715f71c38a7872fa2c2ad535b3d4fa285 and
467c7191249b76abff33853b1692a77f327c2422 because it broke some builds.
2021-07-21 19:15:18 +00:00
Eli Friedman
a9e9596567 [AArch64] Regenerate and add more tests for i128 atomics.
Generating these tests unfortunately means a lot of junk, but it's hard
to write/update these tests by hand.

Added tests focus on atomic orderings for cmpxchg.

Actually writing out these tests showed some potentially dubious
results; we should probably consider using casp for 128-bit atomic
load/store/rmw.
2021-07-21 11:28:27 -07:00
Giorgis Georgakoudis
7e612fb3a1 [Attributor] Preserve BBs and instructions added in AA manifests
Manifesting AbstractAttributes may add new BBs in the IR. This patch provides an interface to register those BBs in the Attributor so that those BBs and containing instructions are not deleted as dead.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106383
2021-07-21 11:27:00 -07:00
Eli Friedman
4384bac220 [SelectionDAG] Fix the representation of ISD::STEP_VECTOR.
The existing rule about the operand type is strange.  Instead, just say
the operand is a TargetConstant with the right width.  (Legalization
ignores TargetConstants, so it doesn't matter if that width is legal.)

Highlights:

1. I had to substantially rewrite the AArch64 isel patterns to expect a
TargetConstant.  Nothing too exotic, but maybe a little hairy. Maybe
worth considering a target-specific node with some dagcombines instead
of this complicated nest of isel patterns.
2. Our behavior on RV32 for vectors of i64 has changed slightly. In
particular, we correctly preserve the width of the arithmetic through
legalization.  This changes the DAG a bit. Maybe room for
improvement here.
3. I explicitly defined the behavior around overflow. This is necessary
to make the DAGCombine transforms legal, and I don't think it causes any
practical issues.

Differential Revision: https://reviews.llvm.org/D105673
2021-07-21 10:58:40 -07:00
Gulfem Savrun Yeniceri
5edc17d32b [profile] Add binary id into profiles
This patch adds binary id into profiles to easily associate binaries
with the corresponding profiles. There is an RFC that discusses
the motivation, design and implementation in more detail:
https://lists.llvm.org/pipermail/llvm-dev/2021-June/151154.html

Differential Revision: https://reviews.llvm.org/D102039
2021-07-21 17:55:43 +00:00
Giorgis Georgakoudis
2b07724890 [Attributor][NFC] Modify isAssumedHeapToStack for const argument
There is no need for a non-const argument interface and the const argument modification covers existing and upcoming use cases.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106418
2021-07-21 10:28:21 -07:00
Giorgis Georgakoudis
ca49ab772d [OpenMP] Expose libomptarget function to get HW thread id
The patch exposes the libomptarget runtime function that gets the hardware thread id through the kmpc API. This is to be used in SPMDization for checking the thread id to execute regions by a single thread in a block.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106323
2021-07-21 10:26:04 -07:00
Thomas Lively
d9c07b1710 [WebAssembly] Codegen for v128.load{32,64}_zero
Replace the experimental clang builtins and LLVM intrinsics for these
instructions with normal instruction selection patterns. The wasm_simd128.h
intrinsics header was already using portable code for the corresponding
intrinsics, so now it produces the correct instructions.

Differential Revision: https://reviews.llvm.org/D106400
2021-07-21 09:02:12 -07:00
Quinn Pham
913473cb58 [PowerPC] Removing a REQUIRES line from llvm test
The test has been moved to the correct directory so this
`REQUIRES` line is not needed.
2021-07-21 10:52:23 -05:00
Eric Astor
be0514d8cd [ms] [llvm-ml] Restrict implicit RIP-relative addressing to named-variable references
ML64.EXE applies implicit RIP-relative addressing only to memory references that include a named-variable reference.

Reviewed By: mstorsjo

Differential Revision: https://reviews.llvm.org/D105372
2021-07-21 11:49:58 -04:00
Arthur Eubanks
f3b675c071 [NewPM][Inliner] Check if deleted function is in current SCC
In weird cases, the inliner will inline internal recursive functions,
sometimes causing them to have no more uses, in which case the
inliner will mark the function to be deleted. The function is
actually deleted after the call to
updateCGAndAnalysisManagerForCGSCCPass(). In
updateCGAndAnalysisManagerForCGSCCPass(), UR.UpdatedC may be set to
the SCC containing the function to be deleted. Then the inliner calls
CG.removeDeadFunction() which can cause that SCC to be deleted, even
though it's still stored in UR.UpdatedC.

We could potentially check in the wrappers/pass managers if UR.UpdatedC
is in UR.InvalidatedSCCs before doing anything with it, but it's safer
to do this as close to possible to the call to CG.removeDeadFunction()
to avoid issues with allocating a new SCC in the same address as
the deleted one.

It's hard to find a small test case since we need to have recursive
internal functions be reachable from non-internal functions, yet they
need to become non-recursive and not referenced by other functions when
inlined.

Similar to https://reviews.llvm.org/D106306.

Fixes PR50788.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D106405
2021-07-21 08:47:45 -07:00
Jon Roelofs
48d5dbf972 [MachineVerifier] Make INSERT_SUBREG diagnostic respect operand 2 subregs
This came out of post-commit review: https://reviews.llvm.org/D105953#inline-1012919

Thanks uabelho!
2021-07-21 08:47:17 -07:00
Eric Astor
2b759c7f74 [ms] [llvm-ml] Support built-in text macros
Add support for all built-in text macros supported by ML64:
@Date, @Time, @FileName, @FileCur, and @CurSeg.

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D104965
2021-07-21 11:44:09 -04:00
Eric Astor
7dfafaa71e [ms] [llvm-ml] Add support for numeric built-in symbols
Support @Version and @Line as built-in symbols. For now, resolves @Version to 1427 (the same as for the VS 2019 release of ML.EXE).

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D104964
2021-07-21 11:43:07 -04:00
Quinn Pham
55cdb9450e [PowerPC] Move backend test to fix non PPC bots
Moving `llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll` to
`llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.ll`
2021-07-21 09:36:29 -05:00
David Spickett
d9349db6cc [PowerPC] Require power-pc target for new builtin test
The llvm test added in e002d251dd34fc1855e3a17feafd358d55d92ed8
was missing a REQUIRES. Failed to run on our AArch64 only bot:
https://lab.llvm.org/buildbot/#/builders/171/builds/1262
2021-07-21 14:19:26 +00:00
Kerry McLaughlin
b539edfe7a Revert "[LV] Use lookThroughAnd with logical reductions"
Reverting patch due to buildbot failures.

This reverts commit e22a59967251294ccdac6b43a06f48c1b7075240.
2021-07-21 15:16:00 +01:00
Simon Pilgrim
26f5246950 [LoopVectorize] Regenerate sve-vector-reverse.ll test checks 2021-07-21 15:14:04 +01:00
Kazu Hirata
5f539e48b6 [InstCombine] Remove CreateOverflowTuple (NFC)
The last use was removed On Jun 3, 2020 in commit
2a6c871596ce8bdd23501a96fd22f0f16d3cfcad.
2021-07-21 07:07:53 -07:00
Quinn Pham
2b9fe667ec [PowerPC] Floating Point Builtins for XL Compat.
This patch is in a series of patches to provide
builtins for compatibility with the XL compiler.
This patch adds builtins related to floating point
operations

Reviewed By: #powerpc, nemanjai, amyk, NeHuang

Differential Revision: https://reviews.llvm.org/D103986
2021-07-21 08:33:39 -05:00
Jakub Kuderski
fe1c7a103a [ADT] Add initializer_list constructor to SmallDenseMap
Make it easier to initialize small maps inline. Note that DenseMap already has an initializer_list constructor.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D106363
2021-07-21 09:32:16 -04:00
Simon Pilgrim
94824eaca5 [InstCombine] Regenerate gep-custom-dl.ll test checks 2021-07-21 14:29:34 +01:00
Sebastian Neubauer
5f547ad156 [AMDGPU] Improve killed check for vgpr optimization
The killed flag is not always set. E.g. when a variable is used in a
loop, it is never marked as killed, although it is unused in following
basic blocks. Also, we try to deprecate kill flags and not use them.

Check if the register is live in the endif block. If not, consider it
killed in the then and else blocks.

The vgpr-liverange tests have two new tests with loops
(pre-committed, so the diff is visible).
I also needed to change the subtarget to gfx10.1, otherwise calls
are not working.

Differential Revision: https://reviews.llvm.org/D106291
2021-07-21 15:24:59 +02:00
Sebastian Neubauer
9894eb12d3 [AMDGPU] Precommit vgpr-liverange tests 2021-07-21 15:24:59 +02:00
Guillaume Chatelet
a29bc1a45f [llvm] Add enum iteration to Sequence
This patch allows iterating typed enum via the ADT/Sequence utility.

It also changes the original design to better separate concerns:
 - `StrongInt` only deals with safe `intmax_t` operations,
 - `SafeIntIterator` presents the iterator and reverse iterator
 interface but only deals with safe `StrongInt` internally.
 - `iota_range` only deals with `SafeIntIterator` internally.

 This design ensures that operations are always valid. In particular,
 "Out of bounds" assertions fire when:
  - the `value_type` is not representable as an `intmax_t`
  - iterator operations make internal computation underflow/overflow
  - the internal representation cannot be converted back to `value_type`

Differential Revision: https://reviews.llvm.org/D106279
2021-07-21 12:48:53 +00:00
Simon Pilgrim
912cf6c6cb [InstCombine] Add multiuse test for D106352 2021-07-21 13:48:15 +01:00
Roman Lebedev
aeb244cb4e [NFC][VectorCombine] Load widening: add a few more negative tests 2021-07-21 15:21:37 +03:00
Simon Pilgrim
33f952ff1c IFSStub.cpp - consistently use default case to silence 'not all control paths return' MSVC warnings. NFCI. 2021-07-21 11:59:34 +01:00
David Green
ddd62877c6 [LV] Make use of PatternMatchers in getReductionPatternCost. NFC
Pulled out of D106166, this modifies getReductionPatternCost to use
PatternMatchers, hopefully simplifying the code a little.
2021-07-21 11:34:30 +01:00
Jay Foad
fd3020376e [AMDGPU] NFC refactoring in isel for buffer access intrinsics
Rename getBufferOffsetForMMO to updateBufferMMO and pass in the MMO to
be updated, in preparation for the bug fix in D106284.

Call updateBufferMMO consistently for all buffer intrinsics, even the
ones that use setBufferOffsets to decompose a combined offset
expression.

Add a getIdxEn helper function.

Differential Revision: https://reviews.llvm.org/D106354
2021-07-21 11:12:49 +01:00
Rosie Sumpter
b11b07e0b8 [LoopFlatten][LoopInfo] Use Loop to identify latch compare instruction
Make getLatchCmpInst non-static and use it in LoopFlatten as a more
robust way of identifying the compare.

Differential Revision: https://reviews.llvm.org/D106256
2021-07-21 10:14:18 +01:00
Kerry McLaughlin
8625c5dcda [LV] Use lookThroughAnd with logical reductions
If a reduction Phi has a single user which `AND`s the Phi with a type mask,
`lookThroughAnd` will return the user of the Phi and the narrower type represented
by the mask. Currently this is only used for arithmetic reductions, whereas loops
containing logical reductions will create a reduction intrinsic using the widened
type, for example:

  for.body:
    %phi = phi i32 [ %and, %for.body ], [ 255, %entry ]
    %mask = and i32 %phi, 255
    %gep = getelementptr inbounds i8, i8* %ptr, i32 %iv
    %load = load i8, i8* %gep
    %ext = zext i8 %load to i32
    %and = and i32 %mask, %ext
    ...

^ this will generate an and reduction intrinsic such as the following:
    call i32 @llvm.vector.reduce.and.v8i32(<8 x i32>...)

The same example for an add instruction would create an intrinsic of type i8:
    call i8 @llvm.vector.reduce.add.v8i8(<8 x i8>...)

This patch changes AddReductionVar to call lookThroughAnd for other integer
reductions, allowing loops similar to the example above with reductions such
as and, or & xor to vectorize.

Reviewed By: david-arm, dmgreen

Differential Revision: https://reviews.llvm.org/D105632
2021-07-21 09:56:00 +01:00
Cullen Rhodes
23e61e0bd4 [AArch64][SME] Support .arch and .arch_extension assembler directives
Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D105566
2021-07-21 08:40:27 +00:00
Tim Northover
a5f7171155 ARM: don't return by popping PC if we have to adjust the stack afterwards.
In mandatory tail calling conventions we might have to deallocate stack
space used by our arguments before return. This happens after popping
CSRs, so the pop cannot be turned into the return itself in this case.

The else branch here was already a nop, so removing it as a tidy-up.
2021-07-21 09:35:14 +01:00
Tim Northover
bd9402142a AArch64: support 8 & 16-bit atomic operations in GlobalISel
We have SelectionDAG patterns for 8 & 16-bit atomic operations, but they
assume the value types will have been legalized to 32-bits. So this adds
the ability to widen them to both AArch64 & generic GISel
infrastructure.
2021-07-21 09:35:14 +01:00
Cullen Rhodes
f8b2068905 [AArch64][SME] Add mova instructions
This patch adds the mova instruction to insert/extract an SVE vector
register to/from a ZA tile vector.

The preferred MOV aliases are also implemented.

Depends on D105572.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

Reviewed By: david-arm, CarolineConcatto

Differential Revision: https://reviews.llvm.org/D105574
2021-07-21 08:20:01 +00:00
Cullen Rhodes
db780333ba [AArch64][SME] Add ldr and str instructions
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

Reviewed By: kmclaughlin

Differential Revision: https://reviews.llvm.org/D105573
2021-07-21 08:17:13 +00:00
Timm Bäder
e396e90533 [llvm][tools] Hide more unrelated LLVM tool options
Differential Revision: https://reviews.llvm.org/D106366
2021-07-21 09:14:04 +02:00
Lang Hames
864fe23f53 [ORC][ORC-RT] Revert MachO TLV patches while I investigate more bot failures.
This reverts commit d4abdefc998a1ee19d5edc79ec233774cbf64f6a ("[ORC-RT] Rename
macho_tlv.x86-64.s to macho_tlv.x86-64.S (uppercase suffix)", and
a7733e9556b5a6334c910f88bcd037e84e17e3fc ("Re-apply "[ORC][ORC-RT] Add initial
native-TLV support to MachOPlatform."), while I investigate failures on
ccache builders (e.g. https://lab.llvm.org/buildbot/#/builders/109/builds/18981)
2021-07-21 15:52:33 +10:00
Lang Hames
248727a066 Re-apply "[ORC][ORC-RT] Add initial native-TLV support to MachOPlatform."
Reapplies fe1fa43f16beac1506a2e73a9f7b3c81179744eb, which was reverted in
6d8c63946cc259c0af02584b7cc690dde11dea35, with fixes:

1. Remove .subsections_via_symbols directive from macho_tlv.x86-64.s (it's
not needed here anyway).

2. Return error from pthread_key_create to the MachOPlatform to silence unused
variable warning.
2021-07-21 15:11:22 +10:00
Tianqing Wang
5f5c9808cd [X86] Update MachineLoopInfo in CMOV conversion.
If a CMOV is in a loop and is converted to branches, CMOV conversion wouldn't
add newly created basic blocks to loop info. Since the candidates is collected
based on loops, instructions in these basic blocks will be ignored.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D104623
2021-07-21 10:53:46 +08:00
Ben Shi
6b99631a69 [RISCV][test] Add tests for mul optimization in the zba extension with SH*ADD
These tests will show the following optimization by future patches.

(mul x, 11) -> (SH1ADD (SH2ADD x, x), x)
(mul x, 19) -> (SH1ADD (SH3ADD x, x), x)
(mul x, 13) -> (SH2ADD (SH1ADD x, x), x)
(mul x, 21) -> (SH2ADD (SH2ADD x, x), x)
(mul x, 37) -> (SH2ADD (SH3ADD x, x), x)
(mul x, 25) -> (SH3ADD (SH1ADD x, x), x)
(mul x, 41) -> (SH3ADD (SH2ADD x, x), x)
(mul x, 73) -> (SH3ADD (SH3ADD x, x), x)

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106031
2021-07-21 10:16:56 +08:00