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3732 Commits

Author SHA1 Message Date
Dan Gohman
2498f902ff i128 and f80 are implemented for x86-64 now. 
llvm-svn: 55920
 2008-09-08 16:42:56 +00:00
Dan Gohman
331ed48bc7 Fix copy+pastos in comments. 
llvm-svn: 55918
 2008-09-08 16:31:35 +00:00
Anton Korobeynikov
cd3e839337 Drop unused variable 
llvm-svn: 55901
 2008-09-08 14:22:38 +00:00
Anton Korobeynikov
abd2198853 We do support EH on x86-64! 
llvm-svn: 55900
 2008-09-08 14:22:16 +00:00
Anton Korobeynikov
8528e4dc99 First draft of EH support on x86/64-linux 
llvm-svn: 55899
 2008-09-08 14:21:53 +00:00
Anton Korobeynikov
38cc49e19d Implement FRAME_TO_ARGS_OFFSET for x86-64 
llvm-svn: 55898
 2008-09-08 14:21:10 +00:00
Evan Cheng
66ef6517ad Add support to extend call operands when needed. Enable x86 fastisel call support. 
llvm-svn: 55891
 2008-09-08 06:35:17 +00:00
Evan Cheng
f016785579 Initial fastisel call support for C, Fast, and X86_FastCall calling conventions. It's meant to handle "simple" calls, i.e. no byval, structret, etc. It doesn't support multi-result returns either. 
Not yet turned on, it needs to support sext / zext of arguments and result.

llvm-svn: 55882
 2008-09-07 09:09:33 +00:00
Evan Cheng
ad262ec3a7 Some code clean up. 
llvm-svn: 55881
 2008-09-07 09:07:23 +00:00
Evan Cheng
6690ccd573 Handle x86 truncate to i8 with target hook for now. 
llvm-svn: 55877
 2008-09-07 08:47:42 +00:00
Owen Anderson
ef6d356c39 Fix constant pool loads, and remove broken versions of addConstantPoolReference. 
llvm-svn: 55868
 2008-09-06 01:11:01 +00:00
Owen Anderson
4d5723c58f Fix the X86 addConstantPoolReference, which had the operands in the wrong order. 
llvm-svn: 55867
 2008-09-06 00:50:00 +00:00
Eli Friedman
fecea4b498 Fix for PR2687: Add patterns to match sint_to_fp and fp_to_sint for <2 x 
i32>.  This is a little messy, but it works.

We should really get rid of the intrinsics, though, since they map
perfectly well to standard LLVM instructions.

llvm-svn: 55864
 2008-09-05 23:07:03 +00:00
Dan Gohman
930d0be24c Fix X86FastISel's shift and select code to reject illegal types. 
llvm-svn: 55857
 2008-09-05 21:27:34 +00:00
Dan Gohman
28e33e92e4 Fix the opcodes used by X86FastISel for shifts and conditional moves. 
llvm-svn: 55855
 2008-09-05 21:13:04 +00:00
Evan Cheng
5fd19547f4 Factor out code that emits load and store instructions. 
llvm-svn: 55854
 2008-09-05 21:00:03 +00:00
Owen Anderson
7866b1c4c3 Rename method. 
llvm-svn: 55853
 2008-09-05 20:49:33 +00:00
Dan Gohman
0be4bca4b6 X86FastISel support for shifts and conditional moves. 
llvm-svn: 55844
 2008-09-05 18:30:08 +00:00
Evan Cheng
10a350fa89 If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls. 
llvm-svn: 55840
 2008-09-05 17:24:07 +00:00
Dan Gohman
29cba19a2a Check a comparion's operand type for legality before 
expanding its operands.

llvm-svn: 55820
 2008-09-05 01:33:56 +00:00
Dan Gohman
121baa1723 Fix X86FastISel code for comparisons and conditional branches 
to check the result of getRegForValue before using it, and
to check for illegal operand types.

llvm-svn: 55819
 2008-09-05 01:15:35 +00:00
Dan Gohman
783f38e056 X86FastISel support for conditional branches. 
llvm-svn: 55816
 2008-09-05 01:06:14 +00:00
Owen Anderson
6d5b72d45a Add initial support for selecting constant materializations that require constant 
pool loads on X86 in fast isel.  This isn't actually used yet.

llvm-svn: 55814
 2008-09-05 00:06:23 +00:00
Dan Gohman
88c3de638e X86FastISel support for ICmpInst and FCmpInst. 
llvm-svn: 55811
 2008-09-04 23:26:51 +00:00
Evan Cheng
bd15e330d0 For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries. 
llvm-svn: 55807
 2008-09-04 22:59:58 +00:00
Devang Patel
f3770334a9 If function notes say optimize for size, then adjust alignment. 
llvm-svn: 55794
 2008-09-04 21:03:41 +00:00
Dan Gohman
e1f9be27bc Tidy up several unbeseeming casts from pointer to intptr_t. 
llvm-svn: 55779
 2008-09-04 17:05:41 +00:00
Owen Anderson
cd3ee9198d Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase. 
llvm-svn: 55777
 2008-09-04 16:48:33 +00:00
Owen Anderson
35485dbae3 Add a first attempt at implementing stores for X86 fast isel using target hooks. 
Dan or Evan, please review.

llvm-svn: 55764
 2008-09-04 07:08:58 +00:00
Evan Cheng
9c728a557d Load from GV stub should be locally CSE'd. 
llvm-svn: 55763
 2008-09-04 06:18:33 +00:00
Evan Cheng
53ce5fa5ce Remove code that pad number of bytes to pop for X86_FastCall CC. The code doesn't do the "aligning" for Cygwin, Mingw, and Windows. But aligning it on Darwin and Linux breaks gcc compatibility. That ruled out all the platforms we support! 
llvm-svn: 55756
 2008-09-04 01:04:15 +00:00
Dale Johannesen
9e4d101fab Add intrinsics for log, log2, log10, exp, exp2. 
No functional change (and no FE change to generate them).

llvm-svn: 55753
 2008-09-04 00:47:13 +00:00
Dan Gohman
18cc2a26df Create HandlePHINodesInSuccessorBlocksFast, a version of 
HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.

This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.

llvm-svn: 55746
 2008-09-03 23:12:08 +00:00
Evan Cheng
942d55dd92 Add X86 target hook to implement load (even from GlobalAddress). 
llvm-svn: 55693
 2008-09-03 06:44:39 +00:00
Ted Kremenek
b7236d215b Fix capitalization in #include of FastISel.h. This unbreaks the build on case-sensitive filesystems. 
llvm-svn: 55687
 2008-09-03 02:54:11 +00:00
Evan Cheng
4cef3f6ce1 Unbreak fast isel. 
llvm-svn: 55685
 2008-09-03 01:04:47 +00:00
Evan Cheng
43c7084625 Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class. 
llvm-svn: 55679
 2008-09-03 00:03:49 +00:00
Gabor Greif
7db742d8c2 fix a bunch of 80-col violations 
llvm-svn: 55588
 2008-08-31 15:37:04 +00:00
Evan Cheng
c3c439a624 For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these. 
llvm-svn: 55562
 2008-08-30 08:54:22 +00:00
Evan Cheng
4bc8c9652e Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). 
llvm-svn: 55558
 2008-08-30 02:03:58 +00:00
Evan Cheng
c1c53221c5 Swap fp comparison operands and change predicate to allow load folding (safely this time). 
llvm-svn: 55553
 2008-08-29 23:22:12 +00:00
Evan Cheng
a884330e08 Use static_cast instead of C style cast. 
llvm-svn: 55552
 2008-08-29 23:21:31 +00:00
Evan Cheng
17382f9ffb Backing out 55521. Not safe. 
llvm-svn: 55548
 2008-08-29 22:13:21 +00:00
Owen Anderson
3aa3841da2 Add initial support for fast isel of instructions that have inputs pinned to physical registers. 
llvm-svn: 55545
 2008-08-29 17:45:56 +00:00
Evan Cheng
cdd06ba3f4 Swap fp comparison operands and change predicate to allow load folding. 
llvm-svn: 55521
 2008-08-28 23:48:31 +00:00
Dan Gohman
c7b8401b77 Add a target callback for FastISel. 
llvm-svn: 55512
 2008-08-28 23:21:34 +00:00
Gabor Greif
5ec5f19852 remove tabs, fix > 80 cols 
llvm-svn: 55511
 2008-08-28 23:19:51 +00:00
Gabor Greif
86c795a8ca erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics 
llvm-svn: 55504
 2008-08-28 21:40:38 +00:00
Rafael Espindola
1cd4fc3111 Use resize instead of reserve. Reserve doesn't change size(). 
llvm-svn: 55486
 2008-08-28 18:32:53 +00:00
Evan Cheng
419506a149 FsFLD0S{S|D} and V_SETALLONES are as cheap as moves. 
llvm-svn: 55466
 2008-08-28 07:52:25 +00:00
Dale Johannesen
490c016734 Split the ATOMIC NodeType's to include the size, e.g. 
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.

llvm-svn: 55457
 2008-08-28 02:44:49 +00:00
Bill Wendling
0b5b31a0be Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the 
SSE2 registers as well as the MMX registers.

llvm-svn: 55436
 2008-08-27 21:32:04 +00:00
Dan Gohman
3976cccecd Reinstate the x86-64 portion of r55190. When doing extloads into 
64-bit registers from 16-bit and smaller memory locations, prefer
instructions that define the entire 64-bit register, to avoid
partial-register updates.

llvm-svn: 55422
 2008-08-27 17:33:15 +00:00
Gabor Greif
4b86114f92 disallow direct access to SDValue::ResNo, provide a getter instead 
llvm-svn: 55394
 2008-08-26 22:36:50 +00:00
Owen Anderson
fc7b8f3073 These assertions should be return false's instead, allowing the client to detect the failure. 
llvm-svn: 55377
 2008-08-26 18:50:40 +00:00
Owen Anderson
5fef19facf Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested 
was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.

llvm-svn: 55375
 2008-08-26 18:03:31 +00:00
Chris Lattner
c5c00890e5 If an xmm register is referenced explicitly in an inline asm, make sure to 
assign it to a version of the xmm register with the regclass that matches its
type.  This fixes PR2715, a bug handling some crazy xpcom case in mozilla.

llvm-svn: 55358
 2008-08-26 06:19:02 +00:00
Evan Cheng
65d29b2553 This is done. 
llvm-svn: 55348
 2008-08-26 01:13:44 +00:00
Evan Cheng
19738e3956 80 col. violations. 
llvm-svn: 55341
 2008-08-25 21:58:43 +00:00
Evan Cheng
569b489cf5 Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot. 
llvm-svn: 55338
 2008-08-25 21:27:18 +00:00
Bill Wendling
7f52506926 Nevermind. This broke the bootstrap (?!). 
llvm-svn: 55318
 2008-08-25 18:32:39 +00:00
Bill Wendling
f86b246fdb MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these 
instructions on having SSE2.

llvm-svn: 55317
 2008-08-25 18:20:52 +00:00
Evan Cheng
2b9f879a99 Fix asm printing of MOVSDto64mr and MOV64toSDrm. 
llvm-svn: 55300
 2008-08-25 04:11:42 +00:00
Bill Wendling
5728cf59fd Temporarily reverting r55292. It's causing a bootstraping failure: 
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc ... src/libiberty/make-temp-file.c -o make-temp-file.o
Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && "Wrong topological sorting"), function InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, line 508.
../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
make[4]: *** [hashtab.o] Error 1
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [multi-do] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libiberty] Error 2
make: *** [all] Error 2

llvm-svn: 55295
 2008-08-24 21:45:30 +00:00
Evan Cheng
a600778748 Move callseq_start above the call address load to allow load to be folded into the call node. 
llvm-svn: 55292
 2008-08-24 19:19:55 +00:00
Cedric Venet
6c99b53fda Use additionnal include directory instead of ../ in #include. 
Suggested by aKor.

llvm-svn: 55282
 2008-08-24 12:30:46 +00:00
Anton Korobeynikov
be3a5a5ce9 Provide a 64 bit variant of mmx.maskmovq intrinsic lowering. 
Is there way to avoid explicit target check?

llvm-svn: 55238
 2008-08-23 15:53:19 +00:00
Dan Gohman
a9d5f9b006 Move the point at which FastISel taps into the SelectionDAGISel 
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.

Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.

To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.

llvm-svn: 55219
 2008-08-23 02:25:05 +00:00
Bill Wendling
60e176391d Reverting r55190, r55191, and r55192. They broke the build with this error message: 
{standard input}:17:bad register name `%sil'
make[4]: *** [libgcc/./_addvsi3.o] Error 1
make[4]: *** Waiting for unfinished jobs....
{standard input}:23:bad register name `%dil'
{standard input}:28:bad register name `%dil'
make[4]: *** [libgcc/./_addvdi3.o] Error 1
{standard input}:18:bad register name `%sil'
make[4]: *** [libgcc/./_subvsi3.o] Error 1

llvm-svn: 55200
 2008-08-22 20:51:05 +00:00
Dan Gohman
897aa30d7c Anyext tweaks for x86. When extloading a value to i32 or i64, choose 
instructions that define the full 32 or 64-bit value. When anyexting
from i8 to i16 or i32, it's not necessary to zero out the high
portion of the register.

llvm-svn: 55190
 2008-08-22 19:19:31 +00:00
Dan Gohman
a398d11527 Factor out the predicate check code from DAGISelEmitter.cpp 
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.

llvm-svn: 55156
 2008-08-22 00:20:26 +00:00
Bill Wendling
f105f92904 If part of the mask is "undef", then ignore it as we don't care what goes into it. 
llvm-svn: 55147
 2008-08-21 22:36:36 +00:00
Bill Wendling
170bd0a562 Fix whitespace. No functionality change. 
llvm-svn: 55146
 2008-08-21 22:35:37 +00:00
Evan Cheng
ef2509b3ba Fix a number of byval / memcpy / memset related codegen issues. 
1. x86-64 byval alignment should be max of 8 and alignment of type. Previously the code was not doing what the commit message was saying.
2. Do not use byte repeat move and store operations. These are slow.

llvm-svn: 55139
 2008-08-21 21:00:15 +00:00
Mon P Wang
bf7b94fd29 Treat floating point ST1 the same as ST0 when lowering for a call result 
llvm-svn: 55135
 2008-08-21 19:54:16 +00:00
Anton Korobeynikov
5bbfc7e05f Allow inline asm nodes with empty bodies inside JIT. 
This unbreaks explicit reg vars inside JIT, which are
implemented in such hacky way :)

llvm-svn: 55128
 2008-08-21 17:33:01 +00:00
Dan Gohman
4b801d38a1 Simplify SelectRoot's interface, and factor out some common code 
from all targets.

llvm-svn: 55124
 2008-08-21 16:36:34 +00:00
Bill Wendling
2ba1a2b516 Clean up whitespace. 
llvm-svn: 55117
 2008-08-21 08:38:54 +00:00
Owen Anderson
2c1d54952b Use raw_ostream throughout the AsmPrinter. 
llvm-svn: 55092
 2008-08-21 00:14:44 +00:00
Dan Gohman
411cc551cb Move the handling of ANY_EXTEND, SIGN_EXTEND_INREG, and TRUNCATE 
out of X86ISelDAGToDAG.cpp C++ code and into tablegen code.
Among other things, using tablegen for these things makes them
friendlier to FastISel.

Tablegen can handle the case of i8 subregs on x86-32, but currently
the C++ code for that case uses MVT::Flag in a tricky way, and it
happens to schedule better in some cases. So for now, leave the
C++ code in place to handle the i8 case on x86-32.

llvm-svn: 55078
 2008-08-20 21:27:32 +00:00
Dan Gohman
ddebe95287 Simplify FastISel's constructor argument list, make the FastISel 
class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.

llvm-svn: 55076
 2008-08-20 21:05:57 +00:00
Dan Gohman
ebba07cccf Tablegen generated code already tests the opcode value, so it's not 
necessary to use dyn_cast in these predicates.

llvm-svn: 55055
 2008-08-20 15:24:22 +00:00
Dan Gohman
e409b06d46 Fix comment spacing. 
llvm-svn: 55047
 2008-08-20 13:46:21 +00:00
Dale Johannesen
69c9d47dce Add remaining 64-bit atomic patterns for x86-64. 
llvm-svn: 55029
 2008-08-20 00:48:50 +00:00
Bill Wendling
ab390189dc Revert r55018 and apply the correct "fix" for the 64-bit sub_and_fetch atomic. 
Just expand it like the other X-bit sub_and_fetches.

llvm-svn: 55023
 2008-08-20 00:28:16 +00:00
Bill Wendling
ab7c8c091e Add support for the __sync_sub_and_fetch atomics and friends for X86. The code 
was already present, but not hooked up to anything.

llvm-svn: 55018
 2008-08-19 23:09:18 +00:00
Dan Gohman
b1ba73eeed Instantiate FastISel for X86. 
llvm-svn: 55011
 2008-08-19 21:45:35 +00:00
Dan Gohman
36e732b8fc The X86 target will soon have an implementation of createFastISel. 
llvm-svn: 55010
 2008-08-19 21:32:53 +00:00
Dale Johannesen
15b76de064 Add support for 8 and 16 bit forms of __sync 
builtins on X86.

Change "lock" instructions to be on a separate line.
This is needed to work around a bug in the Darwin
assembler.

llvm-svn: 54999
 2008-08-19 18:47:28 +00:00
Chris Lattner
61e771be29 add a note 
llvm-svn: 54964
 2008-08-19 00:41:02 +00:00
Chris Lattner
843bb4018c remove empty file 
llvm-svn: 54950
 2008-08-18 21:27:19 +00:00
Evan Cheng
6534c78383 Fix a (u)comiss intrinsic lowering bug. It was using anyext which can return junk in higher bits. Patch by Nate Begeman. 
llvm-svn: 54903
 2008-08-17 19:22:34 +00:00
Cedric Venet
e1e9213f95 Make it compile on VC2005: 
- update VC projects.
- Add an overload to llvm::Stream for <<, since std::hex and std::dec have type std::ios_base& (*)(std::ios_base&) in VC++. (templating the function don't work, due to ambiguities)
- add ../ on several include in X86/AsmPrinter/

llvm-svn: 54898
 2008-08-17 18:24:26 +00:00
Anton Korobeynikov
c2606f65c7 Move X86 assembler printers into separate directory. This allows JIT-only users not to link it in (use 'x86codegen' llvm-config arg for this) 
llvm-svn: 54886
 2008-08-17 13:53:59 +00:00
Anton Korobeynikov
d475141eea Use correct name for TLS address resolution routine on x86-64 
llvm-svn: 54845
 2008-08-16 12:58:29 +00:00
Anton Korobeynikov
767865a3d1 Reduce heap trashing due to std::string construction / concatenation via caching of section flags string representations 
llvm-svn: 54842
 2008-08-16 12:57:07 +00:00
Dan Gohman
1a413c0387 Build the X86GenFastISel.inc file. 
llvm-svn: 54806
 2008-08-14 23:18:11 +00:00
Dan Gohman
7534da85c9 Also avoid pinsrw and pinsrb with a variable insertelement index. 
llvm-svn: 54803
 2008-08-14 22:53:18 +00:00
Owen Anderson
600a8ca0d5 Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. 
llvm-svn: 54802
 2008-08-14 22:49:33 +00:00
Dan Gohman
c530d2983d Don't try to use the insertps instruction for vector 
element inserts with non-constant indices. This fixes
CodeGen/X86/vector-variable-idx.ll on machines that
have SSE4.1.

llvm-svn: 54801
 2008-08-14 22:43:26 +00:00
Owen Anderson
af9e467544 Remove more uses of std::set. 
llvm-svn: 54787
 2008-08-14 21:01:00 +00:00
Dan Gohman
502d2aebff Oops, check in these files too, for the FastISel -> Fast rename. 
llvm-svn: 54750
 2008-08-13 19:55:00 +00:00
Dale Johannesen
686068490f When resolving a stub in x86-64 JIT, use a PC-relative branch 
rather than the absolute address if the target is within range.

llvm-svn: 54708
 2008-08-12 23:20:24 +00:00
Dale Johannesen
4dc25a234c Make x86-64 JIT changes Darwin-specific. 
llvm-svn: 54700
 2008-08-12 21:02:08 +00:00
Dale Johannesen
74bf5907fa In the absence of a linker to build the GOT, use the 32-bit 
non_lazy_ptr mechanism on x86-64 Darwin JIT.  Fixes a bunch
of last night's failures.

llvm-svn: 54692
 2008-08-12 18:23:48 +00:00
Dale Johannesen
718fcee02d Some fixes for x86-64 JIT. Make it use small code 
model, except for external calls; this makes
addressing modes PC-relative.  Incomplete.

The assertion at the top of Emitter::runOnMachineFunction
was obviously bogus (always true) so I removed it.
If someone knows what the correct test should be to cover
all the various targets, please fix.

llvm-svn: 54656
 2008-08-11 23:46:25 +00:00
Dan Gohman
ac992cdc1c Add an EXTRACTPSmr pattern to match the pattern that 
X86ISelLowering creates.

llvm-svn: 54544
 2008-08-08 18:30:21 +00:00
Anton Korobeynikov
14142919d0 Generalize 
llvm-svn: 54542
 2008-08-08 18:25:52 +00:00
Anton Korobeynikov
8d77445753 Handle visibility printing with all generality. Remove bunch of duplicate code. 
llvm-svn: 54540
 2008-08-08 18:25:07 +00:00
Evan Cheng
290a9fa171 Fix indentation. 
llvm-svn: 54518
 2008-08-08 06:43:59 +00:00
Anton Korobeynikov
212df90ce5 Remove dead forward decl 
llvm-svn: 54461
 2008-08-07 09:55:25 +00:00
Anton Korobeynikov
0c8d06f030 Switch ARM to new section handling stuff 
llvm-svn: 54458
 2008-08-07 09:54:23 +00:00
Dan Gohman
74fa421281 Re-enable elimination of unnecessary SUBREG_TO_REG instructions in 
LowerSubregs, and fix an x86-64 isel bug that this exposed.

SUBREG_TO_REG for x86-64 implicit zero extension is only safe for
isel to generate when the source is known to always have zeros in
the high 32 bits. The EXTRACT_SUBREG instruction does not clear
the high 32 bits.

llvm-svn: 54444
 2008-08-07 02:54:50 +00:00
Dan Gohman
cc784f1662 Re-introduce the 8-bit subreg zext-inreg patterns for x86-32, 
this time using MOV32to32_ and MOV16to16_. Thanks to Evan for
suggesting this.

llvm-svn: 54418
 2008-08-06 18:27:21 +00:00
Dan Gohman
99d70043f9 xchg does not modify FLAGS. 
llvm-svn: 54411
 2008-08-06 15:52:50 +00:00
Evan Cheng
f4d1119fbd Fix PR2620: Fix X86cmppd selection code so it expects operands to be v2f64. 
llvm-svn: 54376
 2008-08-05 22:19:15 +00:00
Dan Gohman
5d0df78ae0 Add an assert to catch invalid VECTOR_SHUFFLE mask indices. 
llvm-svn: 54329
 2008-08-04 23:09:15 +00:00
Andrew Lenharth
377c046675 Add atomic sub for other sizes 
llvm-svn: 54314
 2008-08-03 20:17:34 +00:00
Dan Gohman
efb5d2ce6e Reapply r54147 with a constraint to only use the 8-bit 
subreg form on x86-64, to avoid the problem with x86-32
having GPRs that don't have 8-bit subregs.

Also, change several 16-bit instructions to use 
equivalent 32-bit instructions. These have a smaller
encoding and avoid partial-register updates.

llvm-svn: 54223
 2008-07-30 18:09:17 +00:00
Dan Gohman
ebe629a4b2 Revert 54147. 
llvm-svn: 54148
 2008-07-29 01:02:18 +00:00
Dan Gohman
1816900fd1 Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation, 
which is represented in codegen as an 'and' operation. This matches them
with movz instructions, instead of leaving them to be matched by and
instructions with an immediate field.

llvm-svn: 54147
 2008-07-28 22:18:25 +00:00
Dan Gohman
9742f7772d Rename SDOperand to SDValue. 
llvm-svn: 54128
 2008-07-27 21:46:04 +00:00
Dan Gohman
47c5cdbc34 Tidy SDNode::use_iterator, and complete the transition to have it 
parallel its analogue, Value::value_use_iterator. The operator* method
now returns the user, rather than the use.

llvm-svn: 54127
 2008-07-27 20:43:25 +00:00
Nate Begeman
5523d40e4b Disable mov{L, LP, HP, HLP, *DUP} shuffles for mmx 
mmx needs its own fancy shuffle logic based on unpack; for now we get correct but awful code.

Also commit Mon Ping's VSETCC patch

llvm-svn: 54039
 2008-07-25 19:05:58 +00:00
Nate Begeman
730880eec2 Fit in 80 cols 
llvm-svn: 54029
 2008-07-25 17:34:41 +00:00
Nate Begeman
73efed7a4c Remove dead PatLeaf; there are a number of issues around MMX movl that need to be fixed. 
llvm-svn: 54026
 2008-07-25 17:25:04 +00:00
Evan Cheng
20c9cdbe69 Fix PR2485: do all 4-element SSE shuffles in max. of 2 shuffle instructions. 
Based on patch by Nicolas Capens.

llvm-svn: 53939
 2008-07-23 00:22:17 +00:00
Evan Cheng
ff0bd19937 Factor out SSE 4 wide shuffle lowering code into its own function. No functionality changes. 
llvm-svn: 53933
 2008-07-22 21:13:36 +00:00
Evan Cheng
901d469e05 Fix PR2574: implement v2f32 scalar_to_vector. 
llvm-svn: 53927
 2008-07-22 18:39:19 +00:00
Anton Korobeynikov
f13fbd6879 Fix encoding of atomic compare and swap for i64 
llvm-svn: 53911
 2008-07-22 16:22:48 +00:00
Evan Cheng
a2bb31372d Eliminate a compilation warning. 
llvm-svn: 53873
 2008-07-21 20:02:45 +00:00
Dan Gohman
b91bef08a7 Add titles to the various SelectionDAG viewGraph calls 
that include useful information like the name of the
block being viewed and the current phase of compilation.

llvm-svn: 53872
 2008-07-21 20:00:07 +00:00
Duncan Sands
6e31474e71 Add VerifyNode, a place to put sanity checks on 
generic SDNode's (nodes with their own constructors
should do sanity checking in the constructor).  Add
sanity checks for BUILD_VECTOR and fix all the places
that were producing bogus BUILD_VECTORs, as found by
"make check".  My favorite is the BUILD_VECTOR with
only two operands that was being used to build a
vector with four elements!

llvm-svn: 53850
 2008-07-21 10:20:31 +00:00
Evan Cheng
ffd51ccf6b Use movaps instead of movups to spill 16-byte vector values when default alignment is >= 16. This fixes some massive performance regressions. 
llvm-svn: 53844
 2008-07-21 06:34:17 +00:00
Bill Wendling
98b6e63176 Fix for first part of PR2562. Generate the "pinsrw" instruction for inserts 
into v4i16 vectors.

llvm-svn: 53807
 2008-07-20 02:32:23 +00:00
Anton Korobeynikov
449fb584e4 Fix a FIXME :) 
llvm-svn: 53789
 2008-07-19 13:15:46 +00:00
Anton Korobeynikov
5c0eb7e991 Use generic ELFTargetAsmInfo and DarwinTargetAsmInfo for X86 code 
llvm-svn: 53788
 2008-07-19 13:15:21 +00:00
Anton Korobeynikov
6e00357dd6 Use aligned stack spills, where possible. This fixes PR2549. 
llvm-svn: 53784
 2008-07-19 06:30:51 +00:00
Dan Gohman
8981962672 Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk 
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.

Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.

This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.

These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.

llvm-svn: 53728
 2008-07-17 19:10:17 +00:00
Nate Begeman
64f8f7f6bb Remove unnecessary readme entry 
llvm-svn: 53722
 2008-07-17 17:21:14 +00:00
Nate Begeman
61f6c21028 Fix a typo in last commit 
llvm-svn: 53720
 2008-07-17 17:04:58 +00:00
Nate Begeman
af01bfff99 SSE codegen for vsetcc nodes 
llvm-svn: 53719
 2008-07-17 16:51:19 +00:00
Mon P Wang
57cd9d6e5a When lowering certain atomics, we need to copy the memoperand from the old 
atomic operation to the new one.

llvm-svn: 53714
 2008-07-17 04:54:06 +00:00
Devang Patel
a6c5ff690a Mark function used by asm block as used, otherwise optimizer may not see the use and may delete the function. 
llvm-svn: 53692
 2008-07-16 17:54:34 +00:00
Dan Gohman
4c8c8e3aad Fix the result type of X86's truncate to i8. 
llvm-svn: 53688
 2008-07-16 16:20:48 +00:00
Evan Cheng
face16f9d8 x86-64 PIC JIT fixes: do not generate the extra load for external GV's. 
llvm-svn: 53661
 2008-07-16 01:34:02 +00:00
Evan Cheng
cabfd3f78c X86-64 PIC jump table values are different from x86-32 cases, they are dest - table base. 
llvm-svn: 53660
 2008-07-16 01:33:08 +00:00
Dan Gohman
bf47a27643 Add a utility function to MachineInstr for testing whether an instruction 
has exactly one MachineMemOperand, and change some X86 lowering code to
make use of it.

llvm-svn: 53498
 2008-07-12 00:10:52 +00:00
Dan Gohman
4c18394001 Include a frame index in the "fixed stack" pseudo source value 
instead of using the frame index for the SVOffset, which was
inconsistent.

llvm-svn: 53486
 2008-07-11 22:44:52 +00:00
Bill Wendling
9f17caa9a9 The frame address on an x86-64 box needs to be offset by -8, not -4. 
llvm-svn: 53450
 2008-07-11 07:18:52 +00:00