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21830 Commits

Author SHA1 Message Date
Manman Ren
644e8f4a5b Debug Info: drop debug info via upgrading path if version number does not match.
Add a helper function getDebugInfoVersionFromModule to return the debug info
version number for a module.

"Verifier/module-flags-1.ll" checks for verification errors.
It will seg fault when calling getDebugInfoVersionFromModule because of the
incorrect format for module flags in the testing case. We make
getModuleFlagsMetadata more robust by checking for error conditions.

PR17982

llvm-svn: 196158
2013-12-02 21:29:56 +00:00
Manman Ren
3b572dc7ed Update Ocaml/vmcore.ml to emit a "Debug Info Version" module flag.
llvm-svn: 196156
2013-12-02 21:25:56 +00:00
Chad Rosier
bcca7559f8 [AArch64] Implemented vcopy_lane patterns using scalar DUP instruction.
Patch by Ana Pazos!

llvm-svn: 196151
2013-12-02 21:05:16 +00:00
David Blaikie
74530dc54e DebugInfo: Type Units: Propagate the correct DW_AT_language into type units.
llvm-svn: 196130
2013-12-02 18:44:29 +00:00
Kay Tiong Khoo
5257afa264 Conservative fix for PR17827 - don't optimize a shift + and + compare sequence where the shift is logical unless the comparison is unsigned
llvm-svn: 196129
2013-12-02 18:43:59 +00:00
Vincent Lejeune
26780e84f1 R600: Workaround for cayman loop bug
llvm-svn: 196121
2013-12-02 17:29:37 +00:00
Diego Novillo
a4c6fce65c Add tests for profile sample file parsing.
The profile file parser needed some tests for its parsing actions.
This adds tests for each of the error messages emitted by the parser.

llvm-svn: 196106
2013-12-02 15:12:50 +00:00
Rafael Espindola
5b33cec985 Output .eh_frames on COFF too now that the integrated as is used on mingw.
llvm-svn: 196104
2013-12-02 14:59:34 +00:00
Tim Northover
c144b1204e ARM: decide whether to use movw/movt based on "minsize" attribute.
llvm-svn: 196102
2013-12-02 14:46:26 +00:00
Robert Lytton
aec919de4b XCore target: Make handling of large frames not dependent upon an FP.
eliminateFrameIndex() has been reworked to handle both small & large frames
with either a FP or SP.
An additional Slot is required for Scavenging spills when not using FP for large frames.
Reworked the handling of Register Scavenging.

Whether we are using an FP or not, whether it is a large frame or not,
and whether we are using a large code model or not are now independent.

llvm-svn: 196091
2013-12-02 11:05:28 +00:00
Tim Northover
46df9f449d ARM: add pseudo-instructions for lit-pool global materialisation
These are used by MachO only at the moment, and (much like the existing
MOVW/MOVT set) work around the fact that the labels used in the actual
instructions often contain PC-dependent components, which means that repeatedly
materialising the same global can't be CSEed.

With small modifications, it could be adapted to how ELF finds the address of
_GLOBAL_OFFSET_TABLE_, which would give similar benefits in PIC mode there.

llvm-svn: 196090
2013-12-02 10:35:41 +00:00
Robert Lytton
7a58a4e90d XCore target: fix large code model 'select' indirect address handling.
llvm-svn: 196088
2013-12-02 10:18:37 +00:00
Robert Lytton
3eb24d0e61 XCore target: Add large code model
When using large code model:
Global objects larger than 'CodeModelLargeSize' bytes are placed in sections named with a trailing ".large"
The folded global address of such objects are lowered into the const pool.

During inspection it was noted that LowerConstantPool() was using a default offset of zero.
A fix was made, but due to only offsets of zero being generated, testing only verifies the change is not detrimental.

Correct the flags emitted for explicitly specified sections.

We assume the size of the object queried by getSectionForConstant() is never greater than CodeModelLargeSize.
To handle greater than CodeModelLargeSize, changes to AsmPrinter would be required.

llvm-svn: 196087
2013-12-02 10:18:31 +00:00
Robert Lytton
c3b700cb09 XCore target: extend tests in preparation
llvm-svn: 196086
2013-12-02 10:18:24 +00:00
Robert Lytton
75d72dfcd2 XCore target: Fix eliminateFrameIndex() to handle large frames
Large frame offsets are loaded from the ConstantPool.
Where possible, offsets are encoded using the smaller MKMSK instruction.
Large frame offsets can only be used when there is a frame-pointer.

llvm-svn: 196085
2013-12-02 10:18:19 +00:00
Robert Lytton
9c8a9af745 XCore target: Enable frames larger than 65535 to be lowered
llvm-svn: 196084
2013-12-02 10:18:14 +00:00
Kostya Serebryany
e71e08d007 [tsan] fix instrumentation of vector vptr updates (https://code.google.com/p/thread-sanitizer/issues/detail?id=43)
llvm-svn: 196079
2013-12-02 08:07:15 +00:00
Alp Toker
fcc4ea594d Rename test with misspelt filename
llvm-svn: 196064
2013-12-02 04:31:36 +00:00
Rafael Espindola
cf111ab2af Also test the created stubs on 32 bits.
llvm-svn: 196052
2013-12-01 21:24:30 +00:00
Andrew Trick
26c262f3a7 Add -mcpu to stackmap.ll
llvm-svn: 196051
2013-12-01 18:17:05 +00:00
Tim Northover
bcd72d7348 ARM: fix bug in -Oz stack adjustment folding
Previously, we clobbered callee-saved registers when folding an "add
sp, #N" into a "pop {rD, ...}" instruction. This change checks whether
a register we're going to add to the "pop" could actually be live
outside the function before doing so and should fix the issue.

This should fix PR18081.

llvm-svn: 196046
2013-12-01 14:16:24 +00:00
Michael Kuperstein
356b61c610 Ensure bitcode encoding of linkage types stays stable. Patch by Boaz Ouriel
llvm-svn: 196042
2013-12-01 10:16:35 +00:00
Hal Finkel
14673817db Convert a PPC test from grep to FileCheck
Convert this test to FileCheck, and improve it to check for the instructions it
is trying to exclude instead of checking for register use (especially because
grepping for r1 can be thrown off, for example, by a use of r12).

llvm-svn: 195979
2013-11-30 20:04:33 +00:00
Hal Finkel
ded988ca4c Desensitize a couple of PPC regression tests
Use CHECK-DAG to make these regression tests more resilient against changes in
instruction scheduling.

llvm-svn: 195978
2013-11-30 19:52:28 +00:00
Hal Finkel
1cdcead814 Update the cpu specified on some PPC regression tests
Some of these tests did not specify a cpu but were also sensitive to
instruction scheduling and/or register assignment choices. A few others
similarly-sensitive tests specified a cpu (often the POWER7), and while the P7
currently uses the default model for PPC64, this will soon change. For those
tests which should not really be cpu-dependent anyway, the cpu is set to the
generic 'ppc64'.

llvm-svn: 195977
2013-11-30 19:39:27 +00:00
Zoran Jovanovic
335dc8689e Test case for issue with microMIPS long branch.
llvm-svn: 195976
2013-11-30 19:13:15 +00:00
Daniel Sanders
65ab9582ba [mips][msa] MSA loads and stores have a 10-bit offset. Account for this when lowering FrameIndex.
This prevents the compiler from emitting invalid ld.[bhwd]'s and st.[bhwd]'s
when the stack frame is between 512 and 32,768 bytes in size.

llvm-svn: 195973
2013-11-30 13:47:57 +00:00
Juergen Ributzka
7150312963 Force CPU type to unbreak unit tests on Haswell machines.
llvm-svn: 195971
2013-11-30 03:07:16 +00:00
Reed Kotler
95269c69db Part 1 of 3 patches that completes very long conditional branches
in constant islands for Mips16. We introdcuce JalB16 as a synomnym
for Jal16. It makes it easier to read and is also necessary because
Jal16 is a call instruction but JalB16 is being used as a branch.
Various parts of LLVM will not work properly even in this late stage of
the backend if we use what was declared as a call instruction to function
as a branch. For one, basic block labels may not get emitted in some
situations. 

llvm-svn: 195968
2013-11-29 22:32:56 +00:00
Zoran Jovanovic
b8cffe14c6 Revert revision 195965.
llvm-svn: 195967
2013-11-29 22:10:02 +00:00
Petar Jovanovic
f12c338160 mips: XFAIL llvm-cov test
XFAIL llvm-cov.test for MIPS until big-endian issues are fixed for llvm-cov.
The test does pass on MIPS little-endian.

llvm-svn: 195966
2013-11-29 21:59:09 +00:00
Zoran Jovanovic
797919cb22 Fixed issue with microMIPS long branch.
llvm-svn: 195965
2013-11-29 21:41:24 +00:00
Hao Liu
b9fa1067c7 AArch64: The pattern match should check the range of the immediate value.
Or we can generate some illegal instructions.
E.g. shrn2 v0.4s, v1.2d, #35. The legal range should be in [1, 16].

llvm-svn: 195941
2013-11-29 02:11:22 +00:00
Jiangning Liu
844201423a Add missing test case for bsl_f64 support of AArch64 NEON.
llvm-svn: 195939
2013-11-29 01:38:08 +00:00
Kevin Qin
b95721d200 [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.
llvm-svn: 195936
2013-11-29 01:29:16 +00:00
Stephen Canon
d8aaca93a6 Rein in overzealous InstCombine of fptrunc(OP(fpextend, fpextend)).
llvm-svn: 195934
2013-11-28 21:38:05 +00:00
Hao Liu
2f617213ef AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
llvm-svn: 195903
2013-11-28 01:07:45 +00:00
Reed Kotler
deb5d6d05e Check in conditional branches for constant islands. Still need to finish
conditional branches for very large targets. That will be the next small
patch. Everything now should in principle work as good (functionality
wise) as without constant islands so we decided at Mips/Imagination to
make constant islands the default for Mips16 now so that it will get
excercised a lot and this port is still experimentatl though hopefully soon
we will change the status. Some more cleanup and code review is in order
but things are converging fast.

llvm-svn: 195902
2013-11-28 00:56:37 +00:00
David Blaikie
91268863a6 DebugInfo: Do not include variables only referenced by templates in aranges.
ARanges included even extern variables referenced by pointer non-type
template parameters even though that variable isn't part of this
compilation unit.

llvm-svn: 195895
2013-11-27 23:53:52 +00:00
Akira Hatanaka
ff17fbeebc [mips] Implement the following optimizations using dominance information to
make PIC calls a little more efficient:

1. Remove instructions setting up $gp if it is known that a function has been
   called at least once.
2. Save the address of a called function in a register instead of loading
   it from the GOT at every call site.

llvm-svn: 195892
2013-11-27 23:38:42 +00:00
Tom Stellard
95624c101d R600: Expand vector FABS
NOTE: This is a candidate for the 3.4 branch.
llvm-svn: 195881
2013-11-27 21:23:39 +00:00
Tom Stellard
eac3acc854 R600/SI: Implement spilling of SGPRs v5
SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions.

v2:
  - Fix encoding of Lane Mask
  - Use correct register flags, so we don't overwrite the low dword
    when restoring multi-dword registers.

v3:
  - Register spilling seems to hang the GPU, so replace all shaders
    that need spilling with a dummy shader.

v4:
  - Fix *LANE definitions
  - Change destination reg class for 32-bit SMRD instructions

v5:
  - Remove small optimization that was crashing Serious Sam 3.

https://bugs.freedesktop.org/show_bug.cgi?id=68224
https://bugs.freedesktop.org/show_bug.cgi?id=71285

NOTE: This is a candidate for the 3.4 branch.
llvm-svn: 195880
2013-11-27 21:23:35 +00:00
Tom Stellard
d386cdf4d0 R600/SI: Use SGPR_32 register class for 32-bit SMRD outputs
Writing to the M0 register from an SMRD instruction hangs the GPU, so
we need to use the SGPR_32 register class, which does not include M0.

NOTE: This is a candidate for the 3.4 branch.
llvm-svn: 195879
2013-11-27 21:23:29 +00:00
Tom Stellard
0a14ce13e1 R600: Add support for ISD::FROUND
NOTE: This is a candidate for the 3.4 branch.
llvm-svn: 195878
2013-11-27 21:23:20 +00:00
Rafael Espindola
c377a725ca Use FileCheck and expand the test a bit.
In particular, check the name of the symbol we are putting in the constant pool.

llvm-svn: 195865
2013-11-27 19:22:14 +00:00
Rafael Espindola
c099bf8035 Use the same tls section name as msvc.
We currently error in clang with:
"error: thread-local storage is unsupported for the current target", but we
can start to get the llvm level ready.

When compiling

template<typename T>
struct foo {
  static __declspec(thread) int bar;
};
template<typename T>
__declspec(therad) int foo<T>::bar;
template struct foo<int>;

msvc produces

SECTION HEADER #3
   .tls$ name
       0 physical address
       0 virtual address
       4 size of raw data
     12F file pointer to raw data (0000012F to 00000132)
       0 file pointer to relocation table
       0 file pointer to line numbers
       0 number of relocations
       0 number of line numbers
C0301040 flags
         Initialized Data
         COMDAT; sym= "public: static int foo<int>::bar" (?bar@?$foo@H@@2HA)
         4 byte align
         Read Write

gcc produces a ".data$__emutls_v.<symbol>" for the testcase with
__declspec(thread) replaced with thread_local.

llvm-svn: 195849
2013-11-27 15:52:11 +00:00
Jiangning Liu
d9270b7a51 Fix the AArch64 NEON bug exposed by checking constant integer argument range of ACLE intrinsics.
llvm-svn: 195843
2013-11-27 14:02:25 +00:00
Rafael Espindola
22b6ec4d69 Cleanup and test X86AsmPrinter::printPCRelImm.
It is only used for asm printing.

On X86 we put basic block addresses on register before passing them to inline
asm, so the MO_MachineBasicBlock case was dead.

MO_ExternalSymbol was dead since any symbol being passed to inline asm
is represented as MO_GlobalAddress.

The MO_GlobalAddress and MO_Register cases were not tested.

llvm-svn: 195824
2013-11-27 06:53:13 +00:00
Chad Rosier
ca062e81db [AArch64] Add support for NEON scalar floating-point absolute difference.
llvm-svn: 195803
2013-11-27 01:45:58 +00:00
Rafael Espindola
3ceb67b21b Use simple section names for COMDAT sections on COFF.
With this patch we use simple names for COMDAT sections (like .text or .bss).
This matches the MSVC behavior.

When merging it is the COMDAT symbol that is used to decide if two sections
should be merged, so there is no point in building a fancy name.

This survived a bootstrap on mingw32.

llvm-svn: 195798
2013-11-27 01:18:37 +00:00