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65e7766262
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372 Commits

Author SHA1 Message Date
Evan Cheng
65e7766262 Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. 
llvm-svn: 134030
 2011-06-28 21:14:33 +00:00
Evan Cheng
b83b307ae8 Hide more details in tablegen generated MCRegisterInfo ctor function. 
llvm-svn: 134027
 2011-06-28 20:44:22 +00:00
Evan Cheng
a115f77785 Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc 
llvm-svn: 134024
 2011-06-28 20:07:07 +00:00
Evan Cheng
4a169be530 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and 
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
 2011-06-28 19:10:37 +00:00
Evan Cheng
6fea701360 Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc 
into XXXGenRegisterInfo.inc.

llvm-svn: 133922
 2011-06-27 18:32:37 +00:00
Evan Cheng
e0801b07e0 Starting to refactor Target to separate out code that's needed to fully describe 
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782
 2011-06-24 01:44:41 +00:00
Jakob Stoklund Olesen
626abc2bc3 Allocate SystemZ callee-saved registers backwards: R13-R6 
The reserved R14-R15 are always saved in the prolog, and using CSRs
starting from R13 allows them to be saved in one instruction.

Thanks to Anton for explaining this.

llvm-svn: 133233
 2011-06-17 03:47:30 +00:00
Jakob Stoklund Olesen
d89900e14c Use set operations instead of plain lists to enumerate register classes. 
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.

I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.

llvm-svn: 133105
 2011-06-15 23:28:14 +00:00
Jakob Stoklund Olesen
7b0de9a9e0 Remove custom allocation orders in SystemZ. 
Note that this actually changes code generation, and someone who
understands this target better should check the changes.

- R12Q is now allocatable. I think it was omitted from the allocation
  order by mistake since it isn't reserved. It as apparently used as a
  GOT pointer sometimes, and it should probably be reserved if that is
  the case.

- The GR64 registers are allocated in a different order now. The
  register allocator will automatically put the CSRs last. There were
  other changes to the order that may have been significant.

The test fix is because r0 and r1 swapped places in the allocation order.

llvm-svn: 133067
 2011-06-15 18:02:56 +00:00
Eric Christopher
1ae9ec6124 Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965

llvm-svn: 132763
 2011-06-08 23:55:35 +00:00
Rafael Espindola
33f7d7f9fa Use the dwarf->llvm mapping to print register names in the cfi 
directives.

Fixes PR9826.

llvm-svn: 132317
 2011-05-30 20:20:15 +00:00
Rafael Espindola
33338e912b Remove the DwarfNumbers from the subregisters. They should use DW_OP_bit_piece 
and for now the generic dwarf emission will automatically use the superregister
numbers.

llvm-svn: 132312
 2011-05-30 15:56:04 +00:00
Eli Friedman
12e590e760 Make the logic for determining function alignment more explicit. No functionality change. 
llvm-svn: 131012
 2011-05-06 20:34:06 +00:00
Jakob Stoklund Olesen
6eef723c97 Implement SystemZRegisterInfo::getMatchingSuperRegClass to enable cross-class joins. 
llvm-svn: 130857
 2011-05-04 19:02:04 +00:00
Chris Lattner
0304b82f80 Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!

llvm-svn: 129558
 2011-04-15 05:18:47 +00:00
Owen Anderson
bd26993873 Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. 
llvm-svn: 126518
 2011-02-25 21:41:48 +00:00
Oscar Fuentes
59c8ae34f7 Use explicit add_subdirectory's for LLVM target sublibraries instead 
of testing for its presence at cmake time.

This way the build automatically regenerates the makefiles when a svn
update brings in a new sublibrary.

llvm-svn: 126068
 2011-02-20 02:55:27 +00:00
Anton Korobeynikov
323825cee4 Fix imm printing for logical instructions. 
Patch by Brian G. Lucas!

llvm-svn: 124679
 2011-02-01 20:22:53 +00:00
Rafael Espindola
59c1246cee Remove duplicated code. 
llvm-svn: 124054
 2011-01-23 04:28:49 +00:00
Jakob Stoklund Olesen
0f2b9d9dc4 Teach frame lowering to ignore debug values after the terminators. 
llvm-svn: 123399
 2011-01-13 21:28:52 +00:00
Anton Korobeynikov
abd9a868df Update CMake stuff 
llvm-svn: 123171
 2011-01-10 12:39:23 +00:00
Anton Korobeynikov
cf5967630b Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 
llvm-svn: 123170
 2011-01-10 12:39:04 +00:00
Chris Lattner
01e8c46349 Flag -> Glue, the ongoing saga 
llvm-svn: 122513
 2010-12-23 18:28:41 +00:00
Chris Lattner
65c5243bd6 rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for 
something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310
 2010-12-21 02:38:05 +00:00
Anton Korobeynikov
598465c605 Move more PEI-related hooks to TFI 
llvm-svn: 120229
 2010-11-27 23:05:25 +00:00
Anton Korobeynikov
c87f68e32e Move callee-saved regs spills / reloads to TFI 
llvm-svn: 120228
 2010-11-27 23:05:03 +00:00
Wesley Peck
d589353ad0 Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. 
llvm-svn: 119990
 2010-11-23 03:31:01 +00:00
Anton Korobeynikov
ff8c52bd51 Move some more hooks to TargetFrameInfo 
llvm-svn: 119904
 2010-11-20 15:59:32 +00:00
Anton Korobeynikov
269e7d3be1 Move hasFP() and few related hooks to TargetFrameInfo. 
llvm-svn: 119740
 2010-11-18 21:19:35 +00:00
Anton Korobeynikov
794259aec0 Attempt to unbreak cmake-based builds 
llvm-svn: 119098
 2010-11-15 00:48:12 +00:00
Anton Korobeynikov
76c52dcf44 First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place 
llvm-svn: 119097
 2010-11-15 00:06:54 +00:00
Chris Lattner
cec3b226a4 move all the target's asmprinters into the main target. The piece 
that should be split out is the InstPrinter (if a target is mc'ized).
This change makes all the targets be consistent.

llvm-svn: 119056
 2010-11-14 18:43:56 +00:00
Rafael Espindola
5766346831 Remove some explicit arguments to getELFSection. This is 
a leftover from the removal of isExplicit.

llvm-svn: 118774
 2010-11-11 03:40:25 +00:00
Oscar Fuentes
eb27a44982 Removed a bunch of unnecessary target_link_libraries. 
llvm-svn: 114999
 2010-09-28 22:39:14 +00:00
Chris Lattner
55043ef46a fix a long standing wart: all the ComplexPattern's were being 
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.

llvm-svn: 114471
 2010-09-21 20:31:19 +00:00
Chris Lattner
8cdc5e75f7 update a bunch of code to use the MachinePointerInfo version of getStore. 
llvm-svn: 114461
 2010-09-21 18:41:36 +00:00
Chris Lattner
4320dda4fb convert the targets off the non-MachinePointerInfo of getLoad. 
llvm-svn: 114410
 2010-09-21 06:44:06 +00:00
Chris Lattner
2edbad8a3d convert targets to the new MF.getMachineMemOperand interface. 
llvm-svn: 114391
 2010-09-21 04:39:43 +00:00
Chris Lattner
8df3ffd7ac zap dead code. 
llvm-svn: 113073
 2010-09-04 18:12:00 +00:00
Jim Grosbach
2b81a07dc7 Simplify eliminateFrameIndex() interface back down now that PEI doesn't need 
to try to re-use scavenged frame index reference registers. rdar://8277890

llvm-svn: 112241
 2010-08-26 23:32:16 +00:00
Eric Christopher
ff47f8d94f Constify some arguments. 
llvm-svn: 108812
 2010-07-20 06:52:21 +00:00
Jakob Stoklund Olesen
44949b2e1b Remove the isMoveInstr() hook. 
llvm-svn: 108567
 2010-07-16 22:35:46 +00:00
Benjamin Kramer
da3e6cdb26 Don't pass StringRef by reference. 
llvm-svn: 108366
 2010-07-14 22:38:02 +00:00
Jakob Stoklund Olesen
c48892383f Remove redundant branch. Thanks, Anton! 
llvm-svn: 108097
 2010-07-11 17:17:35 +00:00
Jakob Stoklund Olesen
ecdef6c130 Replace copyRegToReg with copyPhysReg for SystemZ. 
llvm-svn: 108092
 2010-07-11 16:40:46 +00:00
Dan Gohman
c768525273 Split the SDValue out of OutputArg so that SelectionDAG-independent 
code can do calling-convention queries. This obviates OutputArgReg.

llvm-svn: 107786
 2010-07-07 15:54:55 +00:00
Devang Patel
7ab104353b Propagate debug loc. 
llvm-svn: 107710
 2010-07-06 22:08:15 +00:00
Dan Gohman
808f334f79 Reapply r107655 with fixes; insert the pseudo instruction into 
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.

llvm-svn: 107691
 2010-07-06 20:24:04 +00:00
Dan Gohman
4d264f7e51 Revert r107655. 
llvm-svn: 107668
 2010-07-06 15:49:48 +00:00
Dan Gohman
6a73079aba Fix a bunch of custom-inserter functions to handle the case where 
the pseudo instruction is not at the end of the block.

llvm-svn: 107655
 2010-07-06 15:18:19 +00:00