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17036 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
6aeb2e320f Fix the encoding and parsing of clrex instruction 
llvm-svn: 123936
 2011-01-20 19:18:32 +00:00
Bruno Cardoso Lopes
c0f87c11d6 Change instruction names for consistency 
llvm-svn: 123930
 2011-01-20 18:36:07 +00:00
Bruno Cardoso Lopes
5f06c0aa3b Add cdp/cdp2 instructions for thumb/thumb2 
llvm-svn: 123929
 2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes
3584c02d83 - Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present 
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.

llvm-svn: 123927
 2011-01-20 18:06:58 +00:00
Bruno Cardoso Lopes
75712e8a7a Add mcr*2 and mr*c2 support to thumb2 targets 
llvm-svn: 123919
 2011-01-20 16:58:48 +00:00
Bruno Cardoso Lopes
f377d1721e Add mcr* and mr*c support to thumb targets 
llvm-svn: 123917
 2011-01-20 16:35:57 +00:00
Kalle Raiskila
070fb5e54d Allow sign-extending of i8 and i16 to i128 on SPU. 
llvm-svn: 123912
 2011-01-20 15:49:06 +00:00
Bruno Cardoso Lopes
0312bb222e Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. 
llvm-svn: 123910
 2011-01-20 13:17:59 +00:00
Evan Cheng
d9fdc9771e Correct itinerary entry for t2MOV_pic_ga_add_pc. 
llvm-svn: 123907
 2011-01-20 08:43:03 +00:00
Evan Cheng
6dc21c7358 Sorry, several patches in one. 
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.

Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.

ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
   which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
   a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
   to re-materialize the instruction, allow machine LICM to hoist the set of
   instructions out of the loop and make it possible to CSE them. It's a bit
   hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.

With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.

llvm-svn: 123905
 2011-01-20 08:34:58 +00:00
Venkatraman Govindaraju
5280b2876f Sparc backend: Implements a delay slot filler that attempt to fill delay slots 
with useful instructions.

llvm-svn: 123884
 2011-01-20 05:08:26 +00:00
Bruno Cardoso Lopes
0f7a30b1cb Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc 
llvm-svn: 123837
 2011-01-19 16:56:52 +00:00
Daniel Dunbar
dd1dd698f0 ARM/ISel: Factor out isScaledConstantInRange() helper. 
llvm-svn: 123823
 2011-01-19 15:12:16 +00:00
Andrew Trick
305613b87a For ARM subtargets with useNEONForSinglePrecisionFP, double count uses 
of the floating point types less than 64-bits. It's somewhat of a temporary
hack but forces more accurate modeling of register pressure and results
in fewer spills.

llvm-svn: 123811
 2011-01-19 02:35:27 +00:00
Andrew Trick
cf6999ed86 whitespace 
llvm-svn: 123810
 2011-01-19 02:26:13 +00:00
Evan Cheng
7e2b414953 Don't forget to emit the load from indirect symbol when using movw + movt to materialize GA indirect symbols. 
llvm-svn: 123809
 2011-01-19 02:16:49 +00:00
Bruno Cardoso Lopes
e0f8fee637 Create two new generic classes to represent the following VMRS/VMSR variations: 
vmrs  reg, fpexc
vmrs  reg, fpsid
vmsr  fpexc, reg
vmsr  fpsid, reg

llvm-svn: 123783
 2011-01-18 21:58:20 +00:00
Bruno Cardoso Lopes
82c6fe3dfe Fix MRS encoding for arm and thumb. 
llvm-svn: 123778
 2011-01-18 21:31:35 +00:00
Bruno Cardoso Lopes
6e4c5af01e Fix the encoding of t2ISB by using the right class and also parse it correctly 
llvm-svn: 123776
 2011-01-18 21:17:09 +00:00
Bruno Cardoso Lopes
c1e21b06b9 Follow the current hack set and enable the correct parsing of bkpt while in thumb mode. 
llvm-svn: 123772
 2011-01-18 20:55:11 +00:00
Bruno Cardoso Lopes
94247155c4 Add support for parsing and encoding ARM's official syntax for the BFI instruction 
llvm-svn: 123770
 2011-01-18 20:45:56 +00:00
Jim Grosbach
6de3a4f76f Add a FIXME. 
llvm-svn: 123769
 2011-01-18 19:59:19 +00:00
Bruno Cardoso Lopes
13cefe452d Ensure Mips::GP is properly reloaded after a function call. Patch by Sasa Stankovic 
llvm-svn: 123768
 2011-01-18 19:50:18 +00:00
Bruno Cardoso Lopes
2d509b8b40 Negative zero is not legal on mips. Patch by Sasa Stankovic 
llvm-svn: 123766
 2011-01-18 19:41:41 +00:00
Bruno Cardoso Lopes
542853bcd7 Handle (i32,i32) => f64 in a cleaner way. Patch by Sasa Stankovic 
llvm-svn: 123763
 2011-01-18 19:38:25 +00:00
Bruno Cardoso Lopes
6c5db0236a Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka 
llvm-svn: 123760
 2011-01-18 19:29:17 +00:00
Chris Lattner
08e1bf567f add a note 
llvm-svn: 123752
 2011-01-18 07:47:48 +00:00
Venkatraman Govindaraju
ecf49c6279 SPARC backend: Modified LowerCall and LowerFormalArguments so that they use CallingConv assignments. 
llvm-svn: 123749
 2011-01-18 06:09:55 +00:00
Daniel Dunbar
12dd48769d McARM: Use accessors where appropriate. 
llvm-svn: 123746
 2011-01-18 05:55:27 +00:00
Daniel Dunbar
51fef8d445 McARM: Fill in ASMOperand::dump() for memory operands. 
llvm-svn: 123745
 2011-01-18 05:55:21 +00:00
Daniel Dunbar
f966e16cb0 McARM: Make ARMOperand use a union where appropriate. 
llvm-svn: 123744
 2011-01-18 05:55:15 +00:00
Daniel Dunbar
0cff3f953b McARM: Unify ParseMemory() successfull return. 
llvm-svn: 123740
 2011-01-18 05:34:24 +00:00
Daniel Dunbar
3cb5e8b0cb McARM: Early exit on failure (NEFC). 
llvm-svn: 123739
 2011-01-18 05:34:17 +00:00
Daniel Dunbar
9ea6873c89 McARM: Always keep an offset expression, if used (instead of assuming == 0 if used but not present), and simplify logic. 
Also, clean up various non-sensicalisms in isMemModeRegThumb() and isMemModeImmThumb().

llvm-svn: 123738
 2011-01-18 05:34:11 +00:00
Daniel Dunbar
8d7ed1f6a8 McARM: Add a variety of asserts on the sanity of memory operands. 
llvm-svn: 123737
 2011-01-18 05:34:05 +00:00
Daniel Dunbar
aa5e17f3a7 McARM: Use a consistent marker for not-set OffsetRegNum. 
llvm-svn: 123736
 2011-01-18 05:33:57 +00:00
Daniel Dunbar
ba39b2fdc1 McARM: Start marking T2 address operands as such, for the benefit of the parser. 
llvm-svn: 123722
 2011-01-18 03:06:03 +00:00
Eric Christopher
e8aa8b114f The stub routine that we're calling uses test and so clobbers 
the flags.

llvm-svn: 123712
 2011-01-18 01:37:20 +00:00
Chris Lattner
047388c197 minor change to rafael's recent patches: if something is 
constant but requires a unique address, we can still put it in a
readonly section, just not a mergable one.

llvm-svn: 123711
 2011-01-18 01:23:44 +00:00
Jeffrey Yasskin
5f5e1f5ef1 Remove unused variables found by gcc-4.6's -Wunused-but-set-variable. 
llvm-svn: 123707
 2011-01-18 00:51:23 +00:00
Douglas Gregor
49f7d8c38c Add a missing <cctype> include, from Joerg Sonnenberger! 
llvm-svn: 123670
 2011-01-17 19:17:01 +00:00
Kalle Raiskila
7401b2a1db Split up RotateShift itinerary in SPU. 
'rotq*' and 'shlq*' instructions go to the odd pipeline,
wheras the inter-vector equivalents 'rot*', 'shl*' go 
to the even.

llvm-svn: 123622
 2011-01-17 13:33:19 +00:00
Kalle Raiskila
8eaf0e83d5 Don't crash SPU BE with memory accesses with big alignmnet. 
llvm-svn: 123620
 2011-01-17 11:59:20 +00:00
Evan Cheng
53ec6fc591 Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g. 
movw    r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
        movt    r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
        add     r0, pc, r0

It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.

llvm-svn: 123619
 2011-01-17 08:03:18 +00:00
Anton Korobeynikov
2a9d9ef36f Provide instruction sizes for ARMv5 variants of MUL instructions. 
This fixes PR8987

llvm-svn: 123598
 2011-01-16 21:28:33 +00:00
Anders Carlsson
d0103ebf92 Update README.txt to remove the DAE enhancement. 
llvm-svn: 123597
 2011-01-16 21:26:15 +00:00
Rafael Espindola
7933fffe38 Only put unnamed_addr constants in mergeable sections. Fixes PR8297. 
llvm-svn: 123585
 2011-01-16 17:19:34 +00:00
Chris Lattner
dde85de90f fix PR8514, a bug where the "heroic" transformation of shift/and 
into and/shift would cause nodes to move around and a dangling pointer
to happen.  The code tried to avoid this with a HandleSDNode, but 
got the details wrong.

llvm-svn: 123578
 2011-01-16 08:48:11 +00:00
Chris Lattner
91f1b21cf1 add some commentary 
llvm-svn: 123572
 2011-01-16 06:39:44 +00:00
Evan Cheng
144b435a15 Spill R4 if it's going to be used to restore SP from FP. 
llvm-svn: 123567
 2011-01-16 05:14:33 +00:00