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54 Commits

Author SHA1 Message Date
Evan Cheng
2a533e6894 Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and re-commit. 
llvm-svn: 46623
 2008-01-31 21:00:00 +00:00
Dan Gohman
4326d513ab Create a new class, MemOperand, for describing memory references 
in the backend. Introduce a new SDNode type, MemOperandSDNode, for
holding a MemOperand in the SelectionDAG IR, and add a MemOperand
list to MachineInstr, and code to manage them. Remove the offset
field from SrcValueSDNode; uses of SrcValueSDNode that were using
it are all all using MemOperandSDNode now.

Also, begin updating some getLoad and getStore calls to use the
PseudoSourceValue objects.

Most of this was written by Florian Brander, some
reorganization and updating to TOT by me.

llvm-svn: 46585
 2008-01-31 00:25:39 +00:00
Evan Cheng
07f3cd3242 A semi-gross fix for a debug info issue. When inserting the "function start" label (i.e. first label in the entry block) take care to insert it at the beginning of the block. 
llvm-svn: 46568
 2008-01-30 19:35:32 +00:00
Chris Lattner
f83aae613c rename TargetInstrDescriptor -> TargetInstrDesc. 
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695
 2008-01-07 07:27:27 +00:00
Chris Lattner
96167aa93c Rename SSARegMap -> MachineRegisterInfo in keeping with the idea 
that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.

llvm-svn: 45467
 2007-12-31 04:13:23 +00:00
Chris Lattner
e0b1ee937a Don't attribute in file headers anymore. See llvmdev for the 
discussion of this change.  Boy are my fingers tired. ;-)

llvm-svn: 45411
 2007-12-29 19:59:42 +00:00
Evan Cheng
de07843bf3 If a node that defines a physical register that is expensive to copy. The 
scheduler will try a number of tricks in order to avoid generating the
copies. This may not be possible in case the node produces a chain value
that prevent movement. Try unfolding the load from the node before to allow
it to be moved / cloned.

llvm-svn: 42625
 2007-10-05 01:39:18 +00:00
Evan Cheng
d1a77589e9 Remove simple scheduler. 
llvm-svn: 42499
 2007-10-01 20:44:07 +00:00
Evan Cheng
1a48cdc61e If two instructions are both two-address code, favors (schedule closer to 
terminator) the one that has a CopyToReg use. This fixes
2006-05-11-InstrSched.ll with -new-cc-modeling-scheme.

llvm-svn: 42453
 2007-09-28 22:32:30 +00:00
Evan Cheng
71904c241e Trim some unneeded fields. 
llvm-svn: 42442
 2007-09-28 19:24:24 +00:00
Evan Cheng
2075b448c3 Oops. Forgot this. 
llvm-svn: 42377
 2007-09-26 21:38:03 +00:00
Evan Cheng
6d8f155a63 Added major new capabilities to scheduler (only BURR for now) to support physical register dependency. The BURR scheduler can now backtrace and duplicate instructions in order to avoid "expensive / impossible to copy" values (e.g. status flag EFLAGS for x86) from being clobbered. 
llvm-svn: 42284
 2007-09-25 01:54:36 +00:00
Evan Cheng
4a117958df Use struct SDep instead of std::pair for SUnit pred and succ lists. First step 
in tracking physical register output dependencies.

llvm-svn: 42125
 2007-09-19 01:38:40 +00:00
Dan Gohman
cbb2ee9062 Add an option, -view-sunit-dags, for viewing the actual SUnit DAGs used by 
scheduling.

llvm-svn: 41556
 2007-08-28 20:32:58 +00:00
Evan Cheng
14bd520741 Instead of adding copyfromreg's to handle physical definitions. Now isel can 
simply specify them as results and let scheduledag handle them. That
is, instead of
SDOperand Flag = DAG.getTargetNode(Opc, MVT::i32, MVT::Flag, ...)
SDOperand Result = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, Flag)

Just write:
SDOperand Result = DAG.getTargetNode(Opc, MVT::i32, MVT::i32, ...)

And let scheduledag emit the move from X86::EAX to a virtual register.

llvm-svn: 40710
 2007-08-02 00:28:15 +00:00
Christopher Lamb
08bcd5c0f8 Teach DAG scheduling how to properly emit subreg insert/extract machine instructions. PR1350 
llvm-svn: 40520
 2007-07-26 08:12:07 +00:00
Evan Cheng
cf3b1c89a9 When a node value is only used by a CopyToReg, use the user's dest. This should not be restricted to nodes that produce only a single value. 
llvm-svn: 38485
 2007-07-10 07:08:32 +00:00
Chris Lattner
15fb4ef992 switch the VRBaseMap in the scheduler from an std::map to a DenseMap. This 
speeds up the isel pass from 2.5570s to 2.4722s on kc++ (3.4%).

llvm-svn: 33879
 2007-02-04 08:47:20 +00:00
Chris Lattner
b35593a1c5 switch the sched unit map over to use a DenseMap instead of std::map. This 
speeds up isel as a whole time by 2.6%.

llvm-svn: 33810
 2007-02-03 01:34:13 +00:00
Chris Lattner
a24a3aaa94 rename DenseMap to IndexedMap. 
llvm-svn: 33749
 2007-02-01 05:32:05 +00:00
Jim Laskey
64f4242072 Change the MachineDebugInfo to MachineModuleInfo to better reflect usage 
for debugging and exception handling.

llvm-svn: 33550
 2007-01-26 21:22:28 +00:00
Evan Cheng
a4bfb23119 Move to operand constraints for two-address instructions. 
llvm-svn: 31452
 2006-11-04 09:42:53 +00:00
Chris Lattner
a2eba83561 switch the SUnit pred/succ sets from being std::sets to being smallvectors. 
This reduces selectiondag time on kc++ from 5.43s to 4.98s (9%).  More
significantly, this speeds up the default ppc scheduler from ~1571ms to 1063ms,
a 33% speedup.

llvm-svn: 29743
 2006-08-17 00:09:56 +00:00
Chris Lattner
1e0b221fb2 Convert vector to smallvector: 4% speedup. 
llvm-svn: 29735
 2006-08-16 22:12:48 +00:00
Jim Laskey
f9f462bc5e Now that the ISel is available, it's possible to create a default instruction 
scheduler creator.

llvm-svn: 29452
 2006-08-01 19:14:14 +00:00
Jim Laskey
f5e160063e 1. Change use of "Cache" to "Default". 
2. Added argument to instruction scheduler creators so the creators can do
special things.
3. Repaired target hazard code.
4. Misc.

More to follow.

llvm-svn: 29450
 2006-08-01 18:29:48 +00:00
Jim Laskey
b92b14f422 Introducing plugable register allocators and instruction schedulers. 
llvm-svn: 29434
 2006-08-01 14:21:23 +00:00
Chris Lattner
f604017e47 Patches to make the LLVM sources more -pedantic clean. Patch provided 
by Anton Korobeynikov!  This is a step towards closing PR786.

llvm-svn: 28447
 2006-05-24 17:04:05 +00:00
Evan Cheng
7bb257e178 Revert an un-intended change 
llvm-svn: 28278
 2006-05-13 05:53:47 +00:00
Evan Cheng
0b8e4bca80 Add capability to scheduler to commute nodes for profit. 
If a two-address code whose first operand has uses below, it should be commuted
when possible.

llvm-svn: 28230
 2006-05-12 01:58:24 +00:00
Evan Cheng
cb2a0f392c Refactor scheduler code. Move register-reduction list scheduler to a 
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.

llvm-svn: 28226
 2006-05-11 23:55:42 +00:00
Nate Begeman
7ed816f900 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
 2006-04-22 18:53:45 +00:00
Chris Lattner
0a64d261e0 Move simple-selector-specific types to the simple selector. 
llvm-svn: 26693
 2006-03-10 07:51:18 +00:00
Chris Lattner
40b1b16c56 Simplify the interface to the schedulers, to not pass the selected heuristic 
in.

llvm-svn: 26691
 2006-03-10 07:48:52 +00:00
Chris Lattner
da5f77e3cf Move some simple-sched-specific instance vars to the simple scheduler. 
llvm-svn: 26690
 2006-03-10 07:42:02 +00:00
Chris Lattner
808cc02983 move some simple scheduler methods into the simple scheduler 
llvm-svn: 26688
 2006-03-10 07:35:21 +00:00
Chris Lattner
89a5a946f5 Make EmitNode take a SDNode instead of a NodeInfo* 
llvm-svn: 26687
 2006-03-10 07:28:36 +00:00
Chris Lattner
f1be1182f0 Store VRBase in a map, not in NodeInfo. 
llvm-svn: 26685
 2006-03-10 07:24:45 +00:00
Chris Lattner
6ef56b998f make some methods protected instead of private 
llvm-svn: 26681
 2006-03-10 06:30:11 +00:00
Chris Lattner
3f23d22d3f Change the interface for getting a target HazardRecognizer to be more clean. 
llvm-svn: 26608
 2006-03-08 04:25:59 +00:00
Chris Lattner
a0769e790e Hoist the HazardRecognizer out of the ScheduleDAGList.cpp file to where 
targets can implement them.  Make the top-down scheduler non-g5-specific.

llvm-svn: 26568
 2006-03-06 00:20:29 +00:00
Chris Lattner
4dae9a978e add an emitnoop method 
llvm-svn: 26563
 2006-03-05 23:50:42 +00:00
Jim Laskey
45dfae3a50 Breathe some life into a comment. 
llvm-svn: 26553
 2006-03-05 21:20:20 +00:00
Chris Lattner
a171bcca08 Add a new scheduling type. This is, of course, a hack. Proper factoring 
will come later.

llvm-svn: 26551
 2006-03-05 21:08:06 +00:00
Chris Lattner
291e17764d add a method 
llvm-svn: 26357
 2006-02-24 18:53:51 +00:00
Chris Lattner
ed45ad33b7 Make the LLVM headers "-ansi -pedantic -Wno-long-long" clean. 
Patch by Martin Partel!

llvm-svn: 26313
 2006-02-22 16:23:43 +00:00
Evan Cheng
062ac6e46b Get rid of some memory leaks identified by Valgrind 
llvm-svn: 25960
 2006-02-04 06:49:00 +00:00
Evan Cheng
cf49c6411a Duh. 
llvm-svn: 25628
 2006-01-26 00:28:35 +00:00
Evan Cheng
168b8c5b29 No need to keep track of top and bottom nodes in a group since the vector is 
already in order. Thanks Jim for pointing it out.

llvm-svn: 25608
 2006-01-25 18:54:24 +00:00
Evan Cheng
27e82023a4 Some minor scheduler changes. 
llvm-svn: 25597
 2006-01-25 09:07:50 +00:00