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Commit Graph

190712 Commits

Author SHA1 Message Date
Igor Kudrin
70ab7c2444 [DWARF] Do not pass Version to DWARFExpression. NFCI.
The Version was used only to determine the size of an operand of
DW_OP_call_ref. The size was 4 for all versions apart from 2, but
the DW_OP_call_ref operation was introduced only in DWARF3. Thus,
the code may be simplified and using of Version may be eliminated.

Differential Revision: https://reviews.llvm.org/D73264
2020-01-27 19:08:46 +07:00
Igor Kudrin
b22a094351 [DWARF] Simplify DWARFExpression. NFC.
As DataExtractor already has a method to extract an unsigned value of
a specified size, there is no need to duplicate that.

Differential Revision: https://reviews.llvm.org/D73263
2020-01-27 19:08:46 +07:00
David Stenberg
e4d1228ccd Improvements to call site register worklist
Summary:
This fixes PR44118. For cases where we have a chain like this:

  R8 = R1 (entry value)
  R0 = R8
  call @foo R0

the code that emits call site entries using entry values would not
follow that chain, instead emitting a call site entry with R8 as
location rather than R0. Such a case was discovered when originally
adding dbgcall-site-orr-moves.mir. This patch fixes that issue. This is
done by changing the ForwardedRegWorklist set to a map in which the
worklist registers always map to the parameter registers that they
describe.

Another thing this patch fixes is that worklist registers now can
describe more than one parameter register at a time. Such a case
occurred in dbgcall-site-interpretation.mir, resulting in a call site
entry not being emitted for one of the parameters.

Reviewers: djtodoro, NikolaPrica, aprantl, vsk

Reviewed By: vsk

Subscribers: hiraditya, llvm-commits

Tags: #debug-info, #llvm

Differential Revision: https://reviews.llvm.org/D73168
2020-01-27 12:41:42 +01:00
Sjoerd Meijer
1ac7c4fcb9 [ARM][MVE] Tail-predication: support constant trip count
We had support for runtime trip count values, but not constants, and this adds
supports for that.

And added a minor optimisation while I was add it: don't invoke Cleanup when
there's nothing to clean up.

Differential Revision: https://reviews.llvm.org/D73198
2020-01-27 11:05:26 +00:00
Sam Parker
15c79be89a [ARM][LowOverheadLoops] Dont ignore VCTP
When expanding the LoopStart, we try to remove the iteration count
calculation. However, if part of the calculation was also used to
calculate the number of elements we could end up deleting
instructions that were required to feed DLSTP/WLSTP.

Differential Revision: https://reviews.llvm.org/D73275
2020-01-27 10:59:12 +00:00
David Stenberg
25a13f02ab Don't separate imp/expl def handling for call site params
Summary:
Since D70431 the describeLoadedValue() hook takes a parameter register,
meaning that it can now be asked to describe any register. This means
that we can drop the difference between explicit and implicit defines
that we previously had in collectCallSiteParameters().

I have not found any case for any upstream targets where a parameter
register is only implicitly defined, and does not overlap with any
explicit defines. I don't know if such a case would even make sense. So
as far as I have tested, this patch should be a non-functional change.
However, this reduces the complexity of the code a bit, and it will
simplify the implementation of an upcoming patch which solves PR44118.

Reviewers: djtodoro, NikolaPrica, aprantl, vsk

Reviewed By: djtodoro, vsk

Subscribers: hiraditya, llvm-commits

Tags: #debug-info, #llvm

Differential Revision: https://reviews.llvm.org/D73167
2020-01-27 11:31:09 +01:00
Georgii Rymar
7bdcb225b9 [llvm-readobj] - Refine --needed-libs implementation and add a test.
We have no good test for --needed-libs option.
The one we have as a part of Object/readobj-shared-object.test
is not complete.

In this patch I've did a minor NFC changes to the implementation and
added a test. This allowed to remove this piece from
Object/readobj-shared-object.test

Differential revision: https://reviews.llvm.org/D73174
2020-01-27 13:29:28 +03:00
Guillaume Chatelet
8f250c81f4 [Alignment][NFC] Use Align with CreateAlignedLoad
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet, bollu

Subscribers: hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D73449
2020-01-27 10:58:36 +01:00
Georgii Rymar
dbe828563d [llvm-readobj] - Add a test for --dyn-symbols when there are no dynamic symbols.
It removes the Object/readobj-absent.test test and creates a one more case in
dyn-symbols.test we have.

Differential revision: https://reviews.llvm.org/D73169
2020-01-27 12:34:58 +03:00
Georgii Rymar
0e3dc3bd7a [llvm-readobj] - Add a test for --hash-table option.
We had no test for --hash-table in tools/llvm-readobj.

The one we had was in test/Object and checked that
it is possible to dump the hash table even when an object
doesn't have a section header table.

In this patch I created a test, moved and merged the existent one.
During moving I converted it to be YAML based to stop using the
precompiled binary.

Differential revision: https://reviews.llvm.org/D73105
2020-01-27 12:28:21 +03:00
Guillaume Chatelet
e18e01b543 [Alignment][NFC] Use Align with CreateMaskedScatter/Gather
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

This patch shows that CreateMaskedScatter/CreateMaskedGather can only take positive non zero alignment values.

Reviewers: courbet

Subscribers: hiraditya, llvm-commits, delena

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73361
2020-01-27 10:17:14 +01:00
Petar Avramovic
75e76863f0 [MIPS GlobalISel] Select population count (popcount)
G_CTPOP is generated from llvm.ctpop.<type> intrinsics, clang generates
these intrinsics from __builtin_popcount and __builtin_popcountll.
Add lower and narrow scalar for G_CTPOP.
Lower G_CTPOP for MIPS32.

Differential Revision: https://reviews.llvm.org/D73216
2020-01-27 09:59:50 +01:00
Petar Avramovic
4b729fba3d [MIPS GlobalISel] Select count trailing zeros
llvm.cttz.<type> intrinsic has additional i1 argument is_zero_undef,
it tells whether zero as the first argument produces a defined result.
G_CTTZ is generated from llvm.cttz.<type> (<type> <src>, i1 false)
intrinsics, clang generates these intrinsics from __builtin_ctz and
__builtin_ctzll.
G_CTTZ_ZERO_UNDEF comes from llvm.cttz.<type> (<type> <src>, i1 true).
Clang generates such intrinsics as parts of expansion of builtin_ffs
and builtin_ffsll. It is also traditionally part of and many
algorithms that are now predicated on avoiding zero-value inputs.

Add narrow scalar (algorithm uses G_CTTZ_ZERO_UNDEF) for G_CTTZ.
Lower G_CTTZ and G_CTTZ_ZERO_UNDEF for MIPS32.

Differential Revision: https://reviews.llvm.org/D73215
2020-01-27 09:51:06 +01:00
Petar Avramovic
4fef9ac108 [MIPS GlobalISel] Select count leading zeros
llvm.ctlz.<type> intrinsic has additional i1 argument is_zero_undef,
it tells whether zero as the first argument produces a defined result.
MIPS clz instruction returns 32 for zero input.
G_CTLZ is generated from llvm.ctlz.<type> (<type> <src>, i1 false)
intrinsics, clang generates these intrinsics from __builtin_clz and
__builtin_clzll.
G_CTLZ_ZERO_UNDEF can also be generated from llvm.ctlz with true as
second argument. It is also traditionally part of and many algorithms
that are now predicated on avoiding zero-value inputs.

Add narrow scalar for G_CTLZ (algorithm uses G_CTLZ_ZERO_UNDEF).
Lower G_CTLZ_ZERO_UNDEF and select G_CTLZ for MIPS32.

Differential Revision: https://reviews.llvm.org/D73214
2020-01-27 09:43:38 +01:00
Fangrui Song
274a5fbacd [MachineVerifier] Simplify and delete LLVM_VERIFY_MACHINEINSTRS from a comment. NFC
The environment variable has been unused since r228079.
2020-01-27 00:31:23 -08:00
Wang, Pengfei
0507f61bd2 [FPEnv] Divide macro INSTRUCTION into INSTRUCTION and DAG_INSTRUCTION,
and macro FUNCTION likewise. NFCI.

Some functions like fmuladd don't really have a node, we should divide
the declaration form those have node to avoid introducing fake nodes.

Differential Revision: https://reviews.llvm.org/D72871
2020-01-27 10:38:05 +08:00
Roman Lebedev
daa0abe865 [X86][BdVer2] Polish LEA instruction scheduling info
Based on exhaustive llvm-exegesis measurements.
There may still be some imperfections for LEA16r/LEA32r.

Much like was observed in D68646, i'm also measuring some outliers
with some specific registers.
2020-01-26 22:17:27 +03:00
Roman Lebedev
399f253bb6 [NFC][MCA] Re-autogenerate all check lines in all X86 MCA tests
Some whitespace issues have crept in,
and some znver2 check lines were missing..
2020-01-26 22:17:26 +03:00
Simon Pilgrim
a5fc7e6584 [InstCombine] Add extra shift(c1,add(c2,y)) tests for PR15141 2020-01-26 19:04:12 +00:00
Simon Pilgrim
54efe84932 [X86][AVX] Extend combineCommutableSHUFP to handle v8f32 and v16f32 commutable shufps patterns 2020-01-26 19:04:12 +00:00
Guillaume Chatelet
5d96838bf7 [IR] masked gather/scatter alignment should be set
Summary: masked_load and masked_store instructions require the alignment to be specified and a power of two. It seems to me that this requirement applies to masked_gather and masked_scatter as well.

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73179
2020-01-26 18:51:36 +01:00
Simon Pilgrim
2df81e215e [X86][AVX] Add tests showing combineCommutableSHUFP failure to handle v8f32 and v16f32 commutable shufps patterns 2020-01-26 14:36:24 +00:00
Simon Pilgrim
800fdc3aba [X86][SSE] combineCommutableSHUFP - permilps(shufps(load(),x)) --> permilps(shufps(x,load()))
Pull out combineTargetShuffle code added in rG3fd5d1c6e7db into a helper function and extend it to handle shufps(shufps(load(),x),y) and shufps(y,shufps(load(),x)) cases as well.
2020-01-26 14:36:23 +00:00
Simon Pilgrim
375cf300cf [TargetLowering] Respect recursive depth in SimplifyDemandedBits call to ComputeNumSignBits 2020-01-26 10:01:56 +00:00
Maheaha Shivamallappa
53ded98375 AMDGPU/GlobalISel: Clean-up code around ISel for Intrinsics.
Summary:
A minor code clean-up around ISel for intrinsic llvm.amdgcn.end.cf()

Reviewers: arsenm, mshivama

Reviewed By: arsenm

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73358
2020-01-26 14:09:31 +05:30
George Burgess IV
e09bf79aaa [Support] constify a method; NFC
Pointed out by Stepan on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2020-January/138617.html
2020-01-25 21:48:04 -08:00
Craig Topper
cf6099d98c [X86] Use a macro to convert X86ISD names to strings in getTargetNodeName.
Every case in the switch had a string version of themselves. Two
of them had a typo that used : instead of ::

By using a macro we can automate the string creation and avoid
the possibility of typos like this.

This is similar to what is done on the AMDGPU target.
2020-01-25 18:27:29 -08:00
Simon Pilgrim
e88b5ce1b3 [SelectionDAG] ComputeNumSignBits - add DemandedElts support for MIN/MAX ops 2020-01-25 20:21:14 +00:00
Simon Pilgrim
bf8ae6ec9f [X86] Add tests showing ComputeNumSignBits's failure to use DemandedElts for MIN/MAX opcodes 2020-01-25 19:28:57 +00:00
Simon Pilgrim
4698ac9eca [SelectionDAG] ComputeNumSignBits - add support for rotate non-uniform vector amounts 2020-01-25 19:15:05 +00:00
Simon Pilgrim
f80272cd53 [SelectionDAG] ComputeNumSignBits - add support for rotate uniform vector amounts 2020-01-25 18:55:47 +00:00
Simon Pilgrim
7b1dd7f901 [X86] Add tests showing ComputeNumSignBits's failure to see through rotate vector amounts 2020-01-25 18:24:51 +00:00
Simon Pilgrim
ab495709db [TargetLowering] SimplifyDemandedBits - Remove ashr if all our demandedbits already match the sign bit
Differential Revision: https://reviews.llvm.org/D73412
2020-01-25 17:36:46 +00:00
Sam McCall
0fbf4f0211 [Support] Fix race in threading test, found by TSan 2020-01-25 15:22:12 +01:00
Tom Stellard
55630191a3 AMDGPU/SILoadStoreOptimizer: Fix uninitialized variable error
This was introduced by 86c944d790728891801778b8d98c2c65a83f36a5 and
caught by the sanitizer-x86_64-linux-fast bot.
2020-01-24 21:53:05 -08:00
Matt Arsenault
22688e4b7f AMDGPU: Generate test checks 2020-01-24 23:25:57 -05:00
Tom Stellard
fe894cb93a AMDGPU/SILoadStoreOptimizer: Improve merging of out of order offsets
Summary:
This improves merging of sequences like:

store a, ptr + 4
store b, ptr + 8
store c, ptr + 12
store d, ptr + 16
store e, ptr + 20
store f, ptr

Prior to this patch the basic block was scanned in order to find instructions
to merge and the above sequence would be transformed to:

store4 <a, b, c, d>, ptr + 4
store e, ptr + 20
store r, ptr

With this change, we now sort all the candidate merge instructions by their offset,
so instructions are visited in offset order rather than in the order they appear
in the basic block.  We now transform this sequnce into:

store4 <f, a, b, c>, ptr
store2 <d, e>, ptr + 16

Another benefit of this change is that since we have sorted the mergeable lists
by offset, we can easily check if an instruction is mergeable by checking the
offset of the instruction that becomes before or after it in the sorted list.
Once we determine an instruction is not mergeable we can remove it from the list
and avoid having to do the more expensive mergeablilty checks.

Reviewers: arsenm, pendingchaos, rampitec, nhaehnle, vpykhtin

Reviewed By: arsenm, nhaehnle

Subscribers: kerbowa, merge_guards_bot, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65966
2020-01-24 19:45:56 -08:00
LLVM GN Syncbot
b191b5e878 [gn build] Port dd8e0a0a23b 2020-01-25 02:40:48 +00:00
Nico Weber
9a83eff740 [gn build] (manually) merge 81b700e302b1 2020-01-24 21:40:26 -05:00
Weverything
d91bb42dca Fix header includes after 0697bcb66f1d82f2fd447e9d13b74d141c3ce085 2020-01-24 18:32:54 -08:00
Vedant Kumar
0e3d6e2d5b Revert "Reland: [DWARF] Allow cross-CU references of subprogram definitions"
... as well as:
Revert "[DWARF] Defer creating declaration DIEs until we prepare call site info"

This reverts commit fa4701e1979553c2df61698ac1ac212627630442.

This reverts commit 79daafc90308787b52a5d3a7586e82acd5e374b3.

There have been reports of this assert getting hit:

CalleeDIE && "Could not find DIE for call site entry origin
2020-01-24 18:07:54 -08:00
Reid Kleckner
eba62584a3 [Support] Fix up header comments after splitting Allocator.h, NFC 2020-01-24 17:43:38 -08:00
Reid Kleckner
8067073c48 [Support] Split MallocAllocator out of Allocator.h
StringMap.h is very popular (4K uses), and it doesn't need to see
BumpPtrAllocator, which is relatively expensive according to
ClangBuildAnalyzer. StringMap only needs MallocAllocator, so split that
into AllocatorBase.h and use it instead.

Here is the change in header uses:
$ diff -u thedeps-before.txt thedeps-after.txt | \
    grep '^[-+] ' |  sort | uniq -c | sort -nr
   3993 +    ../llvm/include/llvm/Support/AllocatorBase.h
    758 -    ../llvm/include/llvm/Support/Allocator.h
    270 -    ../llvm/include/llvm/Support/Alignment.h
     13 -    ../llvm/include/llvm/Support/Host.h
      6 -    ../llvm/include/llvm/ADT/StringMap.h
      4 -    ../llvm/include/llvm/Support/SwapByteOrder.h
      4 -    ../llvm/include/llvm/Support/MathExtras.h
      4 -    ../llvm/include/llvm/Support/AlignOf.h
      4 -    ../llvm/include/llvm/ADT/SmallVector.h
      1 -    ../llvm/include/llvm/Support/PointerLikeTypeTraits.h

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D73392
2020-01-24 17:29:32 -08:00
Reid Kleckner
efe8889235 [IR] Move CallBase::getOperandBundlesAsDefs out of line, NFC
Copying operand bundles doesn't need to be inlined, and this template
instantiation shows up in ClangBuildAnalyzer.
2020-01-24 17:25:42 -08:00
Quentin Colombet
f9aef81caa [GISelKnownBits] Add support for PHIs
Teach the GISelKnowBits analysis how to deal with PHI operations.
PHIs are essentially COPYs happening on edges, so we can just reuse
the code for COPY.

This is NFC COPY-wise has we leave Depth untouched when calling
computeKnownBitsImpl for COPYs, like it was before this patch.
Increasing Depth is however required for PHIs as they may loop back to
themselves and we would end up in an infinite loop if we were not
increasing Depth.

Differential Revision: https://reviews.llvm.org/D73317
2020-01-24 16:43:52 -08:00
Reid Kleckner
c822eded13 [codeview] Prune SimpleTypeSerializer.h headers, NFC
These are left over from when the class was more complicated. Add a
header comment banner to the .cpp file, which was missing.
2020-01-24 16:07:36 -08:00
@justice_adams (Justice Adams)
56d09f370d [SelectionDag] Updated FoldConstantArithmetic method signature in preparation for merge with FoldConstantVectorArithmetic
Updated FoldConstantArithmetic method signature to match that of
FoldConstantVectorArithmetic in preparation for merging the two
functions together

https://bugs.llvm.org/show_bug.cgi?id=36544

This is the first step in combining the various
FoldConstantVectorArithmetic and FoldConstantVectorArithmetic
functions into one FoldConstantArithmetic function.

Differential Revision: https://reviews.llvm.org/D72870
2020-01-24 18:00:58 -05:00
Craig Topper
21a7c5eac7 [X86] Break the loop in LowerReturn into 2 loops. NFCI
I believe for STRICT_FP I need to use a STRICT_FP_EXTEND for the extending to f80 for returning f32/f64 in 32-bit mode when SSE is enabled. The STRICT_FP_EXTEND node requires a Chain. I need to get that node onto the chain before any CopyToRegs are emitted. This is because all the CopyToRegs are glued and chained together. So I can't put a STRICT_FP_EXTEND on the chain between the glued nodes without also glueing the STRICT_ FP_EXTEND.

This patch moves all the extend creation to a first pass and then creates the copytoregs and fills out RetOps in a second pass.

Differential Revision: https://reviews.llvm.org/D72665
2020-01-24 14:44:38 -08:00
Roman Lebedev
695c422f49 [X86] Make llc --help output readable again
Long `cl::value_desc()` is added right after the flag name,
before `cl::desc()` column. And thus the `cl::desc()` column,
for all flags, is padded to the right,
which makes the output unreadable.
2020-01-25 01:43:52 +03:00
Evgenii Stepanov
67d6f58389 [msan] Instrument x86.pclmulqdq* intrinsics.
Summary:
These instructions ignore parts of the input vectors which makes the
default MSan handling too strict and causes false positive reports.

Reviewers: vitalybuka, RKSimon, thakis

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73374
2020-01-24 14:31:06 -08:00