Colin LeMahieu
769b0f293d
[Hexagon] Adding encoding information for absolute address loads.
...
llvm-svn: 225279
2015-01-06 18:38:26 +00:00
Colin LeMahieu
6a3f537bb7
[Hexagon] Fix 225267. GP register is not yet fully implemented. Removing Uses [GP] maintains existing behavior.
...
llvm-svn: 225270
2015-01-06 16:52:38 +00:00
Colin LeMahieu
7c1bcabc22
[Hexagon] Adding dealloc_return encoding and absolute address stores.
...
llvm-svn: 225267
2015-01-06 16:15:15 +00:00
Colin LeMahieu
9f18605465
[Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references.
...
llvm-svn: 225210
2015-01-05 21:36:38 +00:00
Colin LeMahieu
139c47f671
[Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts.
...
llvm-svn: 225201
2015-01-05 20:56:41 +00:00
Colin LeMahieu
9a85ae53a7
[Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without encoding bits.
...
llvm-svn: 225199
2015-01-05 20:35:54 +00:00
Colin LeMahieu
ef8cb75b7d
[Hexagon] Adding V4 logic-logic instructions and tests.
...
llvm-svn: 225198
2015-01-05 20:14:58 +00:00
Colin LeMahieu
e42756883b
[Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions.
...
llvm-svn: 225197
2015-01-05 20:04:40 +00:00
Colin LeMahieu
caea68537b
[Hexagon] Adding round reg/imm and bitsplit instructions.
...
llvm-svn: 225188
2015-01-05 18:08:21 +00:00
Colin LeMahieu
664727ddb9
[Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doubleword bitfield extract, word parity, accumulating multiplies with saturation.
...
llvm-svn: 225024
2014-12-31 00:08:34 +00:00
Colin LeMahieu
ce5a9848a5
[Hexagon] Adding double-logic on predicate instructions.
...
llvm-svn: 225018
2014-12-30 23:22:39 +00:00
Colin LeMahieu
d9937c62e9
[Hexagon] Adding newvalue compare and jumps.
...
llvm-svn: 225015
2014-12-30 23:04:21 +00:00
Colin LeMahieu
4d12863d57
[Hexagon] Adding postincrement register newvalue stores.
...
llvm-svn: 225010
2014-12-30 22:34:08 +00:00
Colin LeMahieu
e11e421bc5
[Hexagon] Removing old newvalue store variants. Adding postincrement immediate newvalue stores.
...
llvm-svn: 225009
2014-12-30 22:28:31 +00:00
Colin LeMahieu
a76ddd9ae4
[Hexagon] Adding indexed store new-value variants.
...
llvm-svn: 225007
2014-12-30 22:00:26 +00:00
Colin LeMahieu
ef54aa0778
[Hexagon] Adding indexed store of immediates.
...
llvm-svn: 225006
2014-12-30 21:01:38 +00:00
Colin LeMahieu
4a47613bb1
[Hexagon] Adding indexed stores.
...
llvm-svn: 225005
2014-12-30 20:42:23 +00:00
Colin LeMahieu
be9ae58d93
[Hexagon] Adding reg-reg indexed load forms.
...
llvm-svn: 224997
2014-12-30 18:58:47 +00:00
Colin LeMahieu
0b193a8b1c
[Hexagon] Dropping old combine instructions without encodings.
...
llvm-svn: 224992
2014-12-30 17:53:54 +00:00
Colin LeMahieu
c9924ffc90
[Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare to general register reg-imm form.
...
llvm-svn: 224991
2014-12-30 17:39:24 +00:00
Colin LeMahieu
300c89d245
[Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares.
...
llvm-svn: 224989
2014-12-30 15:44:17 +00:00
Colin LeMahieu
c8d82f0149
[Hexagon] Reapplying 224775 load words.
...
llvm-svn: 224786
2014-12-23 20:02:16 +00:00
Colin LeMahieu
240787f100
Reverting 224775 until mayLoad flag is addressed.
...
llvm-svn: 224783
2014-12-23 19:22:59 +00:00
Colin LeMahieu
9d1882c36f
[Hexagon] Adding word loads.
...
llvm-svn: 224775
2014-12-23 18:06:56 +00:00
Colin LeMahieu
263816de1a
[Hexagon] Adding signed halfword loads.
...
llvm-svn: 224774
2014-12-23 17:25:57 +00:00
Colin LeMahieu
df751494b1
[Hexagon] Adding unsigned halfword load.
...
llvm-svn: 224772
2014-12-23 16:42:57 +00:00
Colin LeMahieu
c88fff49c9
[Hexagon] Adding classes and load unsigned byte instruction, updating usages.
...
llvm-svn: 224730
2014-12-22 21:20:03 +00:00
Colin LeMahieu
4c325f2cef
[Hexagon] Removing old variants of instructions and updating references.
...
llvm-svn: 224612
2014-12-19 20:29:29 +00:00
Colin LeMahieu
de7232ce5b
[Hexagon] Adding encoding information for sign extend word instruction.
...
llvm-svn: 224026
2014-12-11 16:43:06 +00:00
Colin LeMahieu
6bafcd8eab
[Hexagon] Adding combine ri/ir instructions.
...
llvm-svn: 223971
2014-12-10 22:23:07 +00:00
Colin LeMahieu
5a093ecd78
[Hexagon] Adding encodings for JR class instructions. Updating complier usages.
...
llvm-svn: 223967
2014-12-10 21:24:10 +00:00
Colin LeMahieu
867128021f
[Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests.
...
llvm-svn: 223821
2014-12-09 20:23:30 +00:00
Colin LeMahieu
2b8dd30859
[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.
...
llvm-svn: 223800
2014-12-09 18:16:49 +00:00
Colin LeMahieu
4f286f5f23
[Hexagon] Updating mux_ir/ri/ii/rr with encoding bits
...
llvm-svn: 223515
2014-12-05 21:09:27 +00:00
Craig Topper
0734168db8
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.
...
llvm-svn: 222801
2014-11-26 00:46:26 +00:00
Colin LeMahieu
4a42d4abd9
[Hexagon] Replacing cmp* instructions with ones that contain encoding bits.
...
llvm-svn: 222771
2014-11-25 18:20:52 +00:00
Sid Manning
f1133d5d3f
Add missing attributes !cmp.[eq,gt,gtu] instructions.
...
These instructions do not indicate they are extendable or the
number of bits in the extendable operand. Rename to match
architected names. Add a testcase for the intrinsics.
llvm-svn: 218453
2014-09-25 13:09:54 +00:00
Tim Northover
20001e6010
TableGen: permit non-leaf ComplexPattern uses
...
This allows the results of a ComplexPattern check to be distributed to separate
named Operands, instead of the current system where all results must apply (and
match perfectly) with a single Operand.
For example, if "some_addrmode" is a ComplexPattern producing two results, you
can write:
def : Pat<(load (some_addrmode GPR64:$base, imm:$offset)),
(INST GPR64:$base, imm:$offset)>;
This should allow neater instruction definitions in TableGen that don't put all
possible aspects of addressing into a single operand, but are still usable with
relatively simple C++ CodeGen idioms.
llvm-svn: 209206
2014-05-20 11:52:46 +00:00
Jyotsna Verma
c9cece4644
[Hexagon] Add New TSFlags to be used in the upcoming patches.
...
llvm-svn: 208239
2014-05-07 19:07:34 +00:00
Alp Toker
f3e1a22860
Fix typos
...
llvm-svn: 202107
2014-02-25 04:21:15 +00:00
Alp Toker
e845f8af67
Correct word hyphenations
...
This patch tries to avoid unrelated changes other than fixing a few
hyphen-related ambiguities and contractions in nearby lines.
llvm-svn: 196471
2013-12-05 05:44:44 +00:00
NAKAMURA Takumi
cff4821ad4
Prune trailing linefeeds.
...
llvm-svn: 193511
2013-10-28 04:07:31 +00:00
Jyotsna Verma
980fae33f3
Hexagon: Add patterns to generate 'combine' instructions.
...
llvm-svn: 181805
2013-05-14 17:16:38 +00:00
Jyotsna Verma
2dfc0b2d13
Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.
...
llvm-svn: 181624
2013-05-10 20:27:34 +00:00
Jyotsna Verma
71c6bf55f2
Hexagon: Set accessSize and addrMode on all load/store instructions.
...
llvm-svn: 181324
2013-05-07 15:06:29 +00:00
Jyotsna Verma
0ec07a2dbc
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
...
llvm-svn: 181235
2013-05-06 18:49:23 +00:00
Jyotsna Verma
08d387d6f8
reverting r180953
...
llvm-svn: 180964
2013-05-02 22:10:59 +00:00
Jyotsna Verma
cd4db6de1c
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
...
llvm-svn: 180953
2013-05-02 21:21:57 +00:00
Jyotsna Verma
a3587dd6bb
Hexagon: Use multiclass for Jump instructions.
...
llvm-svn: 180885
2013-05-01 21:37:34 +00:00
Jyotsna Verma
4a5d195942
Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.
...
llvm-svn: 180145
2013-04-23 21:17:40 +00:00