Evan Cheng
626e85dfc2
Fix MOVrx, MOVsrl_flag, and MOVsra_flag encodings.
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llvm-svn: 59314
2008-11-14 20:09:11 +00:00
Evan Cheng
3c0113820b
Fix pre- and post-indexed load / store encoding bugs.
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llvm-svn: 59230
2008-11-13 07:34:59 +00:00
Evan Cheng
7fef8cfe75
Consolidate formats; fix FCMPED etc. encodings.
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llvm-svn: 59107
2008-11-12 07:18:38 +00:00
Evan Cheng
21df9f3b4f
Jump table JIT support. Work in progress.
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llvm-svn: 58836
2008-11-07 09:06:08 +00:00
Evan Cheng
88726d85eb
Encode misc arithmetic instructions.
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llvm-svn: 58828
2008-11-07 01:41:35 +00:00
Evan Cheng
3bcb71912f
Encode extend instructions; more clean up.
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llvm-svn: 58818
2008-11-06 22:15:19 +00:00
Evan Cheng
af54e4ed18
- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
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- Consolidate instruction formats.
- Other clean up.
llvm-svn: 58808
2008-11-06 17:48:05 +00:00
Evan Cheng
aa24d19533
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
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llvm-svn: 58800
2008-11-06 08:47:38 +00:00
Evan Cheng
078361bddc
Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
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llvm-svn: 58793
2008-11-06 03:35:07 +00:00
Evan Cheng
058721d10b
Fix so_imm encoding bug; add support for MOVi2pieces.
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llvm-svn: 58790
2008-11-06 02:25:39 +00:00
Evan Cheng
ca6759021b
Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
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llvm-svn: 58789
2008-11-06 01:21:28 +00:00
Evan Cheng
ce97712aa6
Encode pic load / store instructions; fix some encoding bugs.
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llvm-svn: 58780
2008-11-05 23:22:34 +00:00
Evan Cheng
9970c31dcf
Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
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llvm-svn: 58764
2008-11-05 18:35:52 +00:00
Jim Grosbach
5262898365
Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
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llvm-svn: 58626
2008-11-03 18:38:31 +00:00
Evan Cheng
6a824a7741
Forgot this in last commit.
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llvm-svn: 58527
2008-10-31 19:11:09 +00:00
Jim Grosbach
d0ff59ec42
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right)
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llvm-svn: 57524
2008-10-14 20:36:24 +00:00
Chris Lattner
7910d59d44
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
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parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
llvm-svn: 57385
2008-10-11 22:08:30 +00:00
Jim Grosbach
8ac554209f
Unconditional branch instruction encoding fix. Needs to use ABI, not AXI, to get the proper opcode bits.
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llvm-svn: 57262
2008-10-07 21:08:09 +00:00
Jim Grosbach
a52546fec4
Fix Opcode values of CMP and CMN
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llvm-svn: 57251
2008-10-07 17:40:46 +00:00
Evan Cheng
f2c04a10e6
Fix addrmode1 instruction encodings; fix bx_ret encoding.
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llvm-svn: 56277
2008-09-17 07:53:38 +00:00
Evan Cheng
0a3a595612
Revert 56176. All those instruction formats are still needed.
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llvm-svn: 56180
2008-09-13 01:35:33 +00:00
Evan Cheng
18fd8337b3
Eliminate unnecessary instruction formats.
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llvm-svn: 56176
2008-09-12 23:15:39 +00:00
Dan Gohman
89660301e3
Rename ConstantSDNode::getValue to getZExtValue, for consistency
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with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
llvm-svn: 56159
2008-09-12 16:56:44 +00:00
Evan Cheng
738426a2a1
Control flow instruction encodings.
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llvm-svn: 55601
2008-09-01 08:25:56 +00:00
Evan Cheng
36170e63a3
ldm / stm instruction encodings.
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llvm-svn: 55599
2008-09-01 07:48:18 +00:00
Evan Cheng
01019d7909
AXI2 and AXI3 instruction encodings.
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llvm-svn: 55598
2008-09-01 07:34:13 +00:00
Evan Cheng
26305b192f
addrmode3 instruction encodings.
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llvm-svn: 55596
2008-09-01 07:00:14 +00:00
Evan Cheng
fa095aec1e
Rest of addrmode2 instruction encodings.
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llvm-svn: 55593
2008-09-01 01:27:33 +00:00
Evan Cheng
4c8338c0d3
Addr2 word / byte load encodings.
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llvm-svn: 55591
2008-08-31 19:02:21 +00:00
Evan Cheng
5150e3da45
MVN is addrmode1.
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llvm-svn: 55530
2008-08-29 07:36:24 +00:00
Evan Cheng
c50df85672
Refactor ARM instruction format definitions into a separate file. No functionality changes.
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llvm-svn: 55518
2008-08-28 23:39:26 +00:00
Dan Gohman
9742f7772d
Rename SDOperand to SDValue.
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llvm-svn: 54128
2008-07-27 21:46:04 +00:00
Evan Cheng
11d2c09adc
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
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llvm-svn: 48380
2008-03-15 00:03:38 +00:00
Bill Wendling
2cae66e28b
Final de-tabification.
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llvm-svn: 47663
2008-02-27 06:33:05 +00:00
Chris Lattner
41717f6989
This commit changes:
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1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
llvm-svn: 46140
2008-01-17 19:59:44 +00:00
Chris Lattner
6846e346a8
rename SDTRet -> SDTNone.
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Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.
llvm-svn: 46017
2008-01-15 22:02:54 +00:00
Chris Lattner
9b4f2b2316
get def use info more correct.
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llvm-svn: 45821
2008-01-10 05:12:37 +00:00
Evan Cheng
9de4f35e9f
Only mark instructions that load a single value without extension as isSimpleLoad = 1.
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llvm-svn: 45727
2008-01-07 23:56:57 +00:00
Chris Lattner
14310afe42
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
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llvm-svn: 45667
2008-01-06 23:38:27 +00:00
Chris Lattner
5489888580
rename isStore -> mayStore to more accurately reflect what it captures.
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llvm-svn: 45656
2008-01-06 08:36:04 +00:00
Chris Lattner
2bb919b542
remove explicit isStore flags that are now inferrable.
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llvm-svn: 45653
2008-01-06 05:55:01 +00:00
Chris Lattner
ad9a6ccb83
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Evan Cheng
64a1febf9a
Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
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llvm-svn: 44960
2007-12-12 23:12:09 +00:00
Bill Wendling
934fcd87e7
Unifacalize the CALLSEQ{START,END} stuff.
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llvm-svn: 44045
2007-11-13 09:19:02 +00:00
Bill Wendling
cc75435ebf
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
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adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
llvm-svn: 44037
2007-11-13 00:44:25 +00:00
Owen Anderson
aba398a5ce
Add a flag for indirect branch instructions.
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Target maintainers: please check that the instructions for your target are correctly marked.
llvm-svn: 44012
2007-11-12 07:39:39 +00:00
Evan Cheng
b43255bc68
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
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llvm-svn: 41863
2007-09-11 19:55:27 +00:00
Evan Cheng
24e8e4d6ef
80 col.
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llvm-svn: 41812
2007-09-10 22:22:23 +00:00
Raul Herbster
49b44eae34
ARM instruction table was modified by adding information to generate multiply instruction of V5TE.
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llvm-svn: 41626
2007-08-30 23:25:47 +00:00
Evan Cheng
8c896cc115
Initial JIT support for ARM by Raul Fernandes Herbster.
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llvm-svn: 40887
2007-08-07 01:37:15 +00:00