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174 Commits

Author SHA1 Message Date
Evan Cheng
ab0a826b88 Indexed loads each has 2 outputs. 
llvm-svn: 40658
 2007-08-01 00:12:08 +00:00
Evan Cheng
53cb03b583 No more noResults. 
llvm-svn: 40132
 2007-07-21 00:34:19 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Evan Cheng
abcf3842bb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
llvm-svn: 38501
 2007-07-10 18:08:01 +00:00
Evan Cheng
d9d3be078c No need for ccop anymore. 
llvm-svn: 37965
 2007-07-06 23:34:09 +00:00
Evan Cheng
3b1b3eba6a Do away with ImmutablePredicateOperand. 
llvm-svn: 37961
 2007-07-06 23:22:46 +00:00
Evan Cheng
c2c0b495ed PredicateDefOperand -> OptionalDefOperand. 
llvm-svn: 37931
 2007-07-06 01:00:49 +00:00
Evan Cheng
a59422068f Unbreak the build. 
llvm-svn: 37914
 2007-07-05 17:13:19 +00:00
Evan Cheng
ef8a1bcbc3 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
llvm-svn: 37895
 2007-07-05 07:13:32 +00:00
Dan Gohman
9cbc3fb1ab Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
 2007-06-26 00:48:07 +00:00
Owen Anderson
89558a0db6 Fix the build. 
llvm-svn: 37705
 2007-06-22 16:59:54 +00:00
Evan Cheng
c49382e48f Allow predicated immediate ARM to ARM calls. 
llvm-svn: 37659
 2007-06-19 21:05:09 +00:00
Dan Gohman
b60d8a92c9 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
 2007-06-19 01:48:05 +00:00
Evan Cheng
12b3002673 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. 
llvm-svn: 37643
 2007-06-19 01:26:51 +00:00
Evan Cheng
7b433a2954 Mark these instructions clobbersPred. They modify the condition code register. 
llvm-svn: 37468
 2007-06-06 10:17:05 +00:00
Evan Cheng
8a52b80cdf Opcode modifier s comes after condition code. e.g. addlts, not addslt. 
llvm-svn: 37388
 2007-06-01 20:51:29 +00:00
Evan Cheng
c2fec89f4a Make jumptable non-predicable for now. 
llvm-svn: 37381
 2007-06-01 00:56:15 +00:00
Evan Cheng
5df14b3451 For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq. 
llvm-svn: 37349
 2007-05-29 23:32:06 +00:00
Dale Johannesen
f01566b705 Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic. 
llvm-svn: 37271
 2007-05-21 22:42:04 +00:00
Dale Johannesen
8f484d16b0 Add some patterns for PIC PC-relative loads and stores. 
llvm-svn: 37269
 2007-05-21 22:14:33 +00:00
Evan Cheng
e875732104 Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code. 
llvm-svn: 37199
 2007-05-18 01:53:54 +00:00
Evan Cheng
d3f1a259db Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable. 
llvm-svn: 37118
 2007-05-16 20:50:01 +00:00
Evan Cheng
6943cefdcd Conditional branch is not a barrier. 
llvm-svn: 37103
 2007-05-16 07:45:54 +00:00
Evan Cheng
9f0ffdf4b3 Add PredicateOperand to all ARM instructions that have the condition field. 
llvm-svn: 37066
 2007-05-15 01:29:07 +00:00
Evan Cheng
73abcaa525 Switch BCC, MOVCCr, etc. to PredicateOperand. 
llvm-svn: 36948
 2007-05-08 21:08:43 +00:00
Dale Johannesen
0a4acbf6ac change per review 
llvm-svn: 36519
 2007-04-28 00:36:37 +00:00
Dale Johannesen
74feb7979a Prevent Thumb code from generating ARM instructions 
llvm-svn: 36518
 2007-04-27 22:17:18 +00:00
Lauro Ramos Venancio
f385b56870 ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. 
llvm-svn: 36506
 2007-04-27 13:54:47 +00:00
Chris Lattner
87296c2580 dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll 
llvm-svn: 36222
 2007-04-17 22:39:58 +00:00
Lauro Ramos Venancio
7e21418680 - Divides the comparisons in two types: comparisons that only use N and Z 
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).

llvm-svn: 35573
 2007-04-02 01:30:03 +00:00
Lauro Ramos Venancio
8b2e32de5a bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK. 
llvm-svn: 35381
 2007-03-27 16:19:21 +00:00
Lauro Ramos Venancio
11d7d3fcaf bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218
 2007-03-20 17:57:23 +00:00
Evan Cheng
4fec9d7228 Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. 
llvm-svn: 35207
 2007-03-20 08:11:30 +00:00
Evan Cheng
8d374caead Fix naming inconsistencies. 
llvm-svn: 35163
 2007-03-19 07:48:02 +00:00
Evan Cheng
7cbf4c4582 Special LDR instructions to load from non-pc-relative constantpools. These are 
rematerializable. Only used for constant generation for now.

llvm-svn: 35162
 2007-03-19 07:20:03 +00:00
Evan Cheng
389cf8e719 Constant generation instructions are re-materializable. 
llvm-svn: 35161
 2007-03-19 07:09:02 +00:00
Evan Cheng
bf4ca3b491 ARM callseq_end should have a input flag operand so it would be scheduled right after the call. 
llvm-svn: 33832
 2007-02-03 09:11:58 +00:00
Evan Cheng
0f07707270 - Fix codegen for pc relative constant (e.g. JT) in thumb mode: 
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

- In thumb mode, it's not possible to use .set generate a pc relative stub
  address. The stub is ARM code which is in a different section from the thumb
  code. Load the value from a constpool instead.
- Some asm printing clean up.

llvm-svn: 33664
 2007-01-30 20:37:08 +00:00
Jim Laskey
23ed7d2625 Make LABEL a builtin opcode. 
llvm-svn: 33537
 2007-01-26 14:34:52 +00:00
Evan Cheng
5d0be572b5 Code clean up. Use def : pat instead of defining new instructions. 
llvm-svn: 33368
 2007-01-19 20:27:35 +00:00
Evan Cheng
c6e1d453d3 ARM backend contribution from Apple. 
llvm-svn: 33353
 2007-01-19 07:51:42 +00:00
Rafael Espindola
d1baea3471 implement missing compares 
patch by Lauro
bug fixed by me

llvm-svn: 32795
 2006-12-31 18:52:39 +00:00
Lauro Ramos Venancio
7bfe536783 Implement SELECT_CC (f32/f64) for ARM. 
llvm-svn: 32762
 2006-12-28 13:11:14 +00:00
Rafael Espindola
da5b9584ce remove duplicated line 
bug noticed by Lauro

llvm-svn: 32761
 2006-12-28 12:51:40 +00:00
Lauro Ramos Venancio
2cde823f98 This patch defines extloadi1 and fixes an internal compiler error on 
arm.

llvm-svn: 32760
 2006-12-26 19:30:42 +00:00
Rafael Espindola
7c4245c4e3 more general matching of the MVN instruction 
llvm-svn: 32484
 2006-12-12 17:10:13 +00:00
Rafael Espindola
d29cb12dfc use MVN to handle small negative constants 
llvm-svn: 32459
 2006-12-12 01:03:11 +00:00
Rafael Espindola
b8163fd828 add mvn 
llvm-svn: 32454
 2006-12-12 00:37:38 +00:00
Rafael Espindola
514fcabb29 fix truncstorei1 
llvm-svn: 32364
 2006-12-08 18:41:21 +00:00
Rafael Espindola
5daebfdae0 implement load effective address similar to the alpha backend 
remove lea_addri and the now unused memri addressing mode

llvm-svn: 31592
 2006-11-09 13:58:55 +00:00
Rafael Espindola
f7b898d497 initial implementation of addressing mode 2 
TODO: fix lea_addri

llvm-svn: 31552
 2006-11-08 17:07:32 +00:00
Chris Lattner
7c265ad682 remove dead/redundant vars 
llvm-svn: 31435
 2006-11-03 23:48:56 +00:00
Rafael Espindola
a52f709418 implement zextload bool and truncstore bool 
llvm-svn: 31348
 2006-11-01 14:13:27 +00:00
Chris Lattner
71dc932fcb implement uncond branch insertion, mark branches with isBranch. 
llvm-svn: 31160
 2006-10-24 16:47:57 +00:00
Rafael Espindola
70f01d5cc0 implement STRB and STRH 
llvm-svn: 31138
 2006-10-23 20:34:27 +00:00
Rafael Espindola
c08546401b use Pat to implement extloadi8 and extloadi16 
llvm-svn: 31052
 2006-10-19 17:05:03 +00:00
Rafael Espindola
35e92188e0 implement undef 
llvm-svn: 31049
 2006-10-19 13:45:00 +00:00
Rafael Espindola
722266845b implement extloadi8 and extloadi16 
llvm-svn: 31047
 2006-10-19 12:45:04 +00:00
Rafael Espindola
1220d18e11 add blx 
llvm-svn: 31037
 2006-10-18 16:21:43 +00:00
Rafael Espindola
73e8f41749 add isTerminatortto b and bcond 
llvm-svn: 31036
 2006-10-18 16:20:57 +00:00
Rafael Espindola
4e8824608e add the FPUnaryOp and DFPUnaryOp classes 
llvm-svn: 31013
 2006-10-17 20:45:22 +00:00
Rafael Espindola
fe0a9a6fe2 add FABSS and FABSD 
llvm-svn: 31012
 2006-10-17 20:33:13 +00:00
Rafael Espindola
64f93033bc remove extra [] in stores 
llvm-svn: 31008
 2006-10-17 18:29:14 +00:00
Rafael Espindola
47970f96ac initial implementation of addressing mode 5 
llvm-svn: 31002
 2006-10-17 18:04:53 +00:00
Rafael Espindola
31f59f5b94 add FSTD and FSTS 
llvm-svn: 30996
 2006-10-17 13:36:07 +00:00
Rafael Espindola
01400015fc add FCPYS and FCPYD 
llvm-svn: 30995
 2006-10-17 13:13:23 +00:00
Rafael Espindola
a156538e34 add fdivs e fdivd 
llvm-svn: 30988
 2006-10-16 21:50:04 +00:00
Rafael Espindola
4f61431679 expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS 
llvm-svn: 30987
 2006-10-16 21:10:32 +00:00
Rafael Espindola
25fbeb5ec2 define the DFPBinOp class 
llvm-svn: 30981
 2006-10-16 18:39:22 +00:00
Rafael Espindola
57dc40a3a8 add the FPBinOp class 
llvm-svn: 30980
 2006-10-16 18:32:36 +00:00
Rafael Espindola
8a40de94f2 define the Addr1BinOp class 
llvm-svn: 30979
 2006-10-16 18:18:14 +00:00
Rafael Espindola
6554b1014d define the IntBinOp class and use it to implement the multiply instructions 
llvm-svn: 30978
 2006-10-16 17:57:20 +00:00
Rafael Espindola
71ae8c3d4a fix assembly syntax 
llvm-svn: 30977
 2006-10-16 17:38:12 +00:00
Rafael Espindola
d255bfb09b implement LDRB, LDRSB, LDRH and LDRSH 
llvm-svn: 30976
 2006-10-16 17:17:22 +00:00
Rafael Espindola
93359fa883 implement smull and umull 
llvm-svn: 30975
 2006-10-16 16:33:29 +00:00
Rafael Espindola
38c602f658 fix some fp condition codes 
use non trapping comparison instructions

llvm-svn: 30962
 2006-10-14 13:42:53 +00:00
Rafael Espindola
1f85e7a2a1 add FNEGS and FNEGD 
llvm-svn: 30932
 2006-10-13 17:37:35 +00:00
Rafael Espindola
042e61af25 add SBCS and SUBS 
llvm-svn: 30930
 2006-10-13 17:19:20 +00:00
Rafael Espindola
bd50a4d757 implement unordered floating point compares 
llvm-svn: 30928
 2006-10-13 13:14:59 +00:00
Chris Lattner
b7ff3d59f7 mark call adjustments as modifying the SP 
llvm-svn: 30911
 2006-10-12 18:00:26 +00:00
Evan Cheng
ca66f49574 Add properties to ComplexPattern. 
llvm-svn: 30891
 2006-10-11 21:03:53 +00:00
Rafael Espindola
46e7aceb1d uint <-> double conversion 
llvm-svn: 30862
 2006-10-10 20:38:57 +00:00
Rafael Espindola
0112351e9a add fp sub 
llvm-svn: 30859
 2006-10-10 19:35:01 +00:00
Rafael Espindola
27d68a3c22 add double <-> int conversion 
llvm-svn: 30858
 2006-10-10 18:55:14 +00:00
Rafael Espindola
413aa20bc8 compare doubles 
llvm-svn: 30856
 2006-10-10 16:33:47 +00:00
Rafael Espindola
b0719f1374 initial support for fp compares. Unordered compares not implemented yet 
llvm-svn: 30854
 2006-10-10 12:56:00 +00:00
Rafael Espindola
bae07b25d6 add float -> double and double -> float conversion 
llvm-svn: 30835
 2006-10-09 17:50:29 +00:00
Rafael Espindola
f917f096e2 add ADDS and ADCS 
llvm-svn: 30830
 2006-10-09 17:18:28 +00:00
Rafael Espindola
38e9e2e01d implement FUITOS and FUITOD 
llvm-svn: 30803
 2006-10-07 14:24:52 +00:00
Rafael Espindola
90a24709fb implement FLDD 
llvm-svn: 30802
 2006-10-07 14:03:39 +00:00
Rafael Espindola
b8ce0f8bbd implement fadds, faddd, fmuls and fmuld 
llvm-svn: 30801
 2006-10-07 13:46:42 +00:00
Rafael Espindola
a96c205e12 add optional input flag to FMRRD 
llvm-svn: 30774
 2006-10-06 20:33:26 +00:00
Rafael Espindola
f0e4950ef4 implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL 
implement FMDRR
add support for f64 function arguments

llvm-svn: 30754
 2006-10-05 16:48:49 +00:00
Rafael Espindola
b77754ce4d Implement floating point constants 
llvm-svn: 30704
 2006-10-03 17:27:58 +00:00
Rafael Espindola
36c3e0028b fix the names of the 64bit fp register 
initial support for returning 64bit floating point numbers

llvm-svn: 30692
 2006-10-02 19:30:56 +00:00
Rafael Espindola
1b39270c95 add floating point registers 
implement SINT_TO_FP

llvm-svn: 30673
 2006-09-29 21:20:16 +00:00
Rafael Espindola
1a3020bfcf add shifts to addressing mode 1 
llvm-svn: 30291
 2006-09-13 12:09:43 +00:00
Rafael Espindola
7722bae67e implement SRL and MUL 
llvm-svn: 30262
 2006-09-11 19:24:19 +00:00
Rafael Espindola
89ac048c5d partial implementation of the ARM Addressing Mode 1 
llvm-svn: 30252
 2006-09-11 17:25:40 +00:00
Rafael Espindola
20146be5e8 implement shl and sra 
llvm-svn: 30191
 2006-09-08 17:36:23 +00:00