Rafael Espindola
f7b898d497
initial implementation of addressing mode 2
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TODO: fix lea_addri
llvm-svn: 31552
2006-11-08 17:07:32 +00:00
Chris Lattner
7c265ad682
remove dead/redundant vars
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llvm-svn: 31435
2006-11-03 23:48:56 +00:00
Rafael Espindola
a52f709418
implement zextload bool and truncstore bool
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llvm-svn: 31348
2006-11-01 14:13:27 +00:00
Chris Lattner
71dc932fcb
implement uncond branch insertion, mark branches with isBranch.
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llvm-svn: 31160
2006-10-24 16:47:57 +00:00
Rafael Espindola
70f01d5cc0
implement STRB and STRH
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llvm-svn: 31138
2006-10-23 20:34:27 +00:00
Rafael Espindola
c08546401b
use Pat to implement extloadi8 and extloadi16
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llvm-svn: 31052
2006-10-19 17:05:03 +00:00
Rafael Espindola
35e92188e0
implement undef
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llvm-svn: 31049
2006-10-19 13:45:00 +00:00
Rafael Espindola
722266845b
implement extloadi8 and extloadi16
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llvm-svn: 31047
2006-10-19 12:45:04 +00:00
Rafael Espindola
1220d18e11
add blx
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llvm-svn: 31037
2006-10-18 16:21:43 +00:00
Rafael Espindola
73e8f41749
add isTerminatortto b and bcond
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llvm-svn: 31036
2006-10-18 16:20:57 +00:00
Rafael Espindola
4e8824608e
add the FPUnaryOp and DFPUnaryOp classes
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llvm-svn: 31013
2006-10-17 20:45:22 +00:00
Rafael Espindola
fe0a9a6fe2
add FABSS and FABSD
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llvm-svn: 31012
2006-10-17 20:33:13 +00:00
Rafael Espindola
64f93033bc
remove extra [] in stores
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llvm-svn: 31008
2006-10-17 18:29:14 +00:00
Rafael Espindola
47970f96ac
initial implementation of addressing mode 5
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llvm-svn: 31002
2006-10-17 18:04:53 +00:00
Rafael Espindola
31f59f5b94
add FSTD and FSTS
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llvm-svn: 30996
2006-10-17 13:36:07 +00:00
Rafael Espindola
01400015fc
add FCPYS and FCPYD
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llvm-svn: 30995
2006-10-17 13:13:23 +00:00
Rafael Espindola
a156538e34
add fdivs e fdivd
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llvm-svn: 30988
2006-10-16 21:50:04 +00:00
Rafael Espindola
4f61431679
expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS
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llvm-svn: 30987
2006-10-16 21:10:32 +00:00
Rafael Espindola
25fbeb5ec2
define the DFPBinOp class
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llvm-svn: 30981
2006-10-16 18:39:22 +00:00
Rafael Espindola
57dc40a3a8
add the FPBinOp class
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llvm-svn: 30980
2006-10-16 18:32:36 +00:00
Rafael Espindola
8a40de94f2
define the Addr1BinOp class
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llvm-svn: 30979
2006-10-16 18:18:14 +00:00
Rafael Espindola
6554b1014d
define the IntBinOp class and use it to implement the multiply instructions
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llvm-svn: 30978
2006-10-16 17:57:20 +00:00
Rafael Espindola
71ae8c3d4a
fix assembly syntax
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llvm-svn: 30977
2006-10-16 17:38:12 +00:00
Rafael Espindola
d255bfb09b
implement LDRB, LDRSB, LDRH and LDRSH
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llvm-svn: 30976
2006-10-16 17:17:22 +00:00
Rafael Espindola
93359fa883
implement smull and umull
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llvm-svn: 30975
2006-10-16 16:33:29 +00:00
Rafael Espindola
38c602f658
fix some fp condition codes
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use non trapping comparison instructions
llvm-svn: 30962
2006-10-14 13:42:53 +00:00
Rafael Espindola
1f85e7a2a1
add FNEGS and FNEGD
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llvm-svn: 30932
2006-10-13 17:37:35 +00:00
Rafael Espindola
042e61af25
add SBCS and SUBS
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llvm-svn: 30930
2006-10-13 17:19:20 +00:00
Rafael Espindola
bd50a4d757
implement unordered floating point compares
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llvm-svn: 30928
2006-10-13 13:14:59 +00:00
Chris Lattner
b7ff3d59f7
mark call adjustments as modifying the SP
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llvm-svn: 30911
2006-10-12 18:00:26 +00:00
Evan Cheng
ca66f49574
Add properties to ComplexPattern.
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llvm-svn: 30891
2006-10-11 21:03:53 +00:00
Rafael Espindola
46e7aceb1d
uint <-> double conversion
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llvm-svn: 30862
2006-10-10 20:38:57 +00:00
Rafael Espindola
0112351e9a
add fp sub
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llvm-svn: 30859
2006-10-10 19:35:01 +00:00
Rafael Espindola
27d68a3c22
add double <-> int conversion
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llvm-svn: 30858
2006-10-10 18:55:14 +00:00
Rafael Espindola
413aa20bc8
compare doubles
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llvm-svn: 30856
2006-10-10 16:33:47 +00:00
Rafael Espindola
b0719f1374
initial support for fp compares. Unordered compares not implemented yet
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llvm-svn: 30854
2006-10-10 12:56:00 +00:00
Rafael Espindola
bae07b25d6
add float -> double and double -> float conversion
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llvm-svn: 30835
2006-10-09 17:50:29 +00:00
Rafael Espindola
f917f096e2
add ADDS and ADCS
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llvm-svn: 30830
2006-10-09 17:18:28 +00:00
Rafael Espindola
38e9e2e01d
implement FUITOS and FUITOD
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llvm-svn: 30803
2006-10-07 14:24:52 +00:00
Rafael Espindola
90a24709fb
implement FLDD
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llvm-svn: 30802
2006-10-07 14:03:39 +00:00
Rafael Espindola
b8ce0f8bbd
implement fadds, faddd, fmuls and fmuld
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llvm-svn: 30801
2006-10-07 13:46:42 +00:00
Rafael Espindola
a96c205e12
add optional input flag to FMRRD
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llvm-svn: 30774
2006-10-06 20:33:26 +00:00
Rafael Espindola
f0e4950ef4
implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL
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implement FMDRR
add support for f64 function arguments
llvm-svn: 30754
2006-10-05 16:48:49 +00:00
Rafael Espindola
b77754ce4d
Implement floating point constants
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llvm-svn: 30704
2006-10-03 17:27:58 +00:00
Rafael Espindola
36c3e0028b
fix the names of the 64bit fp register
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initial support for returning 64bit floating point numbers
llvm-svn: 30692
2006-10-02 19:30:56 +00:00
Rafael Espindola
1b39270c95
add floating point registers
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implement SINT_TO_FP
llvm-svn: 30673
2006-09-29 21:20:16 +00:00
Rafael Espindola
1a3020bfcf
add shifts to addressing mode 1
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llvm-svn: 30291
2006-09-13 12:09:43 +00:00
Rafael Espindola
7722bae67e
implement SRL and MUL
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llvm-svn: 30262
2006-09-11 19:24:19 +00:00
Rafael Espindola
89ac048c5d
partial implementation of the ARM Addressing Mode 1
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llvm-svn: 30252
2006-09-11 17:25:40 +00:00
Rafael Espindola
20146be5e8
implement shl and sra
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llvm-svn: 30191
2006-09-08 17:36:23 +00:00
Rafael Espindola
9ffcdb8ab7
add the eor (xor) instruction
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llvm-svn: 30189
2006-09-08 16:59:47 +00:00
Rafael Espindola
af1689d5a5
implement unconditional branches
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fix select.ll
llvm-svn: 30186
2006-09-08 12:47:03 +00:00
Rafael Espindola
d9cebd5e48
add the orr instruction
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llvm-svn: 30125
2006-09-06 18:03:12 +00:00
Rafael Espindola
fb63eba81c
add the "eq" condition code
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implement a movcond instruction
llvm-svn: 29857
2006-08-24 17:19:08 +00:00
Rafael Espindola
cf999a6d39
create a generic bcond instruction that has a conditional code argument
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llvm-svn: 29856
2006-08-24 16:13:15 +00:00
Rafael Espindola
9e2a2dfb2d
initial support for branches
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llvm-svn: 29854
2006-08-24 13:45:55 +00:00
Rafael Espindola
474f6c5bf1
initial support for select
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llvm-svn: 29802
2006-08-21 22:00:32 +00:00
Rafael Espindola
13eb38e699
add the and instruction
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llvm-svn: 29793
2006-08-21 13:58:59 +00:00
Rafael Espindola
ff879761c1
add a "load effective address"
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llvm-svn: 29748
2006-08-17 17:09:40 +00:00
Rafael Espindola
b98e92cb78
Declare the callee saved regs
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Remove the hard coded store and load of the link register
Implement ARMFrameInfo
llvm-svn: 29727
2006-08-16 14:43:33 +00:00
Evan Cheng
34a49551f5
CALLSEQ_* produces chain even if that's not needed.
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llvm-svn: 29603
2006-08-11 09:03:33 +00:00
Rafael Espindola
ae2d1c53c7
change the addressing mode of the str instruction to reg+imm
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llvm-svn: 29571
2006-08-08 20:35:03 +00:00
Rafael Espindola
fa94338687
add and use ARMISD::RET_FLAG
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llvm-svn: 29499
2006-08-03 17:02:20 +00:00
Rafael Espindola
719336441f
start comments with #
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move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save
llvm-svn: 29451
2006-08-01 18:53:10 +00:00
Rafael Espindola
9ea0bc742c
implemented sub
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correctly update the stack pointer in the prologue and epilogue
llvm-svn: 29244
2006-07-21 12:26:16 +00:00
Rafael Espindola
ad256854c0
initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)
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llvm-svn: 29175
2006-07-18 17:00:30 +00:00
Rafael Espindola
40073f5767
skeleton of a lowerCall implementation for ARM
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llvm-svn: 29159
2006-07-16 01:02:57 +00:00
Rafael Espindola
fdfaee67f5
add the memri memory operand
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this makes it possible for ldr instructions with non-zero immediate
llvm-svn: 29103
2006-07-11 11:36:48 +00:00
Rafael Espindola
071c83dff0
create the raddr addressing mode that matches any register and the frame index
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use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
Rafael Espindola
14a59f5b6e
initial implementation of ARMRegisterInfo::eliminateFrameIndex
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fixes test/Regression/CodeGen/ARM/ret_arg5.ll
llvm-svn: 28854
2006-06-18 00:08:07 +00:00
Rafael Espindola
1bf57da16e
Expand ret into "CopyToReg;BRIND"
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llvm-svn: 28559
2006-05-30 17:33:19 +00:00
Rafael Espindola
f7c5af4863
On ARM, alignment is in bits
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Add lr as a hard coded operand of bx
llvm-svn: 28494
2006-05-26 10:56:17 +00:00
Rafael Espindola
a0e82ff9be
implement movri
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add a stub LowerFORMAL_ARGUMENTS
llvm-svn: 28388
2006-05-18 21:45:49 +00:00
Rafael Espindola
dd49dfc0df
added a skeleton of the ARM backend
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llvm-svn: 28301
2006-05-14 22:18:28 +00:00