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9077a6f901
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2159 Commits

Author SHA1 Message Date
Johnny Chen
9077a6f901 Added versions of VCGE, VCGT, VCLE, and VCLT NEON instructions which compare to 
(immediate #0) for disassembly only.

A8.6.283, A8.6.285, A8.6.287, A8.6.290

llvm-svn: 96856
 2010-02-23 01:42:58 +00:00
Johnny Chen
b35408e8df Added VCEQ (immediate #0) NEON instruction for disassembly only. 
A8.6.281

llvm-svn: 96838
 2010-02-23 00:33:12 +00:00
Jim Grosbach
c4ab116a90 Updated version of r96634 (which was reverted due to failing 176.gcc and 
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.

llvm-svn: 96822
 2010-02-22 23:10:38 +00:00
Jim Grosbach
4aea6e93c8 Clean up a bit and fix for when SPAdj != 0 
llvm-svn: 96818
 2010-02-22 22:54:55 +00:00
Jim Grosbach
8ae3bf1f1e The predicate index isn't fixed, so scan for it to make sure we get the proper 
value.

Thumb2 uses the tADJCALLSTACK* instructions, and doesn't need t2 versions, so
remove the FIXME entry.

llvm-svn: 96817
 2010-02-22 22:47:46 +00:00
Johnny Chen
0e6c232f0e Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD, 
for disassembly only.

llvm-svn: 96806
 2010-02-22 21:50:40 +00:00
Johnny Chen
bdb1fdccfb Added a bunch of instructions for disassembly only: 
o signed/unsigned add/subtract
o signed/unsigned halving add/subtract
o unsigned sum of absolute difference [and accumulate]
o signed/unsigned saturate
o signed multiply accumulate/subtract [long] dual

llvm-svn: 96795
 2010-02-22 18:50:54 +00:00
Johnny Chen
abea29dc85 Undo r96654. The printing of ARM shift instructions in canonical forms can be 
handled in ARMInstPrinter.cpp.

And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only.

llvm-svn: 96719
 2010-02-21 04:42:01 +00:00
Bob Wilson
df432a30b2 Revert 96634. It causes assertion failures for 126.gcc and 176.gcc in 
the armv6 nightly tests.

llvm-svn: 96691
 2010-02-19 18:59:53 +00:00
Johnny Chen
2a3db5ee3d Added entries for ASR, LSL, LSR, ROR, and RRX so that the disassembler prints 
out the canonical form (A8.6.98) instead of the pseudo-instruction as provided
via MOVs.

DBG_ARM_DISASM=YES llvm-mc -triple=arm-unknown-unknown --disassemble
0xc0 0x00 0xa0 0xe1
Opcode=29 Name=ASR Format=ARM_FORMAT_LDMISCFRM
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	asr	r0, r0, #1

llvm-svn: 96654
 2010-02-19 02:12:06 +00:00
Jim Grosbach
53ef05fa82 Radar 7636153. In the presence of large call frames, it's not sufficient 
for ARM to just check if a function has a FP to determine if it's safe
to simplify the stack adjustment pseudo ops prior to eliminating frame
indices. Allow targets to override the default behavior and does so for ARM
and Thumb2.

llvm-svn: 96634
 2010-02-19 00:16:24 +00:00
Johnny Chen
8d67f1d58d Added LDRD_PRE/POST & STRD_PRE/POST for disassembly only. 
llvm-svn: 96619
 2010-02-18 22:31:18 +00:00
Bob Wilson
84fc0200bd Use NEON vmin/vmax instructions for floating-point selects. 
Radar 7461718.

llvm-svn: 96572
 2010-02-18 06:05:53 +00:00
Johnny Chen
2ef74d0ad2 Added LDRSBT, LDRHT, LDRSHT for disassembly only. And fixed encoding errors 
of AI3ldsbpo, AI3ldhpo, and AI3ldshpo in ARMInstrFormats.td in the process.

llvm-svn: 96565
 2010-02-18 03:27:42 +00:00
Johnny Chen
7f0bf276c2 Added for disassembly only the variants of DMB, DSB, and ISB. 
llvm-svn: 96540
 2010-02-18 00:19:08 +00:00
Bob Wilson
400e59ba21 Remove the NEON N2VSInt instruction class: it's only used in one place and 
since it has no pattern, there's not much point in distinguishing an "N2VS"
class for intrinsics anyway.

llvm-svn: 96525
 2010-02-17 22:42:54 +00:00
Johnny Chen
69bbc8c81b Added CLREX (Clear-Exclusive) for disassembly only. 
A8.6.30

llvm-svn: 96523
 2010-02-17 22:37:58 +00:00
Bob Wilson
ea55421ec2 More cleanup for NEON: 
* Use "S" abbreviation for scalar single FP registers in class and pattern
names, instead of keeping the "D" (for "double") abbreviation and tacking on
an "s" elsewhere in the name.
* Move the scalar single FP register classes and patterns to be more
consistent with other definitions in the file.
* Rename "VNEGf32d" definition to "VNEGfd" for consistency.
* Deleted the N2VDIntsPat pattern; N2VSPat is good enough.

llvm-svn: 96521
 2010-02-17 22:23:11 +00:00
Johnny Chen
6b8a65b0e0 Added RFE for disassembly only. 
B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the
specified address and the following word respectively.

llvm-svn: 96519
 2010-02-17 21:39:10 +00:00
Chris Lattner
f95f8a8c7c add a note, from PR5100 
llvm-svn: 96490
 2010-02-17 18:42:24 +00:00
Johnny Chen
3107d9d344 Added BFI for disassembly only. 
A8.6.18  BFI - Bitfield insert (Encoding A1)

llvm-svn: 96462
 2010-02-17 06:31:48 +00:00
Bob Wilson
532656cffc Wrap lines to 80 columns and generally try to clean up whitespace and 
indentation.  No functional changes.

llvm-svn: 96418
 2010-02-17 00:31:29 +00:00
Bob Wilson
ed0eab5843 Handle tGPR register class in a few more places. This fixes some llvm-gcc 
build failures due to my fix for pr6111.

llvm-svn: 96402
 2010-02-16 22:01:59 +00:00
Johnny Chen
7171461638 Add SMC (Secure Monitor Call) system instruction for disassembly only. 
llvm-svn: 96401
 2010-02-16 21:59:54 +00:00
Jim Grosbach
2acf602672 80 column cleanup 
llvm-svn: 96393
 2010-02-16 21:23:02 +00:00
Jim Grosbach
0c678d7b17 Remove trailing whitespace 
llvm-svn: 96388
 2010-02-16 21:07:46 +00:00
Jim Grosbach
0c8c072ddf Update Thumb2 to not use CarryDefIsUnused or CarryDefIsUsed predicates, but 
to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.

llvm-svn: 96384
 2010-02-16 20:42:29 +00:00
Jim Grosbach
27e3b55717 Remove redundant setting of Defs. CPSR is already marked by the block level set of Defs. 
llvm-svn: 96383
 2010-02-16 20:35:59 +00:00
Jim Grosbach
872d6b21aa First step in eliminating the CarryDefIsUnused and CarryDefIsUsed predicates. 
They won't work with the new ISel mechanism, as Requires predicates are no
longer allowed to reference the node being selected. Moving the predicate to
the patterns instead solves the problem.

This patch handles ARM mode. Thumb2 will follow.

llvm-svn: 96381
 2010-02-16 20:17:57 +00:00
Johnny Chen
900ebc03c5 Added for disassembly the following instructions: 
o Store Return State (SRSW, SRS)
o Load/Store Coprocessor (LDC/STC and friends)
o MSR (immediate)

llvm-svn: 96380
 2010-02-16 20:04:27 +00:00
Bob Wilson
94eef3fc13 Fix pr6111: Avoid using the LR register for the target address of an indirect 
branch in ARM v4 code, since it gets clobbered by the return address before
it is used.  Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.

llvm-svn: 96360
 2010-02-16 17:24:15 +00:00
Bob Wilson
c85ee6018a Put repeated empty pattern into the AQI instruction class. 
We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.

llvm-svn: 96297
 2010-02-15 23:43:47 +00:00
Anton Korobeynikov
ef1862e256 Move TLOF implementations to libCodegen to resolve layering violation. 
llvm-svn: 96288
 2010-02-15 22:37:53 +00:00
Evan Cheng
b5fe25544c Split SelectionDAGISel::IsLegalAndProfitableToFold to 
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.

This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.

llvm-svn: 96255
 2010-02-15 19:41:07 +00:00
David Greene
1efa05ab91 Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96230
 2010-02-15 16:55:24 +00:00
Johnny Chen
475f273d63 Try to factorize the specification of saturating add/subtract operations a bit, 
as suggested by Bob Wilson.

llvm-svn: 96153
 2010-02-14 06:32:20 +00:00
Johnny Chen
f252f7cf0d Add SETEND and BXJ instructions for disassembly only. 
llvm-svn: 96075
 2010-02-13 02:51:09 +00:00
Evan Cheng
6eb7ff5bbf Teach MachineFrameInfo to track maximum alignment while stack objects are being 
created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.

llvm-svn: 96069
 2010-02-13 01:56:41 +00:00
Johnny Chen
727c71d8ac Added a bunch of saturating add/subtract instructions for disassembly only. 
llvm-svn: 96063
 2010-02-13 01:21:01 +00:00
Johnny Chen
d36727232c Add YIELD, WFE, WFI, and SEV instructions for disassembly only. 
Plus add two formats: MiscFrm and ThumbMiscFrm.  Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.

llvm-svn: 96032
 2010-02-12 22:53:19 +00:00
Evan Cheng
c2084b74bb Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case. 
llvm-svn: 96023
 2010-02-12 22:17:21 +00:00
Johnny Chen
a56964de27 Add halfword multiply accumulate long SMLALBB/BT/TB/TT for disassembly only. 
llvm-svn: 96019
 2010-02-12 21:59:23 +00:00
Johnny Chen
0f2837db87 Add SWP (Swap) and SWPB (Swap Byte) for disassembly only. 
llvm-svn: 96010
 2010-02-12 20:48:24 +00:00
Johnny Chen
473d813c5d Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only. 
llvm-svn: 95999
 2010-02-12 18:55:33 +00:00
Johnny Chen
d4e67c4648 Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, 
MRRC, MRRc2.  For disassembly only.

llvm-svn: 95955
 2010-02-12 01:44:23 +00:00
Johnny Chen
6b88fb6575 Added LDRT/LDRBT/STRT/STRBT for disassembly only. 
llvm-svn: 95916
 2010-02-11 20:31:08 +00:00
Johnny Chen
09cc8c09c5 Forgot to also check in this file for vcvt (floating-point <-> fixed-point, VFP). 
Sorry!

llvm-svn: 95892
 2010-02-11 18:47:03 +00:00
Johnny Chen
7c088ab119 Added VCVT (between floating-point and fixed-point, VFP) for disassembly. 
A8.6.297

llvm-svn: 95885
 2010-02-11 18:17:16 +00:00
Johnny Chen
c6ca0de853 Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose. 
llvm-svn: 95884
 2010-02-11 18:12:29 +00:00
Johnny Chen
b1e50a8594 Add pseudo instruction TRAP for disassembly, which is encoded according to A5-21 
as the "Permanently UNDEFINED" instruction.

llvm-svn: 95873
 2010-02-11 17:14:31 +00:00