Chris Lattner
068190eb91
Pass the MachineFunction into EmitJumpTableInfo.
...
llvm-svn: 30742
2006-10-05 03:01:21 +00:00
Chris Lattner
cc21d20348
Use getSectionForFunction.
...
llvm-svn: 30740
2006-10-05 02:49:23 +00:00
Rafael Espindola
b77754ce4d
Implement floating point constants
...
llvm-svn: 30704
2006-10-03 17:27:58 +00:00
Rafael Espindola
36c3e0028b
fix the names of the 64bit fp register
...
initial support for returning 64bit floating point numbers
llvm-svn: 30692
2006-10-02 19:30:56 +00:00
Rafael Espindola
1b39270c95
add floating point registers
...
implement SINT_TO_FP
llvm-svn: 30673
2006-09-29 21:20:16 +00:00
Rafael Espindola
9cfd72a3d1
add a note
...
llvm-svn: 30581
2006-09-22 11:36:17 +00:00
Rafael Espindola
a51ec7153c
more condition codes
...
llvm-svn: 30567
2006-09-21 13:06:26 +00:00
Rafael Espindola
4de4f87be5
if a constant can't be an immediate, add it to the constant pool
...
llvm-svn: 30566
2006-09-21 11:29:52 +00:00
Rafael Espindola
cd52f85028
fix header
...
add comments
untabify
llvm-svn: 30486
2006-09-19 16:41:40 +00:00
Rafael Espindola
6c7627e002
Implement a MachineFunctionPass to fix the mul instruction
...
llvm-svn: 30485
2006-09-19 15:49:25 +00:00
Rafael Espindola
1a3020bfcf
add shifts to addressing mode 1
...
llvm-svn: 30291
2006-09-13 12:09:43 +00:00
Evan Cheng
dd52a60189
Reflects MachineConstantPoolEntry changes.
...
llvm-svn: 30279
2006-09-12 21:04:05 +00:00
Rafael Espindola
7722bae67e
implement SRL and MUL
...
llvm-svn: 30262
2006-09-11 19:24:19 +00:00
Rafael Espindola
d8b1142d79
add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1
...
llvm-svn: 30261
2006-09-11 19:23:32 +00:00
Rafael Espindola
89ac048c5d
partial implementation of the ARM Addressing Mode 1
...
llvm-svn: 30252
2006-09-11 17:25:40 +00:00
Rafael Espindola
a8dd3960f1
call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization
...
llvm-svn: 30246
2006-09-11 12:49:38 +00:00
Anton Korobeynikov
4141c7992e
Removed unnecessary Mangler creation.
...
llvm-svn: 30239
2006-09-10 21:17:03 +00:00
Rafael Espindola
20146be5e8
implement shl and sra
...
llvm-svn: 30191
2006-09-08 17:36:23 +00:00
Rafael Espindola
9ffcdb8ab7
add the eor (xor) instruction
...
llvm-svn: 30189
2006-09-08 16:59:47 +00:00
Rafael Espindola
af1689d5a5
implement unconditional branches
...
fix select.ll
llvm-svn: 30186
2006-09-08 12:47:03 +00:00
Jim Laskey
160a8aa339
1. Remove condition on delete.
...
2. Protect and outline createTargetAsmInfo.
3. Misc. kruft.
llvm-svn: 30169
2006-09-07 23:39:26 +00:00
Jim Laskey
9da25f6119
Make target asm info a property of the target machine.
...
llvm-svn: 30162
2006-09-07 22:06:40 +00:00
Jim Laskey
a64fe8ccf2
Break out target asm info into separate files.
...
llvm-svn: 30161
2006-09-07 22:05:02 +00:00
Jim Laskey
6b86ef852c
Separate target specific asm properties from the asm printers.
...
llvm-svn: 30126
2006-09-06 18:34:40 +00:00
Rafael Espindola
d9cebd5e48
add the orr instruction
...
llvm-svn: 30125
2006-09-06 18:03:12 +00:00
Chris Lattner
9cd4e3429e
Completely eliminate def&use operands. Now a register operand is EITHER a
...
def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
Rafael Espindola
de18749e1f
add support for returning 64bit values
...
llvm-svn: 30103
2006-09-04 19:05:01 +00:00
Chris Lattner
33c9ddc91d
Completely rearchitect the interface between targets and the pass manager.
...
This pass:
1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
output, move all this to common code, and give targets hooks they can
implement.
3. Commonalize the target population stuff between file emission and JIT
emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
paves the way for "fast -O0" stuff in the CFE later, and now LLC could
lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
which is now orthogonal to the fact that JIT'ing is being done.
llvm-svn: 30081
2006-09-04 04:14:57 +00:00
Chris Lattner
fb12884be6
Simplify target construction.
...
llvm-svn: 30070
2006-09-03 18:44:02 +00:00
Rafael Espindola
65007fc49c
add the SETULT condition code
...
llvm-svn: 30067
2006-09-03 13:19:16 +00:00
Rafael Espindola
5c0443c41e
add more condition codes
...
llvm-svn: 30056
2006-09-02 20:24:25 +00:00
Evan Cheng
2db7799507
Select() no longer require Result operand by reference.
...
llvm-svn: 29898
2006-08-26 05:34:46 +00:00
Rafael Espindola
91954ae78f
use @ for comments
...
store LR in an arbitrary stack slot
add support for writing varargs functions
llvm-svn: 29876
2006-08-25 17:55:16 +00:00
Rafael Espindola
fb63eba81c
add the "eq" condition code
...
implement a movcond instruction
llvm-svn: 29857
2006-08-24 17:19:08 +00:00
Rafael Espindola
cf999a6d39
create a generic bcond instruction that has a conditional code argument
...
llvm-svn: 29856
2006-08-24 16:13:15 +00:00
Rafael Espindola
9e2a2dfb2d
initial support for branches
...
llvm-svn: 29854
2006-08-24 13:45:55 +00:00
Rafael Espindola
af0512fc8d
add a README.txt
...
llvm-svn: 29814
2006-08-22 12:22:46 +00:00
Rafael Espindola
474f6c5bf1
initial support for select
...
llvm-svn: 29802
2006-08-21 22:00:32 +00:00
Rafael Espindola
13eb38e699
add the and instruction
...
llvm-svn: 29793
2006-08-21 13:58:59 +00:00
Rafael Espindola
c255c4c434
call computeRegisterProperties
...
llvm-svn: 29780
2006-08-20 01:49:49 +00:00
Chris Lattner
db290f7479
Constify some methods. Patch provided by Anton Vayvod, thanks!
...
llvm-svn: 29756
2006-08-17 22:00:08 +00:00
Rafael Espindola
ff879761c1
add a "load effective address"
...
llvm-svn: 29748
2006-08-17 17:09:40 +00:00
Rafael Espindola
b98e92cb78
Declare the callee saved regs
...
Remove the hard coded store and load of the link register
Implement ARMFrameInfo
llvm-svn: 29727
2006-08-16 14:43:33 +00:00
Rafael Espindola
48bed9023d
select code like
...
ldr rx, [ry, #offset]
llvm-svn: 29664
2006-08-14 19:01:24 +00:00
Chris Lattner
8ca6e82bce
Eliminate use of getNode that takes a vector.
...
llvm-svn: 29614
2006-08-11 17:38:39 +00:00
Chris Lattner
be2765058e
elimiante use of getNode that takes vector of operands.
...
llvm-svn: 29612
2006-08-11 17:22:35 +00:00
Evan Cheng
6053206580
Match tablegen changes.
...
llvm-svn: 29604
2006-08-11 09:08:15 +00:00
Evan Cheng
34a49551f5
CALLSEQ_* produces chain even if that's not needed.
...
llvm-svn: 29603
2006-08-11 09:03:33 +00:00
Rafael Espindola
2ddcf46717
correctly set LocalAreaOffset of TargetFrameInfo
...
llvm-svn: 29589
2006-08-09 17:37:45 +00:00
Rafael Espindola
f0b265b48b
fix the spill code
...
llvm-svn: 29583
2006-08-09 16:41:12 +00:00
Rafael Espindola
9e8af5c486
fix the loading of the link register in emitepilogue
...
llvm-svn: 29580
2006-08-09 13:15:47 +00:00
Rafael Espindola
ae2d1c53c7
change the addressing mode of the str instruction to reg+imm
...
llvm-svn: 29571
2006-08-08 20:35:03 +00:00
Rafael Espindola
7bfbb91f75
initial support for variable number of arguments
...
llvm-svn: 29567
2006-08-08 13:02:29 +00:00
Evan Cheng
d18be1d9c1
Match tablegen isel changes.
...
llvm-svn: 29549
2006-08-07 22:28:20 +00:00
Rafael Espindola
bd29d36be4
use a 'register pressure reducing' scheduler
...
make sure only one move is used in a hello world
llvm-svn: 29520
2006-08-04 12:48:42 +00:00
Rafael Espindola
97918b1d11
Bug fix: always generate a RET_FLAG in LowerRET
...
fixes ret_null.ll and call.ll
llvm-svn: 29519
2006-08-03 22:50:11 +00:00
Rafael Espindola
fa94338687
add and use ARMISD::RET_FLAG
...
llvm-svn: 29499
2006-08-03 17:02:20 +00:00
Rafael Espindola
719336441f
start comments with #
...
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save
llvm-svn: 29451
2006-08-01 18:53:10 +00:00
Rafael Espindola
f11277971f
implement LowerConstantPool and LowerGlobalAddress
...
llvm-svn: 29433
2006-08-01 12:58:43 +00:00
Rafael Espindola
0ea0399411
handle GlobalValue::InternalLinkage in doFinalization
...
llvm-svn: 29417
2006-07-31 20:38:13 +00:00
Evan Cheng
3b5f1c6248
Remove InFlightSet hack. No longer needed.
...
llvm-svn: 29373
2006-07-28 00:47:19 +00:00
Rafael Espindola
c0ede90402
emit global constants
...
llvm-svn: 29344
2006-07-27 11:38:51 +00:00
Rafael Espindola
2919d4ce24
implement function calling of functions with up to 4 arguments
...
llvm-svn: 29274
2006-07-25 20:17:20 +00:00
Rafael Espindola
9ea0bc742c
implemented sub
...
correctly update the stack pointer in the prologue and epilogue
llvm-svn: 29244
2006-07-21 12:26:16 +00:00
Rafael Espindola
ad256854c0
initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)
...
llvm-svn: 29175
2006-07-18 17:00:30 +00:00
Rafael Espindola
40073f5767
skeleton of a lowerCall implementation for ARM
...
llvm-svn: 29159
2006-07-16 01:02:57 +00:00
Rafael Espindola
fdfaee67f5
add the memri memory operand
...
this makes it possible for ldr instructions with non-zero immediate
llvm-svn: 29103
2006-07-11 11:36:48 +00:00
Rafael Espindola
071c83dff0
create the raddr addressing mode that matches any register and the frame index
...
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
Rafael Espindola
f11f34a3d6
handle the "mov reg1, reg2" case in isMoveInstr
...
llvm-svn: 28945
2006-06-27 21:52:45 +00:00
Rafael Espindola
14a59f5b6e
initial implementation of ARMRegisterInfo::eliminateFrameIndex
...
fixes test/Regression/CodeGen/ARM/ret_arg5.ll
llvm-svn: 28854
2006-06-18 00:08:07 +00:00
Chris Lattner
6a9ec7e80e
Don't pass target name into TargetData anymore, it is never used or needed.
...
Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.
llvm-svn: 28830
2006-06-16 18:22:52 +00:00
Rafael Espindola
bcba226a99
lower more then 4 formal arguments. The offset is currently hard coded.
...
implement SelectFrameIndex
llvm-svn: 28751
2006-06-12 12:28:08 +00:00
Rafael Espindola
42375303a6
add R0 to liveout
...
expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch
llvm-svn: 28691
2006-06-05 22:26:14 +00:00
Rafael Espindola
1bf57da16e
Expand ret into "CopyToReg;BRIND"
...
llvm-svn: 28559
2006-05-30 17:33:19 +00:00
Chris Lattner
e1552475d3
Ignore generated files
...
llvm-svn: 28520
2006-05-27 01:23:30 +00:00
Evan Cheng
de0f25081a
Change RET node to include signness information of the return values. i.e.
...
RET chain, value1, sign1, value2, sign2, ...
llvm-svn: 28510
2006-05-26 23:10:12 +00:00
Rafael Espindola
f7c5af4863
On ARM, alignment is in bits
...
Add lr as a hard coded operand of bx
llvm-svn: 28494
2006-05-26 10:56:17 +00:00
Rafael Espindola
31b98f8e04
implement initial version of ARMAsmPrinter::printOperand
...
llvm-svn: 28470
2006-05-25 12:57:06 +00:00
Rafael Espindola
90eec6b0f7
port the ARM backend to use ISD::CALL instead of LowerCallTo
...
llvm-svn: 28469
2006-05-25 11:00:18 +00:00
Evan Cheng
09942d3f8b
Assert if InflightSet is not cleared after instruction selecting a BB.
...
llvm-svn: 28459
2006-05-25 00:24:28 +00:00
Evan Cheng
b040dd86af
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
...
non-deterministic behavior.
llvm-svn: 28454
2006-05-24 20:46:25 +00:00
Chris Lattner
f604017e47
Patches to make the LLVM sources more -pedantic clean. Patch provided
...
by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
Rafael Espindola
bb1e2e2c52
implement minimal versions of
...
ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr
llvm-svn: 28431
2006-05-23 02:48:20 +00:00
Owen Anderson
c6947bf2ce
Make all of the TargetMachine subclasses use the new string TargetData methods.
...
This is part of the on-going work on PR 761.
llvm-svn: 28414
2006-05-20 00:24:56 +00:00
Rafael Espindola
a0e82ff9be
implement movri
...
add a stub LowerFORMAL_ARGUMENTS
llvm-svn: 28388
2006-05-18 21:45:49 +00:00
Evan Cheng
667b133ab9
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
...
llvm-svn: 28378
2006-05-18 00:12:58 +00:00
Evan Cheng
ea24815aa3
Remove PointerType from class Target
...
llvm-svn: 28368
2006-05-17 21:20:27 +00:00
Rafael Espindola
c928207091
add an abort after every assert(0)
...
llvm-svn: 28310
2006-05-15 22:34:39 +00:00
Rafael Espindola
dd49dfc0df
added a skeleton of the ARM backend
...
llvm-svn: 28301
2006-05-14 22:18:28 +00:00