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4081 Commits

Author SHA1 Message Date
Bob Wilson
01593c55a2 Add ARM-specific DAG combining to cast i64 vector element load/stores to f64. 
Type legalization splits up i64 values into pairs of i32 values, which leads
to poor quality code when inserting or extracting i64 vector elements.
If the vector element is loaded or stored, it can be treated as an f64 value
and loaded or stored directly from a VPR register.  Use the pre-legalization
DAG combiner to cast those vector elements to f64 types so that the type
legalizer won't mess them up.  Radar 8755338.

llvm-svn: 122319
 2010-12-21 06:43:19 +00:00
Eric Christopher
72ceef0a74 Arm and thumb call instructions are also in different orders. 
Fixes rdar://8782223

llvm-svn: 122313
 2010-12-21 03:50:43 +00:00
Chris Lattner
65c5243bd6 rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for 
something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310
 2010-12-21 02:38:05 +00:00
Eric Christopher
81ae56b33c If we're not using reg+reg offset we're using reg+imm, set the opcode 
to be the one we want to use. bugpoint reduced testcase is a little large,
I'll see if I can simplify it down more.

Fixes part of rdar://8782207

llvm-svn: 122307
 2010-12-21 02:12:07 +00:00
Bill Wendling
856080c8a1 Fix a copy-pasto. When the tBR_JTr instruction was converted to using the 
tPseudoInst class, its size was changed from "special" to "2 bytes". This is
incorrect because the jump table will no longer be taken into account when
calculating branch offsets.
<rdar://problem/8782216>

llvm-svn: 122303
 2010-12-21 01:57:15 +00:00
Bill Wendling
8c7f90099b Comment cleanups. 
llvm-svn: 122302
 2010-12-21 01:54:40 +00:00
Rafael Espindola
7f9be9e112 Remove the MCObjectFormat class. 
llvm-svn: 122147
 2010-12-18 05:37:28 +00:00
Rafael Espindola
9a4bfd7755 Move some data to the TargetWriter. 
llvm-svn: 122134
 2010-12-18 03:27:34 +00:00
Bill Wendling
9b2ef1c9be r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr to 
ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting
misaligned references to the jump table from an ADR instruction.

There is a test case, but unfortunately it's sensitive to random code changes.

<rdar://problem/8782223>

llvm-svn: 122131
 2010-12-18 02:13:59 +00:00
Bill Wendling
2dde4e38c9 RemoveUnusedCPEntries can change things. Track it. 
llvm-svn: 122129
 2010-12-18 01:53:06 +00:00
Bob Wilson
5f9e78fe20 Rearrange some Neon multiclasses. No functional changes. 
llvm-svn: 122119
 2010-12-18 00:42:58 +00:00
Bob Wilson
776d3f73eb Fix result type of Neon floating-point comparisons against zero. 
The result vector elements are always integers.  Radar 8782191.

llvm-svn: 122112
 2010-12-18 00:04:33 +00:00
Bob Wilson
c000db3584 Add some missing entries in ARMTargetLowering::getTargetNodeName. 
llvm-svn: 122111
 2010-12-18 00:04:26 +00:00
Bill Wendling
c16f9b1ccc During local stack slot allocation, the materializeFrameBaseRegister function 
may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.

Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)

<rdar://problem/8782198>

llvm-svn: 122104
 2010-12-17 23:09:14 +00:00
Bob Wilson
12f2b81599 Avoid report_fatal_error in ARM's PrintAsmOperand method. 
The standard error handling in AsmPrinter::EmitInlineAsm handles this much
better, so just use it.

llvm-svn: 122100
 2010-12-17 23:06:42 +00:00
Jim Grosbach
7ca8ed3d5d If The ARM WriteNopData() gets an unaligned byte count to pad out, fill in with 
a partial value. rdar://8782954

llvm-svn: 122078
 2010-12-17 19:03:02 +00:00
Jim Grosbach
9017f2d179 Add bits 31-28 to the Thumb2 encoding of TBB/TBH. 
llvm-svn: 122076
 2010-12-17 18:42:56 +00:00
Jim Grosbach
e0f65aaf8d Handle 2 and 4 byte data blob fixup values for ARM. 
llvm-svn: 122075
 2010-12-17 18:39:10 +00:00
Rafael Espindola
b9ca29bc1c Stub out explicit MCELFObjectTargetWriter interface. 
llvm-svn: 122067
 2010-12-17 17:45:22 +00:00
Rafael Espindola
38e6fdfd1d Move createELFObjectWriter to its own header. 
llvm-svn: 122064
 2010-12-17 16:59:53 +00:00
Daniel Dunbar
eea7fd1c3e MC/ARM: Use aggressive symbol folding (important for jump tables, for example). 
llvm-svn: 122044
 2010-12-17 06:00:24 +00:00
Daniel Dunbar
6d4a3e98f3 MC/Target: Remove HasScatteredSymbols target hook variable, which has been 
superceded and was effectively dead.

llvm-svn: 122024
 2010-12-17 02:06:08 +00:00
Bob Wilson
125f1a26e0 Use PairDRegs to implement ConcatVectors. No functionality change. 
llvm-svn: 122017
 2010-12-17 01:21:08 +00:00
Jim Grosbach
ce773319e4 Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974 
llvm-svn: 121990
 2010-12-16 19:11:16 +00:00
Daniel Dunbar
2277f06687 MC/Mach-O: Lift some MachObjectWriter arguments into the target specific 
interface.

llvm-svn: 121981
 2010-12-16 17:21:02 +00:00
Daniel Dunbar
5fee4f6862 MC/Mach-O: Stub out explicit MCMachObjectTargetWriter interface. 
llvm-svn: 121973
 2010-12-16 16:09:19 +00:00
Daniel Dunbar
636e690f58 MC/Mach-O: Move createMachObjectWriter into MCMachObjectWriter.h. 
llvm-svn: 121971
 2010-12-16 16:08:33 +00:00
Daniel Dunbar
fc14f1e5f6 MC: Move target specific fixup info descriptors to TargetAsmBackend instead of 
the MCCodeEmitter, which seems like a better organization.
 - Also, cleaned up some magic constants while in the area.

llvm-svn: 121953
 2010-12-16 03:20:06 +00:00
Matt Beaumont-Gay
9b5939da47 Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by Clang 
(see PR4579).

llvm-svn: 121939
 2010-12-16 01:34:26 +00:00
Bill Wendling
c22ad4d7ae Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for 
it. I.e., it was always an immediate value.

llvm-svn: 121932
 2010-12-16 00:50:33 +00:00
Bill Wendling
6ce0807502 Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi 
respectively.

It may be a bug that these opcodes are getting this far into machine code
generation.

llvm-svn: 121931
 2010-12-16 00:49:54 +00:00
Bill Wendling
448cd7f1bb Add encodings for Thumb1 Spill and Restore pseudos. 
llvm-svn: 121929
 2010-12-16 00:38:41 +00:00
Jim Grosbach
84c2b29b58 Thumb1 had two patterns for the same load-from-constant-pool instruction. 
Canonicalize on tLDRpci and remove tLDRcp.

llvm-svn: 121920
 2010-12-15 23:52:36 +00:00
Eric Christopher
339499f8f3 Don't handle -arm-long-calls in fast isel for now. 
llvm-svn: 121919
 2010-12-15 23:47:29 +00:00
Bill Wendling
63ebdf4786 If we're changing the frame register to a physical register other than SP, we 
need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.

llvm-svn: 121915
 2010-12-15 23:32:27 +00:00
Bill Wendling
ed6c88ead9 Whitespace cleanups. 
llvm-svn: 121914
 2010-12-15 23:31:24 +00:00
Bob Wilson
438a9a1367 Add Neon VCVT instructions for f32 <-> f16 conversions. 
Clang is now providing intrinsics for these and so we need to support them
in the backend.  Radar 8068427.

llvm-svn: 121902
 2010-12-15 22:14:12 +00:00
Jim Grosbach
30e7f0d09e Tweak a few pseudo-inst pattern base classes. 
llvm-svn: 121878
 2010-12-15 19:03:16 +00:00
Jim Grosbach
8278d5692a The new t2LEApcrel* pseudo instructions need the size specified. 
rdar://8768390

llvm-svn: 121876
 2010-12-15 18:48:45 +00:00
Owen Anderson
202d654195 Implement cleanups suggested by Daniel. 
llvm-svn: 121875
 2010-12-15 18:48:27 +00:00
Bill Wendling
ab9df10ee5 Add fixups for Thumb LDR/STR instructions. 
llvm-svn: 121858
 2010-12-15 08:51:02 +00:00
Bill Wendling
258739db7e Reapply r121808 now that the missing patterns have been supplied. 
llvm-svn: 121820
 2010-12-15 01:03:19 +00:00
Bill Wendling
2764f25c78 Add some missing patterns now that tLDRB and tLDRH are split into reg and 
immediate versions.

llvm-svn: 121819
 2010-12-15 00:58:57 +00:00
Bill Wendling
ad13b53237 Revert r121808 until I can fix the build. 
llvm-svn: 121815
 2010-12-15 00:04:00 +00:00
Jim Grosbach
386d8fc22c thumb adr fixup needs alignment just like the t2 version. 
llvm-svn: 121812
 2010-12-14 23:47:35 +00:00
Bill Wendling
ab3d22ba7f Comments and cleaning. 
llvm-svn: 121809
 2010-12-14 23:42:48 +00:00
Bill Wendling
2883bbb8c0 Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In 
particular, we want

   ldr r2, [r3]

to be equivalent to

   ldr r2, [r3, #0]

and not

   ldr r2, [r3, r0]

llvm-svn: 121808
 2010-12-14 23:40:49 +00:00
Jim Grosbach
1e943cc60d Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755 
llvm-svn: 121798
 2010-12-14 22:28:03 +00:00
Bill Wendling
213a3d080d Fix comment. 
llvm-svn: 121797
 2010-12-14 22:26:49 +00:00
Bill Wendling
7e589d4753 Multiclassify the LDR/STR encoding patterns. The only functionality difference 
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.

llvm-svn: 121794
 2010-12-14 22:10:49 +00:00