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98fa7ab4d7
Commit Graph

166 Commits

Author SHA1 Message Date
Evan Cheng
98fa7ab4d7 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 
of opcode and number of operands.

llvm-svn: 31947
 2006-11-27 23:37:22 +00:00
Rafael Espindola
5daebfdae0 implement load effective address similar to the alpha backend 
remove lea_addri and the now unused memri addressing mode

llvm-svn: 31592
 2006-11-09 13:58:55 +00:00
Evan Cheng
736a8eb3cd Match tblegen changes. 
llvm-svn: 31571
 2006-11-08 20:34:28 +00:00
Rafael Espindola
f7b898d497 initial implementation of addressing mode 2 
TODO: fix lea_addri

llvm-svn: 31552
 2006-11-08 17:07:32 +00:00
Chris Lattner
7c265ad682 remove dead/redundant vars 
llvm-svn: 31435
 2006-11-03 23:48:56 +00:00
Rafael Espindola
3459a4b85b revert previous patch 
llvm-svn: 31411
 2006-11-03 03:08:28 +00:00
Rafael Espindola
5cfe91aaca add createCFGSimplificationPass to ARMTargetMachine::addInstSelector 
llvm-svn: 31400
 2006-11-03 01:39:25 +00:00
Rafael Espindola
04afe6eb37 move ARMCondCodeToString to ARMAsmPrinter.cpp 
remove unused variables from lowerCall

llvm-svn: 31378
 2006-11-02 15:00:02 +00:00
Rafael Espindola
3ae2b33d17 print null values in bss 
llvm-svn: 31349
 2006-11-01 14:26:44 +00:00
Rafael Espindola
a52f709418 implement zextload bool and truncstore bool 
llvm-svn: 31348
 2006-11-01 14:13:27 +00:00
Rafael Espindola
ba8771a3db add support for calling functions when the caller has variable sized objects 
llvm-svn: 31312
 2006-10-31 13:03:26 +00:00
Evan Cheng
5766dd6455 All targets expand BR_JT for now. 
llvm-svn: 31294
 2006-10-30 08:02:39 +00:00
Rafael Espindola
99322ef58c initial support for frame pointers 
llvm-svn: 31197
 2006-10-26 13:31:26 +00:00
Rafael Espindola
a962656c07 expand ISD::VACOPY 
llvm-svn: 31170
 2006-10-24 20:15:21 +00:00
Rafael Espindola
2259fab5cf fix warning about missing newline at end of file 
llvm-svn: 31162
 2006-10-24 17:07:11 +00:00
Chris Lattner
71dc932fcb implement uncond branch insertion, mark branches with isBranch. 
llvm-svn: 31160
 2006-10-24 16:47:57 +00:00
Rafael Espindola
70f01d5cc0 implement STRB and STRH 
llvm-svn: 31138
 2006-10-23 20:34:27 +00:00
Rafael Espindola
357f151d9d expand ISD::MEMSET 
llvm-svn: 31137
 2006-10-23 20:08:22 +00:00
Reid Spencer
d414793dbc For PR950: 
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.

llvm-svn: 31063
 2006-10-20 07:07:24 +00:00
Rafael Espindola
c08546401b use Pat to implement extloadi8 and extloadi16 
llvm-svn: 31052
 2006-10-19 17:05:03 +00:00
Rafael Espindola
35e92188e0 implement undef 
llvm-svn: 31049
 2006-10-19 13:45:00 +00:00
Rafael Espindola
f7a41f3ddd print common symbols 
llvm-svn: 31048
 2006-10-19 13:30:40 +00:00
Rafael Espindola
722266845b implement extloadi8 and extloadi16 
llvm-svn: 31047
 2006-10-19 12:45:04 +00:00
Rafael Espindola
17544c1c1d expand SIGN_EXTEND_INREG 
llvm-svn: 31046
 2006-10-19 12:06:50 +00:00
Rafael Espindola
6cc20c7950 expand brind so that we don't have to implement jump tables right now 
llvm-svn: 31045
 2006-10-19 10:56:43 +00:00
Rafael Espindola
1220d18e11 add blx 
llvm-svn: 31037
 2006-10-18 16:21:43 +00:00
Rafael Espindola
73e8f41749 add isTerminatortto b and bcond 
llvm-svn: 31036
 2006-10-18 16:20:57 +00:00
Rafael Espindola
80c7461ada implement CallingConv::Fast as CallingConv::C 
llvm-svn: 31034
 2006-10-18 12:03:07 +00:00
Rafael Espindola
58233f9db2 expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM 
llvm-svn: 31014
 2006-10-17 21:05:33 +00:00
Rafael Espindola
4e8824608e add the FPUnaryOp and DFPUnaryOp classes 
llvm-svn: 31013
 2006-10-17 20:45:22 +00:00
Rafael Espindola
fe0a9a6fe2 add FABSS and FABSD 
llvm-svn: 31012
 2006-10-17 20:33:13 +00:00
Rafael Espindola
64f93033bc remove extra [] in stores 
llvm-svn: 31008
 2006-10-17 18:29:14 +00:00
Rafael Espindola
47970f96ac initial implementation of addressing mode 5 
llvm-svn: 31002
 2006-10-17 18:04:53 +00:00
Rafael Espindola
d5a6eaec14 add the immediate to the Offset in eliminateFrameIndex 
llvm-svn: 30998
 2006-10-17 14:34:02 +00:00
Rafael Espindola
31f59f5b94 add FSTD and FSTS 
llvm-svn: 30996
 2006-10-17 13:36:07 +00:00
Rafael Espindola
01400015fc add FCPYS and FCPYD 
llvm-svn: 30995
 2006-10-17 13:13:23 +00:00
Rafael Espindola
a156538e34 add fdivs e fdivd 
llvm-svn: 30988
 2006-10-16 21:50:04 +00:00
Rafael Espindola
4f61431679 expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS 
llvm-svn: 30987
 2006-10-16 21:10:32 +00:00
Rafael Espindola
25fbeb5ec2 define the DFPBinOp class 
llvm-svn: 30981
 2006-10-16 18:39:22 +00:00
Rafael Espindola
57dc40a3a8 add the FPBinOp class 
llvm-svn: 30980
 2006-10-16 18:32:36 +00:00
Rafael Espindola
8a40de94f2 define the Addr1BinOp class 
llvm-svn: 30979
 2006-10-16 18:18:14 +00:00
Rafael Espindola
6554b1014d define the IntBinOp class and use it to implement the multiply instructions 
llvm-svn: 30978
 2006-10-16 17:57:20 +00:00
Rafael Espindola
71ae8c3d4a fix assembly syntax 
llvm-svn: 30977
 2006-10-16 17:38:12 +00:00
Rafael Espindola
d255bfb09b implement LDRB, LDRSB, LDRH and LDRSH 
llvm-svn: 30976
 2006-10-16 17:17:22 +00:00
Rafael Espindola
93359fa883 implement smull and umull 
llvm-svn: 30975
 2006-10-16 16:33:29 +00:00
Rafael Espindola
c426cede28 expand ISD::BRCOND 
llvm-svn: 30963
 2006-10-14 17:59:54 +00:00
Rafael Espindola
38c602f658 fix some fp condition codes 
use non trapping comparison instructions

llvm-svn: 30962
 2006-10-14 13:42:53 +00:00
Evan Cheng
fe5bb5dbe6 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
llvm-svn: 30945
 2006-10-13 21:14:26 +00:00
Rafael Espindola
1f85e7a2a1 add FNEGS and FNEGD 
llvm-svn: 30932
 2006-10-13 17:37:35 +00:00
Rafael Espindola
042e61af25 add SBCS and SUBS 
llvm-svn: 30930
 2006-10-13 17:19:20 +00:00