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Commit Graph

125883 Commits

Author SHA1 Message Date
Sanjay Patel
9ac7e74796 [LibCallSimplifier] use instruction-level fast-math-flags to transform sqrt calls
This is a continuation of adding FMF to call instructions:
http://reviews.llvm.org/rL255555

The intent of the patch is to preserve the current behavior of the transform except
that we use the sqrt instruction's 'fast' attribute as a trigger rather than the
function-level attribute.

But this raises a bug noted by the new FIXME comment.

In order to do this transform:
sqrt((x * x) * y) ---> fabs(x) * sqrt(y)

...we need all of the sqrt, the first fmul, and the second fmul to be 'fast'. 
If any of those ops is strict, we should bail out.

Differential Revision: http://reviews.llvm.org/D15937

llvm-svn: 257400
2016-01-11 22:34:19 +00:00
Sanjay Patel
61d0be65b2 getParent()->getParent() == getFunction() and clang-format ; NFC
llvm-svn: 257399
2016-01-11 22:24:35 +00:00
Sanjay Patel
3bc0384514 don't repeat function names in comments; NFC
llvm-svn: 257396
2016-01-11 22:14:42 +00:00
Rafael Espindola
59ed1d964f Add a missing error handling to llvm-lto.
llvm-svn: 257395
2016-01-11 22:08:22 +00:00
Dan Gohman
a3c4472bce [WebAssembly] Reorganize address offset folding.
Always expect tglobaladdr and texternalsym to be wrapped in
WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so
that it can special-case global addresses, as they can be folded in more
cases.

Unfortunately this doesn't enable any new optimizations yet due to
SelectionDAG limitations. I'll be submitting changes to the SelectionDAG
infrastructure, along with tests, in a separate patch.

llvm-svn: 257394
2016-01-11 22:05:44 +00:00
Matt Arsenault
e2033b4ea1 AMDGPU: Implement {{s|u}}int_to_fp i64 -> f32
The old lowering for uint_to_fp failed opencl conformance.
It might be OK for fast math mode, but I'm not sure.

llvm-svn: 257393
2016-01-11 22:01:48 +00:00
Lang Hames
d0ddff1135 XFAIL the LLI remote JIT tests on Win32.
llvm-svn: 257391
2016-01-11 21:41:34 +00:00
Teresa Johnson
c5417f559e Split resolveCycles(bool AllowTemps) into two interfaces and document
Address review feedback from r255909.

Move body of resolveCycles(bool AllowTemps) to
resolveRecursivelyImpl(bool AllowTemps). Revert resolveCycles back
to asserting on temps, and add new resolveNonTemporaries interface
to invoke the new implementation with AllowTemps=true. Document
the differences between these interfaces, specifically the effect
on RAUW support and uniquing. Call appropriate interface from
ValueMapper.

llvm-svn: 257389
2016-01-11 21:37:41 +00:00
Pete Cooper
6968094852 BumpPtrAllocator::Reset should also poison the first slab which doesn't get deallocated.
When asan is enabled, we poison slabs as we allocate them, and only unpoison the pieces
we need from the slab.

However, in Reset, we were failing to reset the state of the slab back to being poisoned.

Patch by b17 c0de.

llvm-svn: 257388
2016-01-11 21:28:03 +00:00
Matt Arsenault
032b8e5371 AMDGPU: Cleanup udiv test
llvm-svn: 257387
2016-01-11 21:18:40 +00:00
Matt Arsenault
f903e8d6a9 AMDGPU: Fix crash with dispatch.ptr intrinsic with non-HSA target
It might be better to let this be a select failure instead.

llvm-svn: 257386
2016-01-11 21:18:33 +00:00
Ahmed Bougacha
902e3a5e93 [X86] Add AVX512 testcase for r248965/PR24512.
llvm-svn: 257385
2016-01-11 21:16:21 +00:00
Reid Kleckner
e2255be948 Revert "[Windows] Simplify assertion code. NFC."
This reverts commit r254363.

load64BitDebugHelp() has the side effect of loading dbghelp and setting
globals. It should be called in no-asserts builds as well as debug
builds.

llvm_unreachable is also not appropriate here, since we actually want to
return if dbghelp couldn't be loaded in a non-asserts build.

llvm-svn: 257384
2016-01-11 21:07:48 +00:00
Lang Hames
cf27cdf11f [ORC] Add explicit move construction/assignment to
OrcRemoteTargetClient::ObjectAllocs.

More MSVC bot appeasement.

llvm-svn: 257382
2016-01-11 20:52:33 +00:00
Reid Kleckner
cbda36e6e5 Update the VS getting started docs to reflect the current state of support
llvm-svn: 257381
2016-01-11 20:51:57 +00:00
Reid Kleckner
98639cde79 Use ::GetVersionEx directly rather than the Win8.1 SDK helpers
This removes ifdefs and fixes the build for users of the Win8.0 SDK,
which I happen to be. Upgrading is not hard, but executing the same code
everywhere seems better.

llvm-svn: 257379
2016-01-11 20:35:45 +00:00
Lang Hames
fcaa6caed5 [ORC] More MSVC error wrangling.
llvm-svn: 257377
2016-01-11 20:25:25 +00:00
Dimitry Andric
f8ee8c016c Ensure -mcpu=xscale works for arm targets, after rL252903 and rL252904
After these revisions, for arm targets, the -mcpu=xscale option caused
an error: "the clang compiler does not support '-mcpu=xscale'".  Adding
"v5e" as a SUB_ARCH in ARMTargetParser.def helps.

Submitted by: Andrew Turner
Differential Revision: http://reviews.llvm.org/D16043

llvm-svn: 257376
2016-01-11 20:12:53 +00:00
Adhemerval Zanella
cb9b91e743 [sanitizer] [msan] Fix origin store of array types
This patch fixes the memory sanitizer origin store instrumentation for
array types.  This can be triggered by cases where frontend lowers
function return to array type instead of aggregation.

For instance, the C code:

--
struct mypair {
 int64_t x;
 int y;
};

mypair my_make_pair(int64_t x, int y)  {
 mypair p;
 p.x = x;
 p.y = y;
 return p;
}

int foo (int p)
{
  mypair z = my_make_pair(p, 0);
  return z.y + z.x;
}
--

It will be lowered with target set to aarch64-linux and -O0 to:

--
[...]
define i32 @_Z3fooi(i32 %p) #0 {
[...]
%call = call [2 x i64] @_Z12my_make_pairxi(i64 %conv, i32 0)
%1 = bitcast %struct.mypair* %z to [2 x i64]*
store [2 x i64] %call, [2 x i64]* %1, align 8
[...]
--

The origin store will emit a 'icmp' to test each store value again the
TLS origin array.  However since 'icmp' does not support ArrayType the
memory instrumentation phase will bail out with an error.

This patch change it by using the same strategy used for struct type on
array.

It fixes the 'test/msan/insertvalue_origin.cc' for aarch64 (the -O0 case).

llvm-svn: 257375
2016-01-11 19:55:27 +00:00
Lang Hames
789b9a4918 [Orc] Fix missing return.
llvm-svn: 257373
2016-01-11 19:40:25 +00:00
Lang Hames
9f11bb5b33 [Orc] Add explicit move construction/assignment to RCMemoryManager.
Yet another attempt to pacify MSVC.

llvm-svn: 257372
2016-01-11 19:39:49 +00:00
David Blaikie
e31830eba8 Fix some GCC 4.7 issues with the new Orc remote JIT support
I'm still seeing GCC ICE locally, but figured I'd throw this at the wall
& see if it sticks for the bots at least. Will continue investigating
the ICE in any case.

llvm-svn: 257367
2016-01-11 19:26:01 +00:00
Chen Li
a83ca40c36 Code refactoring for commit r257278.
llvm-svn: 257366
2016-01-11 19:20:53 +00:00
Chad Rosier
300eea4596 [NFC] Fix whitespace.
llvm-svn: 257365
2016-01-11 19:17:36 +00:00
Lang Hames
fed2407e06 [ORC] Explicitly delete copy constructors for RCMemoryManager::Alloc.
More MSVC bot appeasement.

llvm-svn: 257364
2016-01-11 19:05:45 +00:00
Lang Hames
4857d16b5d [Orc] Include <system_error> in OrcTargetClient.
Another shot at appeasing the clang-x86_64-ubuntu-gdb-75 builder.

llvm-svn: 257362
2016-01-11 18:48:37 +00:00
Lang Hames
380df1aad3 lli/ChildTarget now depends on OrcJIT. Add that component to the Makefile.
llvm-svn: 257360
2016-01-11 17:44:07 +00:00
Lang Hames
c75302cb86 Remove the remote-JIT small code model tests for now. They're causing
intermittent XPASSes on some builders.

These can be reinstated when we have proper support for small-code model in
the JIT.

llvm-svn: 257359
2016-01-11 17:38:25 +00:00
Lang Hames
a872375ec6 [Orc] More explicit move construction/assignment to appease MSVC.
llvm-svn: 257358
2016-01-11 17:32:03 +00:00
Lang Hames
4df39c1222 XFAIL the remote small code model tests on x86. Small code model is not properly
supported, and only worked previously because we weren't really running them
out-of-process.

llvm-svn: 257355
2016-01-11 17:09:58 +00:00
Matt Arsenault
a8ec54d557 AMDGPU: int_to_fp test cleanups
llvm-svn: 257354
2016-01-11 17:02:10 +00:00
Matt Arsenault
c485a8dc2b AMDGPU: Fix ctlz combine for sub 32-bit types
llvm-svn: 257353
2016-01-11 17:02:06 +00:00
Matt Arsenault
b88ff2e112 AMDGPU: Pattern match ffbh pattern to instruction.
The hardware instruction's output on 0 is -1 rather than 32.
Eliminate a test and select to -1. This removes an extra instruction
from the compatability function with HSAIL's firstbit instruction.

llvm-svn: 257352
2016-01-11 17:02:00 +00:00
Lang Hames
6195badb41 [LLI] Remove dependence on RemoteTarget.cpp from ChildTarget's Makefile.
RemoteTarget.cpp was removed in r257343.

llvm-svn: 257351
2016-01-11 17:00:31 +00:00
Lang Hames
eff773999e [ORC] Pacify MSVC by adding explicit move construction/assignment to
OrcRemoteTargetServer::Allocator.

llvm-svn: 257350
2016-01-11 16:56:24 +00:00
Lang Hames
1753332c86 [ORC] Change 'auto' to 'std::error_code' to try to coax GCC builder into
providing a more helpful error diagnostic.

llvm-svn: 257349
2016-01-11 16:52:11 +00:00
Matt Arsenault
9caa943926 AMDGPU: Custom lower i64 ctlz
llvm-svn: 257348
2016-01-11 16:50:29 +00:00
Matt Arsenault
cb3a3bebdf Mips: Remove lowerSELECT_CC
This is the same as the default expansion.

llvm-svn: 257346
2016-01-11 16:44:48 +00:00
Matt Arsenault
c04b46aa04 LegalizeDAG: Expand ctlz with ctlz_zero_undef if legal
llvm-svn: 257345
2016-01-11 16:37:46 +00:00
Matt Arsenault
c2a350a74a AMDGPU: Remove dead target dag combine
llvm-svn: 257344
2016-01-11 16:37:40 +00:00
Lang Hames
0c18396b3b [LLI] Replace the LLI remote-JIT support with the new ORC remote-JIT components.
The new ORC remote-JITing support provides a superset of the old code's
functionality, so we can replace the old stuff. As a bonus, a couple of
previously XFAILed tests have started passing.

llvm-svn: 257343
2016-01-11 16:35:55 +00:00
Silviu Baranga
90360019af Revert r257164 - it has caused spec2k6 failures in LTO mode
llvm-svn: 257340
2016-01-11 16:19:38 +00:00
Daniel Sanders
f78b9ea9f0 [mips] Never select JAL for calls to an absolute immediate address.
Summary:
It actually takes an offset into the current PC-region.

This fixes the 'expr' command in lldb.

Reviewers: vkalintiris, jaydeep, bhushan

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D16054

llvm-svn: 257339
2016-01-11 15:57:46 +00:00
Krzysztof Parzyszek
e8a7ebcd1a [Hexagon] Add check for nullptr in getFixupNoBits
llvm-svn: 257338
2016-01-11 15:51:53 +00:00
Krzysztof Parzyszek
c902c4f38a [Hexagon] Add implicit uses of GP to GP-relative loads and stores
llvm-svn: 257337
2016-01-11 15:49:58 +00:00
Krzysztof Parzyszek
438a5799b1 [Hexagon] Mark D14 and GP as reserved registers
llvm-svn: 257336
2016-01-11 15:47:41 +00:00
Alexey Bataev
abddd2d70e [X86] Reduce complexity of the LEA optimization pass, by Andrey Turetsky.
In the OptimizeLEA pass keep instructions' positions in the basic block saved and use them for calculation of the distance between two instructions instead of std::distance. This reduces complexity of the pass from O(n^3) to O(n^2) and thus the compile time.
Differential Revision: http://reviews.llvm.org/D15692

llvm-svn: 257328
2016-01-11 11:52:29 +00:00
Junmo Park
7569708aa2 [BranchFolding] Set correct mem refs (2nd try)
This is a recommit of r257253 which was reverted in r257270.
Previous testcase can make failure on some targets due to using opt with O3 option.

Original Summary:
Merge MBBICommon and MBBI's MMOs.

Differential Revision: http://reviews.llvm.org/D15990

llvm-svn: 257317
2016-01-11 07:15:38 +00:00
Lang Hames
10ff8aebeb [ORC] Move ORC RPC helper classes that rely on partial specialization into a
non-template base class.

Hopefully this should fix the issues with the windows bots arrising from
r257305.

llvm-svn: 257316
2016-01-11 05:44:39 +00:00
Craig Topper
8bf4b9d67a [TableGen] Allow asm writer to use up to 3 OpInfo tables instead of 2. This allows x86 to use 56 total bits made up of a 32-bit, 16-bit, and 8-bit table. Previously we were using 64 total bits.
This saves 14K from the x86 table size. And saves space on other targets as well.

llvm-svn: 257315
2016-01-11 05:13:41 +00:00