Jim Grosbach
a3eeee8a91
ARM refactor more NEON VLD/VST instructions to use composite physregs
...
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
llvm-svn: 152150
2012-03-06 22:01:44 +00:00
Kevin Enderby
64d11852dd
Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.
...
llvm-svn: 152127
2012-03-06 18:33:12 +00:00
Jim Grosbach
a6b09b4691
ARM Refactor VLD/VST spaced pair instructions.
...
Use the new composite physical registers.
llvm-svn: 152063
2012-03-05 21:43:40 +00:00
Jim Grosbach
fdfaed95ae
ARM refactor away a bunch of VLD/VST pseudo instructions.
...
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
llvm-svn: 152045
2012-03-05 19:33:30 +00:00
Derek Schuff
db82ff1e09
Make MemoryObject accessor members const again
...
llvm-svn: 151687
2012-02-29 01:09:06 +00:00
Kevin Enderby
91d284c5de
Fix the symbolic operand added for the C disassmbler API for the ARM bl
...
thumb instruction. The PC adjustment is +4 in Thumb mode and +8 in ARM mode.
llvm-svn: 151530
2012-02-27 18:15:15 +00:00
Kevin Enderby
4e089c2b5b
Updated the llvm-mc disassembler C API to support for the X86 target.
...
rdar://10873652
As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back. If there is a
getOpInfo call back that is tried first and then if that gets no information
then the SymbolLookUp is called. I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo. And also don't use any
values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683
For the X86 target also fixed bugs so the annotations get printed.
Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions. rdar://10878166
llvm-svn: 151267
2012-02-23 18:18:17 +00:00
Jia Liu
b077b6085d
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
...
llvm-svn: 150878
2012-02-18 12:03:15 +00:00
Benjamin Kramer
44e872829d
Make the EDis tables const.
...
llvm-svn: 150304
2012-02-11 14:51:07 +00:00
Craig Topper
11bcb12b5e
Convert assert(0) to llvm_unreachable
...
llvm-svn: 149961
2012-02-07 02:50:20 +00:00
Derek Schuff
f522835510
Enable streaming of bitcode
...
This CL delays reading of function bodies from initial parse until
materialization, allowing overlap of compilation with bitcode download.
llvm-svn: 149918
2012-02-06 22:30:29 +00:00
David Blaikie
06ecc99a56
More dead code removal (using -Wunreachable-code)
...
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
Jim Grosbach
b79d2a8f50
ARM NEON VTBL/VTBX assembly parsing and encoding.
...
llvm-svn: 146691
2011-12-15 22:27:11 +00:00
Jim Grosbach
2dac770227
ARM NEON refactor VST2 w/ writeback instructions.
...
In addition to improving the representation, this adds support for assembly
parsing of these instructions.
llvm-svn: 146588
2011-12-14 21:32:11 +00:00
Jim Grosbach
44829ab9d2
ARM NEON VST2 assembly parsing and encoding.
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Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
Daniel Dunbar
30d6a45140
LLVMBuild: Remove trailing newline, which irked me.
...
llvm-svn: 146409
2011-12-12 19:48:00 +00:00
Jim Grosbach
489e81da30
ARM assembly parsing and encoding for VLD2 with writeback.
...
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
llvm-svn: 146278
2011-12-09 21:28:25 +00:00
Matt Beaumont-Gay
07afe588d4
Remove unused variable
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llvm-svn: 145517
2011-11-30 19:53:11 +00:00
Jim Grosbach
6b2f6389cc
ARM parsing for VLD1 all lanes, with writeback.
...
llvm-svn: 145510
2011-11-30 19:35:44 +00:00
Jim Grosbach
538759efa7
ARM assembly parsing and encoding for four-register VST1.
...
llvm-svn: 145450
2011-11-29 22:58:48 +00:00
Jim Grosbach
5418e87582
ARM assembly parsing and encoding for three-register VST1.
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llvm-svn: 145442
2011-11-29 22:38:04 +00:00
Daniel Dunbar
4e00f5f8fd
build/CMake: Finish removal of add_llvm_library_dependencies.
...
llvm-svn: 145420
2011-11-29 19:25:30 +00:00
Owen Anderson
f71db061ba
Fix a misplaced paren bug.
...
llvm-svn: 144692
2011-11-15 20:30:41 +00:00
Owen Anderson
35f049f1fb
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
...
llvm-svn: 144683
2011-11-15 19:55:00 +00:00
Daniel Dunbar
73d41b0f03
build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies.
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- The hope is that we have a tool/test to verify these are accurate (and tight) soon.
llvm-svn: 144444
2011-11-12 02:10:57 +00:00
Jim Grosbach
312b583950
Re-apply 144430, this time with the associated isel and disassmbler bits.
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Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'
llvm-svn: 144437
2011-11-12 00:31:53 +00:00
Benjamin Kramer
e5295a772e
Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
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llvm-svn: 144384
2011-11-11 12:39:41 +00:00
Daniel Dunbar
3760ebeebb
build: Add initial cut at LLVMBuild.txt files.
...
llvm-svn: 143634
2011-11-03 18:53:17 +00:00
Owen Anderson
66d22d36d2
The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552.
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llvm-svn: 143553
2011-11-02 17:46:18 +00:00
Owen Anderson
9b966e47e2
Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case.
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llvm-svn: 143552
2011-11-02 17:41:23 +00:00
Owen Anderson
0d69f6aa51
Fix disassembly of some VST1 instructions.
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llvm-svn: 143507
2011-11-01 22:18:13 +00:00
Jim Grosbach
76dd8a9702
ARM VST1 w/ writeback assembly parsing and encoding.
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llvm-svn: 143369
2011-10-31 21:50:31 +00:00
Owen Anderson
d7700cb13f
More not-crashing NEON disassembly updates for the vld refactoring.
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llvm-svn: 143351
2011-10-31 17:17:32 +00:00
Owen Anderson
3dd6c949a5
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
...
llvm-svn: 143208
2011-10-28 18:02:13 +00:00
Owen Anderson
d35df0aaeb
Add some NEON stores to the VLD decoding hook that were accidentally omitted previously.
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llvm-svn: 143162
2011-10-27 22:53:10 +00:00
Jim Grosbach
fabe0f2f0b
ARM assembly parsing and encoding for VLD1 with writeback.
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Four entry register lists.
llvm-svn: 142882
2011-10-25 00:14:01 +00:00
Jim Grosbach
688186941f
ARM assembly parsing and encoding for VLD1 w/ writeback.
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Three entry register list variation.
llvm-svn: 142876
2011-10-24 23:26:05 +00:00
Jim Grosbach
4a6508dd4e
ARM refactor am6offset usage for VLD1.
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Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
llvm-svn: 142853
2011-10-24 21:45:13 +00:00
Owen Anderson
b0e09258e7
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
...
llvm-svn: 142817
2011-10-24 18:04:29 +00:00
Benjamin Kramer
03065133c3
Move various generated tables into read-only memory, fixing up const correctness along the way.
...
llvm-svn: 142726
2011-10-22 16:50:00 +00:00
Jim Grosbach
d964cf8939
Assembly parsing for 4-register sequential variant of VLD2.
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llvm-svn: 142704
2011-10-21 23:58:57 +00:00
Jim Grosbach
a6e536367e
Assembly parsing for 2-register sequential variant of VLD2.
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llvm-svn: 142691
2011-10-21 22:21:10 +00:00
Jim Grosbach
68dfc88f95
Assembly parsing for 4-register variant of VLD1.
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llvm-svn: 142682
2011-10-21 20:35:01 +00:00
Jim Grosbach
2c1ca90ac9
Assembly parsing for 3-register variant of VLD1.
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llvm-svn: 142675
2011-10-21 20:02:19 +00:00
Jim Grosbach
6bb38d0e97
ARM VLD parsing and encoding.
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Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
Jim Grosbach
547dde4517
Tidy up. Trailing whitespace.
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llvm-svn: 142591
2011-10-20 17:28:20 +00:00
Chad Rosier
8247682aba
Removed set, but unused variables.
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Patch by Joe Abbey <jabbey@arxan.com>.
llvm-svn: 142223
2011-10-17 18:48:30 +00:00
Richard Trieu
5370a1ef01
Fix a non-firing assert. Change:
...
assert("bad SymbolicOp.VariantKind");
To:
assert(0 && "bad SymbolicOp.VariantKind");
llvm-svn: 142000
2011-10-14 20:50:26 +00:00
Eli Friedman
94373219c3
Fix undefined shift. Patch by Ahmed Charles.
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llvm-svn: 141914
2011-10-13 23:36:06 +00:00
Owen Anderson
9f90e2252c
SETEND is not allowed in an IT block.
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llvm-svn: 141874
2011-10-13 17:58:39 +00:00
Jim Grosbach
b9dddb0d13
ARM addrmode5 represents the 'U' bit of the encoding backwards.
...
The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.
llvm-svn: 141819
2011-10-12 21:59:02 +00:00
Jim Grosbach
422576b6e8
Thumb2 assembly parsing and encoding for LDC/STC.
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llvm-svn: 141811
2011-10-12 20:54:17 +00:00
Jim Grosbach
71dbc175ce
addrmode2 is gone from these, so no need for the reg0 operand.
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llvm-svn: 141794
2011-10-12 18:11:24 +00:00
Owen Anderson
dc57f29896
Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.
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llvm-svn: 141339
2011-10-06 23:33:11 +00:00
Kevin Enderby
5a09a8db55
Adding back support for printing operands symbolically to ARM's new disassembler
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using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
llvm-svn: 141129
2011-10-04 22:44:48 +00:00
Jim Grosbach
d94ffffc87
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
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Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
llvm-svn: 140834
2011-09-30 00:50:06 +00:00
Owen Anderson
7742c81cde
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
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llvm-svn: 140560
2011-09-26 21:06:22 +00:00
Owen Anderson
071eb7580a
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
...
llvm-svn: 140415
2011-09-23 21:07:25 +00:00
Owen Anderson
a2cfbf33af
Revert r140412. This affects more instructions than intended.
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llvm-svn: 140413
2011-09-23 21:02:01 +00:00
Owen Anderson
227b8c74fb
Thumb2 register-shifted-register loads cannot target the PC or the SP.
...
llvm-svn: 140412
2011-09-23 21:00:32 +00:00
Owen Anderson
791a17f64a
tMOVSr is not allowed in an IT block either.
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llvm-svn: 140104
2011-09-19 23:57:20 +00:00
Owen Anderson
3920c43055
CPS instructions are UNPREDICTABLE inside IT blocks.
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llvm-svn: 140102
2011-09-19 23:47:10 +00:00
Owen Anderson
25138827ef
Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle.
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llvm-svn: 140079
2011-09-19 22:34:23 +00:00
Jim Grosbach
6da9e6b23d
Thumb2 assembly parsing and encoding for TBB/TBH.
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llvm-svn: 140078
2011-09-19 22:21:13 +00:00
Owen Anderson
b843f3625d
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
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llvm-svn: 140032
2011-09-19 18:07:10 +00:00
Owen Anderson
c1f638997d
Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB.
...
llvm-svn: 139972
2011-09-16 23:30:01 +00:00
Owen Anderson
aec67a3ea1
Fix bitfield decoding based on Eli's feedback.
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llvm-svn: 139969
2011-09-16 23:04:48 +00:00
Owen Anderson
5d23e1e5b4
Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.
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llvm-svn: 139965
2011-09-16 22:42:36 +00:00
Owen Anderson
eae0eee720
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
...
llvm-svn: 139964
2011-09-16 22:29:48 +00:00
Owen Anderson
5804085f26
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
...
llvm-svn: 139943
2011-09-16 21:08:33 +00:00
Owen Anderson
e54c4beb5a
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
...
llvm-svn: 139876
2011-09-15 23:38:46 +00:00
Owen Anderson
04d8803035
Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.
...
llvm-svn: 139736
2011-09-14 21:06:21 +00:00
Owen Anderson
05ef2c122d
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
...
llvm-svn: 139522
2011-09-12 18:56:30 +00:00
Owen Anderson
9cd21ce8c9
LDM writeback is not allowed if Rn is in the target register list.
...
llvm-svn: 139432
2011-09-09 23:13:33 +00:00
Owen Anderson
dbe77fc5a1
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
...
llvm-svn: 139422
2011-09-09 22:24:36 +00:00
Owen Anderson
a7838cb723
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
...
llvm-svn: 139415
2011-09-09 21:48:23 +00:00
Jim Grosbach
eb2d668899
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
...
llvm-svn: 139381
2011-09-09 18:37:27 +00:00
Owen Anderson
99ad1a853e
All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.
...
llvm-svn: 139329
2011-09-08 22:48:37 +00:00
Owen Anderson
d7127e0c27
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
...
llvm-svn: 139328
2011-09-08 22:42:49 +00:00
Jim Grosbach
9f150bfedf
Thumb2 assembly parsing and encoding for LDRD(immediate).
...
Refactor operand handling for STRD as well. Tests for that forthcoming.
llvm-svn: 139322
2011-09-08 22:07:06 +00:00
Owen Anderson
4a5ec6836f
Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.
...
llvm-svn: 139268
2011-09-08 00:11:18 +00:00
Owen Anderson
26467730c1
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
...
llvm-svn: 139256
2011-09-07 21:10:42 +00:00
James Molloy
ac057f13a5
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
...
llvm-svn: 139250
2011-09-07 19:42:28 +00:00
Owen Anderson
4106b9fb31
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
...
llvm-svn: 139240
2011-09-07 17:55:19 +00:00
James Molloy
f781d3d8e9
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
...
llvm-svn: 139237
2011-09-07 17:24:38 +00:00
Owen Anderson
a319b9901d
Merge the ARM disassembler header into the implementation file, since it is not externally exposed.
...
llvm-svn: 138982
2011-09-01 23:35:51 +00:00
Owen Anderson
c4ec9cc45f
Fix 80 columns violations.
...
llvm-svn: 138980
2011-09-01 23:23:50 +00:00
James Molloy
4a63186421
Fix up r137380 based on post-commit review by Jim Grosbach.
...
llvm-svn: 138948
2011-09-01 18:02:14 +00:00
Owen Anderson
dd71d9efb9
The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.
...
llvm-svn: 138910
2011-08-31 22:00:41 +00:00
Owen Anderson
adac5b2109
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
...
llvm-svn: 138840
2011-08-30 22:58:27 +00:00
Owen Anderson
fd21da3506
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
...
llvm-svn: 138675
2011-08-26 23:32:08 +00:00
Owen Anderson
f47325fc54
Spelling fail.
...
llvm-svn: 138667
2011-08-26 21:47:57 +00:00
Owen Anderson
af51fd9868
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
...
llvm-svn: 138653
2011-08-26 20:43:14 +00:00
Owen Anderson
7658e342c3
Update for feedback from Jim.
...
llvm-svn: 138642
2011-08-26 19:39:26 +00:00
Benjamin Kramer
b279f20034
ARMDisassembler: Always return a size, even when disassembling fails.
...
This should fix PR10772.
llvm-svn: 138636
2011-08-26 18:21:36 +00:00
Owen Anderson
86b11d01eb
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
...
llvm-svn: 138635
2011-08-26 18:09:22 +00:00
Owen Anderson
87c906dabf
Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
...
This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.
llvm-svn: 138625
2011-08-26 06:19:51 +00:00
Owen Anderson
d387b48b0b
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
...
llvm-svn: 138575
2011-08-25 18:30:18 +00:00
Owen Anderson
8a6cf48f0e
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
...
llvm-svn: 138507
2011-08-24 22:40:22 +00:00
Owen Anderson
3732f1644b
Be careful not to walk off the end of the operand info list while updating VFP predicates.
...
llvm-svn: 138492
2011-08-24 21:35:46 +00:00
Evan Cheng
420bf5446c
Move TargetRegistry and TargetSelect from Target to Support where they belong.
...
These are strictly utilities for registering targets and components.
llvm-svn: 138450
2011-08-24 18:08:43 +00:00
Owen Anderson
ee4d781cd3
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
...
llvm-svn: 138443
2011-08-24 17:21:43 +00:00
Owen Anderson
3de2d7656d
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
...
llvm-svn: 138341
2011-08-23 17:51:38 +00:00
Owen Anderson
4ae835d7c9
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
...
llvm-svn: 138339
2011-08-23 17:45:18 +00:00
Owen Anderson
33f3f4ec2a
Reject invalid imod values in t2CPS instructions.
...
llvm-svn: 138306
2011-08-22 23:44:04 +00:00
Owen Anderson
39d3f234f7
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
...
llvm-svn: 138269
2011-08-22 20:27:12 +00:00
Owen Anderson
926f360e53
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
...
llvm-svn: 138255
2011-08-22 18:42:13 +00:00
Owen Anderson
816f5524f8
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
...
llvm-svn: 138251
2011-08-22 18:22:06 +00:00
Owen Anderson
59178665b5
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
...
llvm-svn: 138246
2011-08-22 17:56:58 +00:00
Owen Anderson
421e30086e
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
...
Found by randomized testing.
llvm-svn: 138003
2011-08-18 22:47:44 +00:00
Owen Anderson
d113a59074
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
...
llvm-svn: 138000
2011-08-18 22:31:17 +00:00
Owen Anderson
7f3f0234a2
Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.
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llvm-svn: 137997
2011-08-18 22:15:25 +00:00
Owen Anderson
d121f0e77c
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
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Fixes a large class of disassembler crashes found by randomized testing.
llvm-svn: 137995
2011-08-18 22:11:02 +00:00
Jim Grosbach
43a8f9d908
Tidy up. 80 columns.
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llvm-svn: 137881
2011-08-17 21:58:18 +00:00
Jim Grosbach
3efc45bfad
ARM clean up the imm_sr operand class representation.
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Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
llvm-svn: 137879
2011-08-17 21:51:27 +00:00
Owen Anderson
cae3d3381c
Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array.
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llvm-svn: 137838
2011-08-17 18:14:48 +00:00
Owen Anderson
3146968039
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
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Patch by James Molloy.
llvm-svn: 137830
2011-08-17 17:44:15 +00:00
Owen Anderson
ffb049d199
Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
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llvm-svn: 137787
2011-08-16 23:45:44 +00:00
Owen Anderson
2e722e7cd4
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
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llvm-svn: 137686
2011-08-15 23:38:54 +00:00
Owen Anderson
42946000dd
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
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Patch by James Molloy.
llvm-svn: 137647
2011-08-15 20:51:32 +00:00
Owen Anderson
894585de33
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
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llvm-svn: 137635
2011-08-15 18:44:44 +00:00
Owen Anderson
2ea55a0881
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
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llvm-svn: 137502
2011-08-12 20:36:11 +00:00
Owen Anderson
7b426d97ad
Fix decoding of ARM-mode STRH.
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llvm-svn: 137499
2011-08-12 20:02:50 +00:00
Owen Anderson
322b9ce8bf
Fix decoding of pre-indexed stores.
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llvm-svn: 137487
2011-08-12 18:12:39 +00:00
Owen Anderson
a1df383bae
Separate decoding for STREXD and LDREXD to make each work better.
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llvm-svn: 137476
2011-08-12 17:58:32 +00:00
Jim Grosbach
edefbb31c3
ARM STRT assembly parsing and encoding.
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llvm-svn: 137372
2011-08-11 22:18:00 +00:00
Owen Anderson
8a55a4d7be
Add another accidentally omitted predicate operand.
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llvm-svn: 137370
2011-08-11 22:08:38 +00:00
Owen Anderson
253a691ae5
Add missing predicate operand on SMLA and friends.
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llvm-svn: 137368
2011-08-11 22:05:38 +00:00
Owen Anderson
64c500c7dd
Fix decoding support for STREXD and LDREXD.
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llvm-svn: 137356
2011-08-11 21:34:58 +00:00
Owen Anderson
4618d77bcd
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
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llvm-svn: 137347
2011-08-11 20:47:56 +00:00
Owen Anderson
73e7d34732
Continue to tighten decoding by performing more operand validation.
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llvm-svn: 137340
2011-08-11 20:21:46 +00:00
Jim Grosbach
bfc85134c2
ARM STRBT assembly parsing and encoding.
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llvm-svn: 137337
2011-08-11 20:04:56 +00:00
Owen Anderson
63ccfdccd1
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
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llvm-svn: 137325
2011-08-11 19:00:18 +00:00
Owen Anderson
decc5fcced
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
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llvm-svn: 137323
2011-08-11 18:55:42 +00:00
Owen Anderson
8d6b9f063f
Improve error checking in the new ARM disassembler. Patch by James Molloy.
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llvm-svn: 137320
2011-08-11 18:24:51 +00:00
Jim Grosbach
5322f1ea74
ARM LDRT assembly parsing and encoding.
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llvm-svn: 137282
2011-08-10 23:43:54 +00:00
Owen Anderson
0fde7a84ee
Add initial support for decoding NEON instructions in Thumb2 mode.
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llvm-svn: 137236
2011-08-10 19:01:10 +00:00
Owen Anderson
0819cf208f
Cleanups based on Nick Lewycky's feedback.
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llvm-svn: 137224
2011-08-10 17:36:48 +00:00
Owen Anderson
87b5ce880a
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
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llvm-svn: 137189
2011-08-10 00:03:03 +00:00
Owen Anderson
b717d71aa1
Tighten operand checking of register-shifted-register operands.
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llvm-svn: 137180
2011-08-09 23:33:27 +00:00
Owen Anderson
62faf296dd
Tighten operand checking on memory barrier instructions.
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llvm-svn: 137176
2011-08-09 23:25:42 +00:00
Owen Anderson
869ce85500
Tighten operand checking on CPS instructions.
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llvm-svn: 137172
2011-08-09 23:05:39 +00:00
Owen Anderson
8ad37f68a2
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
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llvm-svn: 137168
2011-08-09 22:48:45 +00:00
Benjamin Kramer
ca48bdfd5b
ARM Disassembler: sign extend branch immediates.
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Not sure about BLXi, but this is what the old disassembler did.
llvm-svn: 137156
2011-08-09 22:02:50 +00:00
Owen Anderson
4232cf9141
Silence an false-positive warning.
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llvm-svn: 137154
2011-08-09 21:38:14 +00:00
Owen Anderson
2aa4c7e391
Tighten Thumb1 branch predicate decoding.
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llvm-svn: 137146
2011-08-09 21:07:45 +00:00
Owen Anderson
ffe1c55752
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
llvm-svn: 137144
2011-08-09 20:55:18 +00:00
Jim Grosbach
67621a1af4
ARM simplify the postidx_reg operand encoding.
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The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.
llvm-svn: 136969
2011-08-05 16:11:38 +00:00
Owen Anderson
11e2000c8c
Fix broken encodings for the Thumb2 LDRD/STRD instructions.
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llvm-svn: 136942
2011-08-04 23:18:05 +00:00
Jim Grosbach
767e9d16e6
ARM refactoring assembly parsing of memory address operands.
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Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
llvm-svn: 136845
2011-08-03 23:50:40 +00:00