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13645 Commits

Author SHA1 Message Date
Jim Grosbach
a91fcf98c9 ARM assembly parsing and encoding tests for UQASX and UQSAX. 
llvm-svn: 136280
 2011-07-27 22:09:30 +00:00
Jim Grosbach
a85f517680 ARM assembly parsing and encoding tests for UQADD16 and UQADD8. 
llvm-svn: 136279
 2011-07-27 22:08:14 +00:00
Jim Grosbach
df8040c528 ARM assembly parsing and encoding for UMULL. 
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136277
 2011-07-27 22:01:42 +00:00
Jim Grosbach
dd55e1de02 ARM assembly parsing and encoding for UMLAL. 
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136274
 2011-07-27 21:58:11 +00:00
Jim Grosbach
f48e465aa5 ARM assembly parsing and encoding tests for UMAAL. 
llvm-svn: 136272
 2011-07-27 21:53:42 +00:00
Jim Grosbach
91f7d83f9c ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8. 
llvm-svn: 136267
 2011-07-27 21:21:59 +00:00
Jim Grosbach
6f34be1f69 ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX. 
llvm-svn: 136266
 2011-07-27 21:20:45 +00:00
Jim Grosbach
c5cd3228c4 ARM parsing and encoding of SBFX and UBFX. 
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].

llvm-svn: 136264
 2011-07-27 21:09:25 +00:00
Jim Grosbach
8393f12ec5 ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX. 
llvm-svn: 136261
 2011-07-27 20:43:44 +00:00
Jim Grosbach
1f818d0f25 ARM assembly parsing and encoding tests for TST instruction. 
llvm-svn: 136260
 2011-07-27 20:38:58 +00:00
Jim Grosbach
e74be6ad39 ARM assembly parsing and encoding tests for TEQ instruction. 
llvm-svn: 136259
 2011-07-27 20:37:36 +00:00
Owen Anderson
d2cd33b911 Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. 
llvm-svn: 136255
 2011-07-27 20:29:48 +00:00
Bill Wendling
b20cfdfe95 Merge the contents from exception-handling-rewrite to the mainline. 
This adds the new instructions 'landingpad' and 'resume'.

llvm-svn: 136253
 2011-07-27 20:18:04 +00:00
Jim Grosbach
624acaffd7 ARM assembly parsing and encoding for extend instructions. 
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.

llvm-svn: 136252
 2011-07-27 20:15:40 +00:00
Nick Lewycky
59edfce6f7 Teach the ConstantMerge pass about alignment. Fixes PR10514! 
llvm-svn: 136250
 2011-07-27 19:47:34 +00:00
Bruno Cardoso Lopes
8830fde434 The vpermilps and vpermilpd have different behaviour regarding the 
usage of the shuffle bitmask. Both work in 128-bit lanes without
crossing, but in the former the mask of the high part is the same
used by the low part while in the later both lanes have independent
masks. Handle this properly and and add support for vpermilpd.

llvm-svn: 136200
 2011-07-27 00:56:34 +00:00
Devang Patel
e85a416d4e It is quiet possible that inlined function body is split into multiple chunks of consequtive instructions. But, there is not any way to describe this in .debug_inline accelerator table used by gdb. However, describe non contiguous ranges of inlined function body appropriately using AT_range of DW_TAG_inlined_subroutine debug info entry. 
llvm-svn: 136196
 2011-07-27 00:34:13 +00:00
Eric Christopher
db2a1cde87 Remove these two directories. The tests can be ported to dragonegg if 
they're still wanted.

llvm-svn: 136193
 2011-07-27 00:07:56 +00:00
Eric Christopher
a9f6746f91 Remove test/FrontendC, almost all of the tests have been migrated 
to clang now, the rest are in process (6) or have been deleted.

llvm-svn: 136191
 2011-07-26 23:49:39 +00:00
Jakob Stoklund Olesen
3f729850d3 Eliminate copies of undefined values during coalescing. 
These copies would coalesce easily, but the resulting value would be
defined by a deleted instruction. Now we also remove the undefined value
number from the destination register.

This fixes PR10503.

llvm-svn: 136174
 2011-07-26 23:00:24 +00:00
Benjamin Kramer
32a2ce8416 Update test. 
llvm-svn: 136170
 2011-07-26 22:45:39 +00:00
Benjamin Kramer
bfc2dfe3f7 Add a neat little two's complement hack for x86. 
On x86 we can't encode an immediate LHS of a sub directly. If the RHS comes from a XOR with a constant we can
fold the negation into the xor and add one to the immediate of the sub. Then we can turn the sub into an add,
which can be commuted and encoded efficiently.

This code is generated for __builtin_clz and friends.

llvm-svn: 136167
 2011-07-26 22:42:13 +00:00
Bruno Cardoso Lopes
e53bb853ea Recognize unpckh* masks and match 256-bit versions. The new versions are 
different from the previous 128-bit because they work in lanes.
Update a few comments and add testcases

llvm-svn: 136157
 2011-07-26 22:03:40 +00:00
Eli Friedman
4e16c5341a Prevent x86-specific DAGCombine from creating nodes with illegal type (which could not be selected). Fixes a minor isel issue that was breaking the testcase from r136130. 
llvm-svn: 136148
 2011-07-26 21:02:58 +00:00
Jim Grosbach
906ecb46ed FileCheck'ize test. 
llvm-svn: 136135
 2011-07-26 20:49:44 +00:00
Eli Friedman
8779017138 XFAIL this test while I investigate it; it's failing for an unexpected reason. 
llvm-svn: 136131
 2011-07-26 20:41:03 +00:00
Eli Friedman
e52bee3cc9 Add obvious missing case to switch. PR10497. 
llvm-svn: 136130
 2011-07-26 20:38:49 +00:00
Jim Grosbach
8e642b2b18 ARM diagnostics for ldrexd/stredx out of order paired register operands. 
llvm-svn: 136110
 2011-07-26 18:25:39 +00:00
Jim Grosbach
7b56b1cf0e ARM parsing and encoding tests for load/store exclusive instructions. 
llvm-svn: 136105
 2011-07-26 18:07:21 +00:00
Jim Grosbach
6fbee17fef ARM assembly parsing and encoding for SWP[B] instructions. 
llvm-svn: 136098
 2011-07-26 17:15:11 +00:00
Jim Grosbach
d3152480f2 ARM parsing and encoding for SVC instruction. 
llvm-svn: 136090
 2011-07-26 16:24:27 +00:00
Jim Grosbach
422ac2fc64 ARM assembly parsing and encoding tests for SUB instruction. 
llvm-svn: 136089
 2011-07-26 15:44:05 +00:00
Jim Grosbach
3efad526c2 Update ARM STM tests. Fix check: prefix for diagnostic tests. 
llvm-svn: 136088
 2011-07-26 15:41:22 +00:00
Bruno Cardoso Lopes
ab40a57cce Add 256-bit isel for movsldup/movshdup 
llvm-svn: 136051
 2011-07-26 02:39:32 +00:00
Jim Grosbach
41a5cd3fa2 ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8. 
llvm-svn: 136013
 2011-07-25 23:32:14 +00:00
Nick Lewycky
271216a67b Finish adding support for lifetime intrinsics to SROA. Fixes PR10121! 
llvm-svn: 136008
 2011-07-25 23:14:22 +00:00
Jim Grosbach
ef3d573e31 ARM assembly parsing and encoding for SSAT16 instruction. 
llvm-svn: 136006
 2011-07-25 23:09:14 +00:00
Bruno Cardoso Lopes
c94d6a2d2c Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128 
This also fixes PR10452

llvm-svn: 136004
 2011-07-25 23:05:32 +00:00
Bruno Cardoso Lopes
9380919dc5 - Handle special scalar_to_vector case: splats. Using a native 128-bit 
shuffle before inserting on a 256-bit vector.
- Add AVX versions of movd/movq instructions
- Introduce a few COPY patterns to match insert_subvector instructions.
This turns a trivial insert_subvector instruction into a register copy,
coalescing the xmm into a ymm and avoid emiting on more instruction.

llvm-svn: 136002
 2011-07-25 23:05:25 +00:00
Eli Friedman
dc213dadcc Attempt to fix test failure reported on llvm-commits. 
llvm-svn: 135995
 2011-07-25 22:28:51 +00:00
Eli Friedman
99fd6d41b5 Make sure this DAGCombine actually returns an UNDEF of the correct type; PR10476. 
llvm-svn: 135993
 2011-07-25 22:25:42 +00:00
Jim Grosbach
c1fe042da0 ARM assembly parsing and encoding for SSAT instruction. 
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').

Add tests for diagnostics and proper encoding.

llvm-svn: 135990
 2011-07-25 22:20:28 +00:00
Eli Friedman
234bbb2b95 Get rid of an incorrect optimization for shuffles with PALIGNR and simplify isPALIGNRMask. 
Addresses PR10466, although the crash from that PR only triggers in cases where DAGCombine misses optimizing a shuffle.

llvm-svn: 135980
 2011-07-25 21:36:45 +00:00
Jim Grosbach
2f728674cf Move some ELF directives into ELF asm parser. 
The .local, .hidden, .internal, and .protected are not legal for all supported
file formats (in particular, they're invalid for MachO). Move the parsing for
them into the ELF assembly parser since that's the format they're for.
Similarly, .weak is used by COFF and ELF, but not MachO, so move the parsing
to the COFF and ELF asm parsers. Previously, using any of these directives
on Darwin would result in an assertion failure in the parser; now we get
a diagnostic as we should.

rdar://9827089

llvm-svn: 135921
 2011-07-25 17:55:35 +00:00
Jakob Stoklund Olesen
0e4f7f92a2 Correctly handle <undef> tied uses when rewriting after a split. 
This fixes PR10463. A two-address instruction with an <undef> use
operand was incorrectly rewritten so the def and use no longer used the
same register, violating the tie constraint.

Fix this by always rewriting <undef> operands with the register a def
operand would use.

llvm-svn: 135885
 2011-07-24 20:23:50 +00:00
Dan Gohman
1c4dff0ab3 Move the last uses of RetainFunc etc. over to using getRetainCallee() etc. 
so that a declaration for objc_retain is created when needed if it doesn't
already exist. rdar://9825114.

llvm-svn: 135821
 2011-07-22 22:29:21 +00:00
Jim Grosbach
0bfa6a6db7 Add FIXME 
llvm-svn: 135819
 2011-07-22 22:15:38 +00:00
Jim Grosbach
daf04c88c2 ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX. 
llvm-svn: 135818
 2011-07-22 22:13:00 +00:00
Jim Grosbach
a7a6658647 ARM assembly parsing and encoding updates. 
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.

llvm-svn: 135817
 2011-07-22 22:06:05 +00:00
Jim Grosbach
1e724e3217 ARM assembly parsing and encoding tests. 
Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.

llvm-svn: 135810
 2011-07-22 21:34:56 +00:00