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Author SHA1 Message Date
Bill Wendling
aeb63260c7 Minor modifications to make the Hello World example resemble the Hello World 
pass in the tree. Also some minor formatting changes.
PR9413

llvm-svn: 141655
 2011-10-11 07:03:52 +00:00
Craig Topper
db2d702bff Make Ivy Bridge 16-bit floating point conversion instructions require AVX. 
llvm-svn: 141654
 2011-10-11 07:01:37 +00:00
Nick Lewycky
6bd023fab9 Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take 
that into account and test for no U's showing up in the middle, which is what
we really wanted to test for.

llvm-svn: 141653
 2011-10-11 06:58:11 +00:00
Craig Topper
f95d9bd513 Test case for X86 LZCNT instruction selection. 
llvm-svn: 141652
 2011-10-11 06:47:01 +00:00
Craig Topper
c498c5c0e6 Add X86 LZCNT instruction. Including instruction selection support. 
llvm-svn: 141651
 2011-10-11 06:44:02 +00:00
Bill Wendling
093fd0ca05 Use the proper name for "externally visible" linkage -- 'external'. This is the 
keyword in LLVM for externally visible linkage.
PR10636

llvm-svn: 141649
 2011-10-11 06:41:28 +00:00
Bill Wendling
2d42685bf0 Reword the SetVector description to reflect reality. 
Patch by Michael Ilseman!

llvm-svn: 141648
 2011-10-11 06:33:56 +00:00
Cameron Zwarich
211901eb9f Add a test for PR10565. 
llvm-svn: 141647
 2011-10-11 06:10:37 +00:00
Cameron Zwarich
a34d748f83 Remove a lot of the fancy scalar replacement code for dealing with llvm-gcc's 
lowering of NEON code. It provides little-to-no benefit now and only introduces
additional complexity.

llvm-svn: 141646
 2011-10-11 06:10:30 +00:00
Bill Wendling
2606813218 Test simplification that Ana Pazos noticed. 
llvm-svn: 141644
 2011-10-11 04:43:15 +00:00
Craig Topper
7ae42fbd7e Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
llvm-svn: 141642
 2011-10-11 04:34:23 +00:00
Nick Lewycky
509687695f Also create a shndx even if there are no symbols. This lets us test 
.symtab_shndx reading and writing together, and finally we have a testcase for
r141440.

llvm-svn: 141641
 2011-10-11 03:54:50 +00:00
NAKAMURA Takumi
00636555f2 test/CodeGen/X86/movbe.ll: Give explicit -mtriple=x86_64-linux, to unbreak win32 hosts. 
llvm-svn: 141640
 2011-10-11 03:41:03 +00:00
Nick Lewycky
7cea83d5a5 Reapply r141605 with fixes for appropriate handling of reserved section numbers 
in st_shndx fields.

llvm-svn: 141639
 2011-10-11 03:18:58 +00:00
Nick Lewycky
c8160ebc71 Add support for .symtab_shnidx. Unfortunately, doing this required breaking a 
layer of abstraction around SymbolRef where you can read its private
SymbolPimpl member.

llvm-svn: 141636
 2011-10-11 02:57:48 +00:00
Andrew Trick
23866a5e65 Add experimental -enable-lsr-phielim option. 
I'm not sure we will need it in the long run, but the option is
currently useful for checking if the output of LSR is "clean".

llvm-svn: 141634
 2011-10-11 02:30:45 +00:00
Andrew Trick
d36852e6b1 Move replaceCongruentIVs into SCEVExapander and bias toward "expanded" 
IVs.

Indvars previously chose randomly between congruent IVs. Now it will
bias the decision toward IVs that SCEVExpander likes to create. This
was not done to fix any problem, it's just a welcome side effect of
factoring code.

llvm-svn: 141633
 2011-10-11 02:28:51 +00:00
Akira Hatanaka
2da85501f4 Test cases for 64-bit load and store instructions. 
llvm-svn: 141631
 2011-10-11 01:52:31 +00:00
Lang Hames
386b01379a Added a testcase for r141599, rdar://problem/10063881. 
llvm-svn: 141628
 2011-10-11 01:32:10 +00:00
Akira Hatanaka
20808df5a0 Make changes necessary for supporting floating point load and store instructions 
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623
 2011-10-11 01:12:52 +00:00
Jakob Stoklund Olesen
81dd697279 Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo(). 
The VMOVS widening needs to look at the implicit COPY operands.  Trying
to dig out the COPY instruction from an iterator in copyPhysReg() is the
wrong approach.

The expandPostRAPseudo() hook gets to look at COPY instructions before
they are converted to copyPhysReg() calls.

llvm-svn: 141619
 2011-10-11 00:59:06 +00:00
Akira Hatanaka
3f89f9bc37 Modify lowering of GlobalAddress so that correct code is emitted when target is 
Mips64.

llvm-svn: 141618
 2011-10-11 00:55:05 +00:00
Lang Hames
41b4ff724d Fixed natural stack alignment for Linux x86-32. Thanks Eli. 
llvm-svn: 141616
 2011-10-11 00:51:36 +00:00
Akira Hatanaka
1913a9abc0 Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too. 
llvm-svn: 141615
 2011-10-11 00:44:20 +00:00
Nick Lewycky
76c927f5bd Revert r141605 as it broke tests for llvm-nm. 
llvm-svn: 141614
 2011-10-11 00:38:56 +00:00
Akira Hatanaka
6f90f8d68d Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot. 
llvm-svn: 141613
 2011-10-11 00:37:28 +00:00
Akira Hatanaka
404fb72f59 Add definitions of 64-bit loads and stores. Add a patterns for unaligned 
zextloadi32 for which there is no corresponding pseudo or real instruction. 

llvm-svn: 141608
 2011-10-11 00:27:28 +00:00
Bill Wendling
cb617ae8e0 Add testcase for PR11107. 
llvm-svn: 141607
 2011-10-11 00:26:57 +00:00
Tanya Lattner
0ae574fe2b Make it possible to use the linker without destroying the source module. This is so the source module can be linked to multiple other destination modules. For all that used LinkModules() before, they will continue to destroy the source module as before. 
This line, and those below, will be ignored--

M    include/llvm/Linker.h
M    tools/bugpoint/Miscompilation.cpp
M    tools/bugpoint/BugDriver.cpp
M    tools/llvm-link/llvm-link.cpp
M    lib/Linker/LinkModules.cpp

llvm-svn: 141606
 2011-10-11 00:24:54 +00:00
Nick Lewycky
bf9a3771b7 Add support for reading many-section ELF files. 
If you want to tackle adding the testcase, let me know. It's a 4.2MB ELF file
and I'll be happy to mail it to you.

llvm-svn: 141605
 2011-10-11 00:15:42 +00:00
Akira Hatanaka
ac95006d45 Change definitions of classes LoadM and StoreM in preparation for adding support 
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.

llvm-svn: 141603
 2011-10-11 00:11:12 +00:00
Bill Wendling
1a1ee723b0 Simplify check that optional def is there and is CPSR. 
llvm-svn: 141602
 2011-10-11 00:10:41 +00:00
Lang Hames
be4997db2f Add a natural stack alignment field to TargetData, and prevent InstCombine from 
promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.

The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.

llvm-svn: 141599
 2011-10-10 23:42:08 +00:00
Michael J. Spencer
525906b5d9 Fix warning. 
llvm-svn: 141597
 2011-10-10 23:36:56 +00:00
Devang Patel
e6091c61c7 Revert r141569 and r141576. 
llvm-svn: 141594
 2011-10-10 23:18:02 +00:00
Jim Grosbach
ab5dbe090b Simplify operand Kind checks a bit. 
llvm-svn: 141592
 2011-10-10 23:06:42 +00:00
Bill Wendling
7121342ad5 Reapply r141365 now that PR11107 is fixed. 
llvm-svn: 141591
 2011-10-10 22:59:55 +00:00
Jim Grosbach
21a08a2b41 Add a name to sub-operand for clarity. 
llvm-svn: 141590
 2011-10-10 22:55:05 +00:00
Bill Wendling
9cf46b3bd5 If the CPSR is defined by a copy, then we don't want to merge it into an IT 
block. E.g., if we have:

  movs  r1, r1
  rsb   r1, 0
  movs  r2, r2
  rsb   r2, 0

we don't want this to be converted to:

  movs  r1, r1
  movs  r2, r2
  itt   mi
  rsb   r1, 0
  rsb   r2, 0

PR11107 & <rdar://problem/10259534>

llvm-svn: 141589
 2011-10-10 22:52:53 +00:00
Eli Friedman
7188ba35cb Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102. 
llvm-svn: 141585
 2011-10-10 22:28:47 +00:00
Michael J. Spencer
ebd507f958 Object: add getSectionAlignment. 
llvm-svn: 141581
 2011-10-10 21:55:43 +00:00
Nick Lewycky
73e4d372d0 Add support for dumping section headers to llvm-objdump. This uses the same 
flags as binutils objdump but the output is different, not just in format but
also showing different sections. Compare its results against readelf, not
objdump.

llvm-svn: 141579
 2011-10-10 21:21:34 +00:00
Jakob Stoklund Olesen
0d908f3a85 Give targets a chance to expand even standard pseudos. 
Allow targets to expand COPY and other standard pseudo-instructions
before they are expanded with copyPhysReg().

This allows the target to examine the COPY instruction for extra
operands indicating it can be widened to a preferable super-register
copy.  See the ARM -widen-vmovs option.

llvm-svn: 141578
 2011-10-10 20:34:28 +00:00
Devang Patel
d6f05a47c1 If loop header is also loop exiting block then it may not be safe to hoist instructions. 
llvm-svn: 141576
 2011-10-10 20:32:03 +00:00
Jakob Stoklund Olesen
ad7ffa5235 Emit full ED initializers even for pseudo-instructions. 
This should unbreak the picky buildbots.

llvm-svn: 141575
 2011-10-10 20:15:49 +00:00
Andrew Trick
4c8a7dc833 Allow stat += 0 without activating the stat. 
For me, this is a nice convenience. We generally want grep to match
stats output only when the event has occurred.

llvm-svn: 141574
 2011-10-10 19:48:56 +00:00
Andrew Trick
fe8c38a61e whitespace 
llvm-svn: 141572
 2011-10-10 19:35:46 +00:00
Benjamin Kramer
60387b6640 X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge. 
llvm-svn: 141571
 2011-10-10 19:35:07 +00:00
Nadav Rotem
38187aec17 Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the 
instruction set has no 64-bit SRA support.

llvm-svn: 141570
 2011-10-10 19:31:45 +00:00
Devang Patel
c149f390c6 Add dominance check for the instruction being hoisted. 
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141569
 2011-10-10 19:09:20 +00:00