Evan Cheng
9af68f56c5
Remove isImplicitDef TargetInstrDesc flag.
...
llvm-svn: 48381
2008-03-15 00:19:36 +00:00
Evan Cheng
11d2c09adc
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
Dale Johannesen
6195ace4c0
Implement the real calling convention for ppc32 Altivec:
...
vectors go at the end of the memory area, after all
non-vector parameters.
llvm-svn: 48364
2008-03-14 17:41:26 +00:00
Evan Cheng
877c5ecabd
Fix some 80 col violations.
...
llvm-svn: 48361
2008-03-14 07:46:48 +00:00
Evan Cheng
fc6645a382
Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8).
...
llvm-svn: 48360
2008-03-14 07:39:27 +00:00
Evan Cheng
6ef1ca4e87
Add debugging stuff.
...
llvm-svn: 48359
2008-03-14 07:13:42 +00:00
Chris Lattner
c60749aa4c
Add an issue that is preventing instcombine from doing a simplification.
...
llvm-svn: 48356
2008-03-14 06:00:19 +00:00
Dan Gohman
6a74c23363
Use SDTNone instead of duplicating it.
...
llvm-svn: 48346
2008-03-13 23:07:40 +00:00
Christopher Lamb
0f1c32eb63
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
...
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
2008-03-13 05:47:01 +00:00
Dale Johannesen
1e54f7c2b6
Do not promote float params to double in varargs
...
calls here. This was done earlier for params in
the varargs part of the params; any float params
that survive to here are in the non-varargs part,
and must not be promoted.
llvm-svn: 48310
2008-03-12 23:40:01 +00:00
Chris Lattner
7925cc72c0
Reimplement the parameter attributes support, phase #1 . hilights:
...
1. There is now a "PAListPtr" class, which is a smart pointer around
the underlying uniqued parameter attribute list object, and manages
its refcount. It is now impossible to mess up the refcount.
2. PAListPtr is now the main interface to the underlying object, and
the underlying object is now completely opaque.
3. Implementation details like SmallVector and FoldingSet are now no
longer part of the interface.
4. You can create a PAListPtr with an arbitrary sequence of
ParamAttrsWithIndex's, no need to make a SmallVector of a specific
size (you can just use an array or scalar or vector if you wish).
5. All the client code that had to check for a null pointer before
dereferencing the pointer is simplified to just access the
PAListPtr directly.
6. The interfaces for adding attrs to a list and removing them is a
bit simpler.
Phase #2 will rename some stuff (e.g. PAListPtr) and do other less
invasive changes.
llvm-svn: 48289
2008-03-12 17:45:29 +00:00
Evan Cheng
df92afe7d3
Clean up my own mess.
...
X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.
llvm-svn: 48279
2008-03-12 07:02:50 +00:00
Dale Johannesen
19b4c2dfaf
One more bit of Altivec parameter passing.
...
llvm-svn: 48269
2008-03-12 00:49:20 +00:00
Dale Johannesen
460dc31418
Implement Altivec passing to varargs functions on ppc.
...
llvm-svn: 48264
2008-03-12 00:22:17 +00:00
Anton Korobeynikov
55f54ba252
Correctly propagate thread-local flag from aliasee to alias. This fixes PR2137
...
llvm-svn: 48257
2008-03-11 22:38:53 +00:00
Dan Gohman
8e3c88c4e9
Use PassManagerBase instead of FunctionPassManager for functions
...
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.
llvm-svn: 48256
2008-03-11 22:29:46 +00:00
Chris Lattner
fd2c24af72
Implement basic support for the 'f' register class constraint. This basically
...
works, but probably won't if you mix it with 't' or 'u' yet.
llvm-svn: 48243
2008-03-11 19:50:13 +00:00
Chris Lattner
4458eecb7a
coalesce away 80-bit floating point copies.
...
llvm-svn: 48241
2008-03-11 19:30:09 +00:00
Chris Lattner
aa2287714e
convert a massive if statement to a switch.
...
llvm-svn: 48240
2008-03-11 19:28:17 +00:00
Chris Lattner
b3fefb1e5c
start handling the 'f' x87 constraint.
...
llvm-svn: 48239
2008-03-11 19:06:29 +00:00
Christopher Lamb
4d5034cf91
Missed part of recommit.
...
llvm-svn: 48224
2008-03-11 10:27:36 +00:00
Christopher Lamb
74f4d837df
Recommitting parts of r48130. These do not appear to cause the observed failures.
...
llvm-svn: 48223
2008-03-11 10:09:17 +00:00
Evan Cheng
318a01e5fb
If there are multiple register classes that a register belongs to, return the super-class (e.g. on x86, returns GR32, not GR32_).
...
llvm-svn: 48220
2008-03-11 07:54:14 +00:00
Evan Cheng
af1c76846d
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
...
llvm-svn: 48218
2008-03-11 07:19:34 +00:00
Evan Cheng
53213ba056
In 32-bit mode, mark 64-bit GPR's as unallocatable.
...
llvm-svn: 48217
2008-03-11 07:16:00 +00:00
Nick Lewycky
02e4d6f2dd
Fix the build on gcc 4.2.
...
llvm-svn: 48212
2008-03-11 05:56:09 +00:00
Chris Lattner
9826c9365e
Change the model for FP Stack return to use fp operands on the
...
RET instruction instead of using FpSET_ST0_32. This also generalizes
the code to handling returning of multiple FP results.
llvm-svn: 48209
2008-03-11 03:23:40 +00:00
Dan Gohman
85bfbe2293
Generalize ExpandIntToFP to handle the case where the operand is legal
...
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type.
llvm-svn: 48206
2008-03-11 01:59:03 +00:00
Chris Lattner
d1a014af4e
abort with an assert instead of a cerr to get line#
...
llvm-svn: 48199
2008-03-10 23:56:08 +00:00
Scott Michel
599ff689d0
- Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.
...
- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.
llvm-svn: 48197
2008-03-10 23:49:09 +00:00
Chris Lattner
f0684bfd16
Don't emit FP_REG_KILL into a block that just returns. Nothing
...
can be live out of the block anyway, so it isn't needed.
llvm-svn: 48192
2008-03-10 23:34:12 +00:00
Dale Johannesen
3278acdaaa
Disable prolog code that aligns the stack when a
...
local object of >16 byte alignment exists. It does not
work and getting it to work is not trivial, as explained
in the comment. This fixes all the remaining ppc32
failures in the struct-layout-1 part of the gcc testsuite.
(gcc does not support this either, and the only way to
get such an object is with __attribute__((aligned)) or
generic vectors; it can't be done in a standard-conforming
program, or with Altivec. So I think disabling it is OK.)
llvm-svn: 48188
2008-03-10 22:59:46 +00:00
Bill Wendling
80bc045af5
Change the "enable/disable" mechanism so that we can enable PPC register
...
scavenging for 32-bit and 64-bit separately.
llvm-svn: 48186
2008-03-10 22:49:16 +00:00
Chris Lattner
d393772580
Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to
...
copyfromreg/copytoreg instead.
llvm-svn: 48174
2008-03-10 21:08:41 +00:00
Evan Cheng
7d9e5a7680
Default ISD::PREFETCH to expand.
...
llvm-svn: 48169
2008-03-10 19:38:10 +00:00
Evan Cheng
067ecbc341
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
...
llvm-svn: 48167
2008-03-10 19:31:26 +00:00
Chris Lattner
52be2c645e
fix 80 col violations.
...
llvm-svn: 48166
2008-03-10 18:55:53 +00:00
Nicolas Geoffray
a904844534
Stylistic modifications. No functionality changes.
...
llvm-svn: 48158
2008-03-10 17:46:45 +00:00
Scott Michel
38f8a1043a
Integer comparison tests for CellSPU.
...
llvm-svn: 48152
2008-03-10 16:58:52 +00:00
Scott Michel
bb8e8fca47
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
...
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
llvm-svn: 48145
2008-03-10 15:42:14 +00:00
Nicolas Geoffray
e3381f0f1f
Add description of individual bits in CR. This fix PR1765.
...
llvm-svn: 48143
2008-03-10 14:12:10 +00:00
Christopher Lamb
32e5ce3d96
Allow insert_subreg into implicit, target-specific values.
...
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
llvm-svn: 48130
2008-03-10 06:12:08 +00:00
Dale Johannesen
e6b0009792
Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
...
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff. Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)
llvm-svn: 48122
2008-03-10 02:17:22 +00:00
Chris Lattner
4a5abdbe3f
Darwin PPC64 indirect call target goes in X12, not R12. This fixes these
...
two regression tests:
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
llvm-svn: 48120
2008-03-09 20:49:33 +00:00
Chris Lattner
23ee644c71
cell really does support cross-regclass moves, because R3 is in lots of different regclasses, and the code is not consistent when it comes to value tracking.
...
llvm-svn: 48119
2008-03-09 20:31:11 +00:00
Chris Lattner
9185c43c7d
make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.ll
...
llvm-svn: 48118
2008-03-09 20:12:44 +00:00
Chris Lattner
b6bfedbcfd
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from
...
an RFP register class.
Teach ScheduleDAG how to handle CopyToReg with different src/dst
reg classes.
This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.
llvm-svn: 48107
2008-03-09 09:15:31 +00:00
Chris Lattner
b29a963cf5
add some code to support cross-register class copying from
...
RST -> RFP{32/64/80}. We only handle ST(0) for now.
llvm-svn: 48104
2008-03-09 08:46:19 +00:00
Chris Lattner
53b86390b7
rearrange some code, no functionality change.
...
llvm-svn: 48101
2008-03-09 07:58:04 +00:00
Chris Lattner
71189e9501
claim ST(x) registers are 80 bits, which is true. This doesn't affect
...
codegen yet because these can't be spilled (they don't exist until after RA).
llvm-svn: 48098
2008-03-09 07:49:01 +00:00
Chris Lattner
2e7537b60b
rename FP_SETRESULT -> FP_SET_ST0
...
llvm-svn: 48094
2008-03-09 07:08:44 +00:00
Chris Lattner
826402e365
rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for
...
isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.
llvm-svn: 48093
2008-03-09 07:05:32 +00:00
Chris Lattner
b628208161
Finish implementing a readme entry: when inserting an i64 variable
...
into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle. This allows us to compile
vec_set-B.ll into:
_test3:
movl $1234567, %eax
andl 4(%esp), %eax
movd %eax, %xmm0
ret
instead of:
_test3:
subl $28, %esp
movl $1234567, %eax
andl 32(%esp), %eax
movl %eax, (%esp)
movl $0, 4(%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48090
2008-03-09 05:42:06 +00:00
Chris Lattner
b741ebba29
add a note
...
llvm-svn: 48064
2008-03-09 01:08:22 +00:00
Chris Lattner
17f68a3075
Implement a readme entry, compiling
...
#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
movl $1, %eax
movd %eax, %xmm0
ret
instead of a constant pool load.
llvm-svn: 48063
2008-03-09 01:05:04 +00:00
Chris Lattner
81deb3bc9c
1) Improve comments.
...
2) Don't try to insert an i64 value into the low part of a
vector with movq on an x86-32 target. This allows us to
compile:
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
_doload64:
movaps LCPI1_0, %xmm0
ret
instead of:
_doload64:
subl $28, %esp
movl $0, 4(%esp)
movl $1, (%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48057
2008-03-08 22:59:52 +00:00
Chris Lattner
405f2c6356
minor simplifications to this code, don't create a dead
...
SCALAR_TO_VECTOR on paths that end up not using it.
llvm-svn: 48056
2008-03-08 22:48:29 +00:00
Chris Lattner
ff9dc0af80
This one looks easy, add a note.
...
llvm-svn: 48055
2008-03-08 22:32:39 +00:00
Chris Lattner
b12697f8bb
move these to the appropriate file
...
llvm-svn: 48054
2008-03-08 22:28:45 +00:00
Dale Johannesen
55d6e1a5aa
More ppc32 byval handling (bug fixes). Things
...
are looking pretty good now.
llvm-svn: 48043
2008-03-08 01:41:42 +00:00
Evan Cheng
dba1dfe962
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
...
llvm-svn: 48042
2008-03-08 00:58:38 +00:00
Dan Gohman
afeac8050d
Add support for calls with i128 return values on ppc64.
...
llvm-svn: 48041
2008-03-08 00:19:12 +00:00
Bill Wendling
948c50e2be
PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this
...
by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.
llvm-svn: 48030
2008-03-07 20:49:02 +00:00
Dan Gohman
5bf464e1e6
Add support for lowering 128-bit shifts on ppc64.
...
llvm-svn: 48029
2008-03-07 20:36:53 +00:00
Dale Johannesen
3e6bacf7be
Next bits of PPC byval handling. Basically functional
...
but there are bugs.
llvm-svn: 48028
2008-03-07 20:27:40 +00:00
Chris Lattner
08ec4919ea
Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).
...
llvm-svn: 48027
2008-03-07 20:18:24 +00:00
Chris Lattner
2f13ccc181
Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work
...
with 32 or 64-bit operands/results.
llvm-svn: 48026
2008-03-07 20:13:51 +00:00
Chris Lattner
aa81dc7d21
mark frem as expand for all legal fp types on x86, regardless of whether
...
we're using SSE or not. This fixes PR2122.
llvm-svn: 48006
2008-03-07 06:36:32 +00:00
Gabor Greif
92e00c1e50
some more spelling changes
...
llvm-svn: 47996
2008-03-06 10:51:21 +00:00
Scott Michel
8dd2324903
Refine Cell's i64 constant generation code to cover more constants where the
...
upper and lower 32-bits are the same (in addition to 0 and -1 previously.)
llvm-svn: 47985
2008-03-06 04:02:54 +00:00
Andrew Lenharth
0c26f5bb94
gcc likes things spelled correctly
...
llvm-svn: 47981
2008-03-05 23:41:37 +00:00
Dale Johannesen
6bcc9808db
Next bit of PPC ByVal handling; call-site code seems
...
correct now.
llvm-svn: 47978
2008-03-05 23:31:27 +00:00
Scott Michel
c29399e54e
- Fix support for "special" i64 immediates that can be loaded
...
using IL, ILA, et. al. v2i64 and i64 are now supported by
the select bits (SELB) instruction.
- Add missing comparison operations (testcase forthcoming)
- More multiclass refactoring.
llvm-svn: 47973
2008-03-05 23:02:02 +00:00
Chris Lattner
83e0b885f8
evan implemented this.
...
llvm-svn: 47948
2008-03-05 17:11:51 +00:00
Evan Cheng
a36562006a
isTwoAddress = 1 -> Constraints.
...
llvm-svn: 47941
2008-03-05 08:19:16 +00:00
Evan Cheng
6c2bb7c67e
PSLLWri etc. are two-address instructions.
...
llvm-svn: 47940
2008-03-05 08:11:27 +00:00
Chris Lattner
7571a88209
add a note
...
llvm-svn: 47939
2008-03-05 07:22:39 +00:00
Evan Cheng
d421708e35
Ignore debugging related instructions if they get this far.
...
llvm-svn: 47934
2008-03-05 02:34:36 +00:00
Evan Cheng
a2939a16de
Rather than asserting. Dump out the MI that we are not able to encode and abort.
...
llvm-svn: 47933
2008-03-05 02:08:03 +00:00
Evan Cheng
e0b3c221ab
Add a target lowering hook to control whether it's worthwhile to compress fp constant.
...
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.
llvm-svn: 47931
2008-03-05 01:30:59 +00:00
Andrew Lenharth
95c88272c6
64bit CAS on 32bit x86.
...
llvm-svn: 47929
2008-03-05 01:15:49 +00:00
Evan Cheng
18064ddb5b
Refactor code. Remove duplicated functions that basically do the same thing as
...
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.
llvm-svn: 47927
2008-03-05 00:59:57 +00:00
Bill Wendling
37f5b4586a
Removed spurious EnablePPCRS check.
...
llvm-svn: 47918
2008-03-04 23:27:33 +00:00
Dale Johannesen
86867d323e
Move PPC lowering functions into PPCTargetLowering
...
class (cosmetic). First piece of byval implementation;
this doesn't work yet. No functional change.
llvm-svn: 47917
2008-03-04 23:17:14 +00:00
Bill Wendling
dc9de245cb
Use a command-line option to turn register scavenging on/off for PPC.
...
llvm-svn: 47915
2008-03-04 23:13:51 +00:00
Andrew Lenharth
f5674915c5
x86-64 atomics
...
llvm-svn: 47903
2008-03-04 21:13:33 +00:00
Evan Cheng
ae414db8d2
80 column violations.
...
llvm-svn: 47878
2008-03-04 03:20:06 +00:00
Evan Cheng
139517b682
Remove -always-fold-and-in-test.
...
llvm-svn: 47871
2008-03-04 00:40:35 +00:00
Dan Gohman
ccc0bc5878
Add support for lowering i64 SRA_PARTS and friends on x86-64.
...
llvm-svn: 47865
2008-03-03 22:22:09 +00:00
Bill Wendling
8d64999daf
This is the initial check-in for adding register scavenging to PPC. (Currently,
...
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.
llvm-svn: 47863
2008-03-03 22:19:16 +00:00
Devang Patel
d0d7028a2b
s/isReturnStruct()/hasStructRetAttr()/g
...
llvm-svn: 47857
2008-03-03 21:46:28 +00:00
Chris Lattner
f818270d43
another random note
...
llvm-svn: 47831
2008-03-02 19:29:42 +00:00
Chris Lattner
f2a9b32eec
add a note
...
llvm-svn: 47830
2008-03-02 19:27:34 +00:00
Chris Lattner
299977b5ca
Evan implemented these.
...
llvm-svn: 47828
2008-03-02 18:05:14 +00:00
Chris Lattner
4c67781884
Evan implemented this.
...
llvm-svn: 47827
2008-03-02 17:56:29 +00:00
Chris Lattner
963b3c9039
add support for lvsl, fixing PR1481
...
llvm-svn: 47825
2008-03-02 08:54:27 +00:00
Chris Lattner
fdcd03cc98
add support for the sse.cmp.* intrinsics, which fixes sse.isamax with the CBE.
...
llvm-svn: 47824
2008-03-02 08:47:13 +00:00
Chris Lattner
7196bf5358
refactor intrinsic handling code out into its own method.
...
llvm-svn: 47823
2008-03-02 08:29:41 +00:00
Chris Lattner
75c409057a
fix printing of undef vectors, this fixes "simple" and "build" in UnitTests/Vector.
...
Now they all pass.
llvm-svn: 47820
2008-03-02 08:14:45 +00:00
Chris Lattner
d8eeb6b1c8
insertelement got the wrong operands.
...
llvm-svn: 47819
2008-03-02 08:10:16 +00:00
Chris Lattner
e9aa391b61
Several changes:
...
* Simplify handling of byval, making it easier to understand and more
consistent. This fixes PR2065.
* Clean up and simplify handling of GEPs. I can actually understand it now!
* Implement support for GEP'ing into vectors, this fixes
SingleSource/UnitTests/Vector/build2 among others.
llvm-svn: 47818
2008-03-02 08:07:24 +00:00
Chris Lattner
78f255dca8
Fix a bug I introduced in constant array and constant vector handling.
...
llvm-svn: 47816
2008-03-02 05:46:57 +00:00
Chris Lattner
96469b446d
implement shufflevector.
...
llvm-svn: 47815
2008-03-02 05:41:07 +00:00
Chris Lattner
18c26f3dad
implement extractelement.
...
llvm-svn: 47812
2008-03-02 03:57:08 +00:00
Chris Lattner
72e898e589
implement insertelement.
...
llvm-svn: 47811
2008-03-02 03:52:39 +00:00
Chris Lattner
85243c2223
respect isSigned for vector types, fixing sdiv of vectors etc.
...
llvm-svn: 47810
2008-03-02 03:41:23 +00:00
Chris Lattner
980424b55c
print the attribute in the right place, this fixes function returning vectors.
...
llvm-svn: 47809
2008-03-02 03:39:43 +00:00
Chris Lattner
112819e1e6
vector types are simple types. This fixes div/rem of vectors.
...
llvm-svn: 47807
2008-03-02 03:33:31 +00:00
Chris Lattner
8eddd5055d
Print vector types appropriately. This gets basic vector code working
...
(PR1126)
llvm-svn: 47806
2008-03-02 03:29:50 +00:00
Chris Lattner
c5f37fc11d
rename PT -> VT for VectorTypes.
...
llvm-svn: 47805
2008-03-02 03:18:46 +00:00
Chris Lattner
a70385185e
Print i32/i64 integer constants as 1u instead of ((unsigned int)1).
...
Use dyn_cast better.
llvm-svn: 47804
2008-03-02 03:16:38 +00:00
Chris Lattner
38a684c0c9
Move pr717 to here.
...
llvm-svn: 47803
2008-03-02 02:51:40 +00:00
Andrew Lenharth
ba7f925582
good catch anton
...
llvm-svn: 47800
2008-03-01 23:18:21 +00:00
Andrew Lenharth
f6c220738c
make CAS work
...
llvm-svn: 47799
2008-03-01 22:27:48 +00:00
Andrew Lenharth
b91c664226
all but CAS working on x86
...
llvm-svn: 47798
2008-03-01 21:52:34 +00:00
Andrew Lenharth
ad29a49169
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
...
llvm-svn: 47795
2008-03-01 13:37:02 +00:00
Anton Korobeynikov
875da2420a
Use enumeration for preffered EH dwarf encoding reason
...
llvm-svn: 47770
2008-02-29 22:09:08 +00:00
Anders Carlsson
236f4dff95
Use the correct instruction encodings for the 64-bit MMX movd.
...
llvm-svn: 47740
2008-02-29 01:35:12 +00:00
Evan Cheng
ea1f2d1110
Added option -align-loops=<true/false> to disable loop aligner pass.
...
llvm-svn: 47736
2008-02-28 23:29:57 +00:00
Dale Johannesen
310201ba32
Interface of getByValTypeAlignment differed between
...
generic & x86 versions; change generic to follow x86
and improve comments. Add PPC version (not right
for non-Darwin.)
llvm-svn: 47734
2008-02-28 22:31:51 +00:00
Lauro Ramos Venancio
a6e28675f3
Initialize TextAlignFillValue. Fix revision 47703.
...
llvm-svn: 47732
2008-02-28 22:14:09 +00:00
Lauro Ramos Venancio
ea557cc68e
Avoid collisions in value names.
...
llvm-svn: 47725
2008-02-28 20:26:04 +00:00
Chris Lattner
f0329b6170
add a note
...
llvm-svn: 47720
2008-02-28 17:21:27 +00:00
Evan Cheng
e1d3e0958b
Set to default: x86 no longer fold and into test if it has more than one use.
...
llvm-svn: 47711
2008-02-28 07:46:38 +00:00
Chris Lattner
c1851542a5
Sparc backend doesn't support debug info yet, mark the nodes as expand. This fixes a crash on
...
test/DebugInfo/funccall.ll
llvm-svn: 47709
2008-02-28 05:54:25 +00:00
Chris Lattner
f989deed26
Fix CodeGen/Generic/storetrunc-fp.ll on sparc, PR2105
...
llvm-svn: 47707
2008-02-28 05:48:04 +00:00
Chris Lattner
0f0fc0ccd4
fix CodeGen/Generic/2008-01-25-dag-combine-mul.ll on sparc, PR2105
...
llvm-svn: 47706
2008-02-28 05:44:20 +00:00
Chris Lattner
dab318a206
target-indep codegen memcpy lowering issue.
...
llvm-svn: 47705
2008-02-28 05:34:27 +00:00
Chris Lattner
33b1f491a0
Add a random not very important note
...
llvm-svn: 47704
2008-02-28 04:52:59 +00:00
Evan Cheng
f8b1257d2e
Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.
...
llvm-svn: 47703
2008-02-28 00:43:03 +00:00
Eli Friedman
912a1d48e1
A few more small things I've run into.
...
llvm-svn: 47702
2008-02-28 00:21:43 +00:00
Anton Korobeynikov
f8d5799001
EHPreferredDataFormat hook for PPC targets. Looks like Darwin
...
uses the same encoding everywhere. Linux FIXME'ed.
llvm-svn: 47701
2008-02-27 23:49:15 +00:00
Anton Korobeynikov
7bd4b77e30
Preparation step for some cleanup/generalization in EH information emission:
...
provide TAI hook for selection of EH data emission format. Currently unused.
llvm-svn: 47699
2008-02-27 23:33:50 +00:00
Dan Gohman
5d96a06b0b
Don't hard-code the mask size to be 32, which is incorrect on ppc64
...
and was causing aborts with the new APInt changes. This may also be
fixing an obscure ppc64 bug.
llvm-svn: 47692
2008-02-27 21:12:32 +00:00
Evan Cheng
08f11a37d7
This is done.
...
llvm-svn: 47688
2008-02-27 20:26:32 +00:00
Bill Wendling
2cae66e28b
Final de-tabification.
...
llvm-svn: 47663
2008-02-27 06:33:05 +00:00
Chris Lattner
1f46cc2345
Make X86TargetLowering::LowerSINT_TO_FP return without creating a dead
...
stack slot and store if the SINT_TO_FP is actually legal. This allows
us to compile:
double a(double b) {return (unsigned)b;}
to:
_a:
cvttsd2siq %xmm0, %rax
movl %eax, %eax
cvtsi2sdq %rax, %xmm0
ret
instead of:
_a:
subq $8, %rsp
cvttsd2siq %xmm0, %rax
movl %eax, %eax
cvtsi2sdq %rax, %xmm0
addq $8, %rsp
ret
crazy.
llvm-svn: 47660
2008-02-27 05:57:41 +00:00
Chris Lattner
f19162a87f
this code is correct but strange looking ;-)
...
llvm-svn: 47659
2008-02-27 05:48:44 +00:00
Chris Lattner
bc686e546a
Compile x86-64-and-mask.ll into:
...
_test:
movl %edi, %eax
ret
instead of:
_test:
movl $4294967295, %ecx
movq %rdi, %rax
andq %rcx, %rax
ret
It would be great to write this as a Pat pattern that used subregs
instead of a 'pseudo' instruction, but I don't know how to do that
in td files.
llvm-svn: 47658
2008-02-27 05:47:54 +00:00
Evan Cheng
7553230e3a
Spiller now remove unused spill slots.
...
llvm-svn: 47657
2008-02-27 03:04:06 +00:00
Dan Gohman
938e74654b
Convert the last remaining users of the non-APInt form of
...
ComputeMaskedBits to use the APInt form, and remove the
non-APInt form.
llvm-svn: 47654
2008-02-27 01:23:58 +00:00
Chris Lattner
a81d716e0c
add a note
...
llvm-svn: 47652
2008-02-27 01:17:20 +00:00
Arnold Schwaighofer
642dc28734
Refactor according to Evan's and Anton's suggestions.
...
llvm-svn: 47635
2008-02-26 22:21:54 +00:00
Bill Wendling
8fb166bf6c
Rename PrintableName to Name.
...
llvm-svn: 47629
2008-02-26 21:47:57 +00:00
Bill Wendling
50f5c4be14
Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
...
would have been a Godsend here!
llvm-svn: 47625
2008-02-26 21:11:01 +00:00
Arnold Schwaighofer
7466041819
Correct function comments.
...
llvm-svn: 47606
2008-02-26 17:50:59 +00:00
Bill Wendling
16cba10ae6
De-tabify
...
llvm-svn: 47600
2008-02-26 10:57:23 +00:00
Arnold Schwaighofer
ddebd886dc
Add support for intermodule tail calls on x86/32bit with
...
GOT-style position independent code. Before only tail calls to
protected/hidden functions within the same module were optimized.
Now all function calls are tail call optimized.
llvm-svn: 47594
2008-02-26 10:21:54 +00:00
Arnold Schwaighofer
6383666085
Change the lowering of arguments for tail call optimized
...
calls. Before arguments that could overwrite each other were
explicitly lowered to a stack slot, not giving the register allocator
a chance to optimize. Now a sequence of copyto/copyfrom virtual
registers ensures that arguments are loaded in (virtual) registers
before they are lowered to the stack slot (and might overwrite each
other). Also parameter stack slots are marked mutable for
(potentially) tail calling functions.
llvm-svn: 47593
2008-02-26 09:19:59 +00:00
Dan Gohman
b8e7fea22f
Revert the assert for MUL_LOHI with an unused high result; Chris
...
pointed out that this isn't correct at -O0.
llvm-svn: 47575
2008-02-25 22:43:48 +00:00