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Commit Graph

98186 Commits

Author SHA1 Message Date
David Blaikie
b4fa4b53a5 DebugInfo: Include the section and start-of-section label in the unit
This is a precursor to moving type units into the correct (debug_types)
section with comdat groups and full type unit headers.

llvm-svn: 196615
2013-12-06 22:14:48 +00:00
Duncan P. N. Exon Smith
de77610c42 Don't use isNullValue to evaluate ConstantExpr
ConstantExpr can evaluate to false even when isNullValue gives false.

Fixes PR18143.

llvm-svn: 196611
2013-12-06 21:48:36 +00:00
Yuchen Wu
205ea92d55 llvm-cov: Regenerated gcov files with r195513 changes.
llvm-svn: 196609
2013-12-06 21:33:50 +00:00
David Peixotto
ff3935d81d Integrated assembler incorrectly lexes ARM-style comments
The integrated assembler fails to properly lex arm comments when
they are adjacent to an identifier in the input stream. The reason
is that the arm comment symbol '@' is also used as symbol variant in
other assembly languages so when lexing an identifier it allows the
'@' symbol as part of the identifier.

Example:
  $ cat comment.s
  foo:
    add r0, r0@got to parse this as a comment

  $ llvm-mc -triple armv7 comment.s
  comment.s:4:18: error: unexpected token in argument list
    add r0, r0@got to parse this as a comment
                   ^
This should be parsed as correctly as `add r0, r0`.

This commit modifes the assembly lexer to not include the '@' symbol
in identifiers when lexing for targets that use '@' for comments.

llvm-svn: 196607
2013-12-06 20:35:58 +00:00
Rafael Espindola
ce238ae45e micro optimization: isSizedDerivedType is only called with arrays, vectors and structs.
llvm-svn: 196604
2013-12-06 20:12:19 +00:00
David Blaikie
c7180b55dc DwarfDebug: Walk skeletons during fission pubtypes/pubnames emission
This more accurately represents the actual walk - pubnames/pubtypes are
emitted into the .o, not the .dwo, and reference the skeletons not the
full units.

Use the newly established ID->index invariant to lookup the underlying
full unit to retrieve its public names and types.

llvm-svn: 196601
2013-12-06 19:38:49 +00:00
David Blaikie
24e2ea8a35 DebugInfo: Ensure unit IDs (for non-skeletal units) match thein index in the list
This simplifies reasoning about the code and enables simple navigation
from a skeleton to its full unit. (currently there are no type unit
skeletons, so the skeleton list doesn't have the same ID == index
property)

Eventually we should get rid of this ID and just store the labels we
need as the IDs are allowing this code to create difficult to
manage/understand associations (loops over non-skeletal units are
implicitly referencing their skeletal units during pub* emission, for
example). It may be necessary to have some kind of skeleton->full unit
association and a more direct pointer or similar device would be
preferable than an index.

llvm-svn: 196600
2013-12-06 19:38:46 +00:00
Weiming Zhao
f90fe366af Bug 18149: [AArch32] VSel instructions has no ARMCC field
The current peephole optimizing for compare inst assumes an instr that
uses CPSR has an MO for ARM Cond code.However, for VSEL instructions
(vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do
they support the modification of Cond Code.

llvm-svn: 196588
2013-12-06 17:56:48 +00:00
Andrew Trick
3981c065dd comment grammar
llvm-svn: 196585
2013-12-06 17:19:20 +00:00
Cameron McInally
ca9f2bc25b Update AVX512 vector blend intrinsic names.
llvm-svn: 196581
2013-12-06 13:35:35 +00:00
Richard Sandiford
344b7e5ec3 [SystemZ] Use LOAD AND TEST for comparisons with -0
...since it os equivalent to comparison with +0.

llvm-svn: 196580
2013-12-06 09:59:12 +00:00
Richard Sandiford
f6544bf49a [SystemZ] Extend the use of C(L)GFR
instcombine prefers to put extended operands first, so this patch
handles that case for C(L)GFR.

llvm-svn: 196579
2013-12-06 09:56:50 +00:00
Richard Sandiford
9be3fcae69 [SystemZ] Optimize selects between 0 and -1
Since z has no setcc instruction as such, the choice of setBooleanContents
is a bit arbitrary.  Currently it's set to ZeroOrOneBooleanContent,
so we produced a branch-free form when selecting between 0 and 1,
but not when selecting between 0 and -1.  This patch handles the latter
case too.

At some point I'd like to measure whether it's better to use conditional
moves for constant selects on z196, but that's future work.

llvm-svn: 196578
2013-12-06 09:53:09 +00:00
Kostya Serebryany
f0897919b4 [asan] fix ndebug build with strict warnings (-Wunused-variable)
llvm-svn: 196574
2013-12-06 09:26:09 +00:00
Kostya Serebryany
fc32a3e5d2 [asan] rewrite asan's stack frame layout
Summary:
Rewrite asan's stack frame layout.
First, most of the stack layout logic is moved into a separte file
to make it more testable and (potentially) useful for other projects.
Second, make the frames more compact by using adaptive redzones
(smaller for small objects, larger for large objects).
Third, try to minimized gaps due to large alignments (this is hypothetical since
today we don't see many stack vars aligned by more than 32).

The frames indeed become more compact, but I'll still need to run more benchmarks
before committing, but I am sking for review now to get early feedback.

This change will be accompanied by a trivial change in compiler-rt tests
to match the new frame sizes.

Reviewers: samsonov, dvyukov

Reviewed By: samsonov

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2324

llvm-svn: 196568
2013-12-06 09:00:17 +00:00
Daniel Jasper
8cd731979d Fix bug introduced in r196517.
Not only does it trigger -Wparentheses, I think the assert actually
relies on incorrect operator precedence.

Also, the grammar as questionable, but I might not know enough about the
problem at hand.

llvm-svn: 196567
2013-12-06 08:58:22 +00:00
Eric Christopher
24dfc97f90 Fix an index array check.
Patch by Marius Wachtler.

llvm-svn: 196561
2013-12-06 02:45:24 +00:00
Eric Christopher
64a24813ab Fix a pair of array index checks.
Patch by Marius Wachtler.

llvm-svn: 196560
2013-12-06 02:33:38 +00:00
Rui Ueyama
f6ac3eeb3e Object/COFF: Add export table entry structs.
Differential Revision: http://llvm-reviews.chandlerc.com/D2335

llvm-svn: 196556
2013-12-06 01:06:04 +00:00
Juergen Ributzka
47e3315816 [Stackmap] Update stackmap unit test to use AnyRegCC.
llvm-svn: 196552
2013-12-06 00:28:54 +00:00
Reed Kotler
3658d0ec5d Delete dead code.
llvm-svn: 196551
2013-12-06 00:13:50 +00:00
Yi Jiang
0bd0569be5 Apply transformation on OS X 10.9+ and iOS 7.0+: pow(10, x) ―> __exp10(x)
llvm-svn: 196544
2013-12-05 22:42:50 +00:00
Yuchen Wu
9b66fd728d llvm-cov: Further improved error messages.
llvm-svn: 196542
2013-12-05 22:02:33 +00:00
Yuchen Wu
d29823e2c3 llvm-cov: Conformed headers.
llvm-svn: 196541
2013-12-05 22:02:29 +00:00
Renato Golin
7c406f2a69 Move test to X86 dir
Test is platform independent, but I don't want to force vector-width, or
that could spoil the pragma test.

llvm-svn: 196539
2013-12-05 21:45:39 +00:00
Renato Golin
a4d4a4c44f Add #pragma vectorize enable/disable to LLVM
The intended behaviour is to force vectorization on the presence
of the flag (either turn on or off), and to continue the behaviour
as expected in its absence. Tests were added to make sure the all
cases are covered in opt. No tests were added in other tools with
the assumption that they should use the PassManagerBuilder in the
same way.

This patch also removes the outdated -late-vectorize flag, which was
on by default and not helping much.

The pragma metadata is being attached to the same place as other loop
metadata, but nothing forbids one from attaching it to a function
(to enable #pragma optimize) or basic blocks (to hint the basic-block
vectorizers), etc. The logic should be the same all around.

Patches to Clang to produce the metadata will be produced after the
initial implementation is agreed upon and committed. Patches to other
vectorizers (such as SLP and BB) will be added once we're happy with
the pass manager changes.

llvm-svn: 196537
2013-12-05 21:20:02 +00:00
Aditya Nandakumar
178353e71f Check hint registers for interference only once before evictions
llvm-svn: 196536
2013-12-05 21:18:40 +00:00
Ana Pazos
a6ef726750 Implemented vget/vset_lane_f16 intrinsics
llvm-svn: 196533
2013-12-05 21:07:49 +00:00
Yuchen Wu
dda2c44c38 llvm-cov: Changed extension from .llcov to .gcov.
llvm-svn: 196530
2013-12-05 20:45:36 +00:00
Matt Arsenault
f4228e2204 Revert part of GCC warning fix to fix debug build.
The typedef is used inside the DEBUG(), and apparently can't be moved
inside of it.

llvm-svn: 196528
2013-12-05 20:02:18 +00:00
Matt Arsenault
57be52c610 Fix minor GCC warnings.
Unused typedefs and unused variables.

llvm-svn: 196526
2013-12-05 19:37:36 +00:00
Michael Gottesman
f2e7969964 Change std::deque => std::vector. No functionality change.
There is no reason to use std::deque here over std::vector. Thus given the
performance differences inbetween the two it makes sense to change deque to
vector.

llvm-svn: 196524
2013-12-05 18:42:12 +00:00
Yunzhong Gao
f3138b60c3 Document that dllexported symbols are preserved by optimization passes.
llvm-svn: 196523
2013-12-05 18:37:54 +00:00
Rafael Espindola
2ad993fb14 Fix non-deterministic behavior.
We use CSEBlocks to initialize a worklist:

SmallVector<BasicBlock *, 8> CSEWorkList(CSEBlocks.begin(), CSEBlocks.end());

so it must have a deterministic order.

llvm-svn: 196520
2013-12-05 18:28:01 +00:00
Eric Christopher
e62b076d5b Rename DwarfUnits to DwarfFile to help avoid some naming confusion.
llvm-svn: 196519
2013-12-05 18:06:10 +00:00
Andrew Trick
7eb7f7648b MI-Sched: Model "reserved" processor resources.
This allows a target to use MI-Sched as an in-order scheduler that
will model strict resource conflicts without defining a processor
itinerary. Instead, the target can now use the new per-operand machine
model and define in-order resources with BufferSize=0. For example,
this would allow restricting the type of operations that can be formed
into a dispatch group. (Normally NumMicroOps is sufficient to enforce
dispatch groups).

If the intent is to model latency in in-order pipeline, as opposed to
resource conflicts, then a resource with BufferSize=1 should be
defined instead.

This feature is only casually tested as there are no in-tree targets
using it yet. However, Hal will be experimenting with POWER7.

llvm-svn: 196517
2013-12-05 17:56:02 +00:00
Andrew Trick
192311ab9a MI-Sched: handle latency of in-order operations with the new machine model.
The per-operand machine model allows the target to define "unbuffered"
processor resources. This change is a quick, cheap way to model stalls
caused by the latency of operations that use such resources. This only
applies when the processor's micro-op buffer size is non-zero
(Out-of-Order). We can't precisely model in-order stalls during
out-of-order execution, but this is an easy and effective
heuristic. It benefits cortex-a9 scheduling when using the new
machine model, which is not yet on by default.

MI-Sched for armv7 was evaluated on Swift (and only not enabled because
of a performance bug related to predication). However, we never
evaluated Cortex-A9 performance on MI-Sched in its current form. This
change adds MI-Sched functionality to reach performance goals on
A9. The only remaining change is to allow MI-Sched to run as a PostRA
pass.

I evaluated performance using a set of options to estimate the performance impact once MI sched is default on armv7:
-mcpu=cortex-a9 -disable-post-ra -misched-bench -scheditins=false

For a simple saxpy loop I see a 1.7x speedup. Here are the llvm-testsuite results:
(min run time over 2 runs, filtering tiny changes)

Speedups:
| Benchmarks/BenchmarkGame/recursive         |  52.39% |
| Benchmarks/VersaBench/beamformer           |  20.80% |
| Benchmarks/Misc/pi                         |  19.97% |
| Benchmarks/Misc/mandel-2                   |  19.95% |
| SPEC/CFP2000/188.ammp                      |  18.72% |
| Benchmarks/McCat/08-main/main              |  18.58% |
| Benchmarks/Misc-C++/Large/sphereflake      |  18.46% |
| Benchmarks/Olden/power                     |  17.11% |
| Benchmarks/Misc-C++/mandel-text            |  16.47% |
| Benchmarks/Misc/oourafft                   |  15.94% |
| Benchmarks/Misc/flops-7                    |  14.99% |
| Benchmarks/FreeBench/distray               |  14.26% |
| SPEC/CFP2006/470.lbm                       |  14.00% |
| mediabench/mpeg2/mpeg2dec/mpeg2decode      |  12.28% |
| Benchmarks/SmallPT/smallpt                 |  10.36% |
| Benchmarks/Misc-C++/Large/ray              |   8.97% |
| Benchmarks/Misc/fp-convert                 |   8.75% |
| Benchmarks/Olden/perimeter                 |   7.10% |
| Benchmarks/Bullet/bullet                   |   7.03% |
| Benchmarks/Misc/mandel                     |   6.75% |
| Benchmarks/Olden/voronoi                   |   6.26% |
| Benchmarks/Misc/flops-8                    |   5.77% |
| Benchmarks/Misc/matmul_f64_4x4             |   5.19% |
| Benchmarks/MiBench/security-rijndael       |   5.15% |
| Benchmarks/Misc/flops-6                    |   5.10% |
| Benchmarks/Olden/tsp                       |   4.46% |
| Benchmarks/MiBench/consumer-lame           |   4.28% |
| Benchmarks/Misc/flops-5                    |   4.27% |
| Benchmarks/mafft/pairlocalalign            |   4.19% |
| Benchmarks/Misc/himenobmtxpa               |   4.07% |
| Benchmarks/Misc/lowercase                  |   4.06% |
| SPEC/CFP2006/433.milc                      |   3.99% |
| Benchmarks/tramp3d-v4                      |   3.79% |
| Benchmarks/FreeBench/pifft                 |   3.66% |
| Benchmarks/Ptrdist/ks                      |   3.21% |
| Benchmarks/Adobe-C++/loop_unroll           |   3.12% |
| SPEC/CINT2000/175.vpr                      |   3.12% |
| Benchmarks/nbench                          |   2.98% |
| SPEC/CFP2000/183.equake                    |   2.91% |
| Benchmarks/Misc/perlin                     |   2.85% |
| Benchmarks/Misc/flops-1                    |   2.82% |
| Benchmarks/Misc-C++-EH/spirit              |   2.80% |
| Benchmarks/Misc/flops-2                    |   2.77% |
| Benchmarks/NPB-serial/is                   |   2.42% |
| Benchmarks/ASC_Sequoia/CrystalMk           |   2.33% |
| Benchmarks/BenchmarkGame/n-body            |   2.28% |
| Benchmarks/SciMark2-C/scimark2             |   2.27% |
| Benchmarks/Olden/bh                        |   2.03% |
| skidmarks10/skidmarks                      |   1.81% |
| Benchmarks/Misc/flops                      |   1.72% |

Slowdowns:
| Benchmarks/llubenchmark/llu                | -14.14% |
| Benchmarks/Polybench/stencils/seidel-2d    |  -5.67% |
| Benchmarks/Adobe-C++/functionobjects       |  -5.25% |
| Benchmarks/Misc-C++/oopack_v1p8            |  -5.00% |
| Benchmarks/Shootout/hash                   |  -2.35% |
| Benchmarks/Prolangs-C++/ocean              |  -2.01% |
| Benchmarks/Polybench/medley/floyd-warshall |  -1.98% |
| Polybench/linear-algebra/kernels/3mm       |  -1.95% |
| Benchmarks/McCat/09-vor/vor                |  -1.68% |

llvm-svn: 196516
2013-12-05 17:55:58 +00:00
Andrew Trick
24a9064bbd Machine model comments. Explain a ProcessorUnit's BufferSize.
llvm-svn: 196515
2013-12-05 17:55:53 +00:00
Andrew Trick
9518dde658 Fix the A9 machine model. VTRN writes two registers.
llvm-svn: 196514
2013-12-05 17:55:49 +00:00
Andrew Trick
6bd4b82476 comment typo and reformat
llvm-svn: 196513
2013-12-05 17:55:47 +00:00
Rafael Espindola
eb989f9afc Add a default constructor to get deterministic behavior.
Should fix the msan and valgrind bots.

llvm-svn: 196509
2013-12-05 16:21:17 +00:00
Arnold Schwaighofer
120880c780 SLPVectorizer: An in-tree vectorized entry cannot also be a scalar external use
We were creating external uses for scalar values in MustGather entries that also
had a ScalarToTreeEntry (they also are present in a vectorized tuple). This
meant we would keep a value 'alive' as a scalar and vectorized causing havoc.
This is not necessary because when we create a MustGather vector we explicitly
create external uses entries for the insertelement instructions of the
MustGather vector elements.

Fixes PR18129.

radar://15582184

llvm-svn: 196508
2013-12-05 15:14:40 +00:00
Kostya Serebryany
eb57b3e248 [tsan] fix PR18146: sometimes a variable written into vptr could have an integer type (after other optimizations)
llvm-svn: 196507
2013-12-05 15:03:02 +00:00
Justin Holewinski
925169cb4e [NVPTX] Fix off-by-one error when creating the VT list for an SDNode
llvm-svn: 196503
2013-12-05 12:58:00 +00:00
Alexey Samsonov
66f3fd41ae Add forgotten header guards
llvm-svn: 196500
2013-12-05 12:52:32 +00:00
Matheus Almeida
b651cddc0c [mips] Small code generation improvement for conditional operator (select)
in case the operands are constants and its difference is |1|.
It should be possible in those cases to rematerialize the result using
MIPS's slt and similar instructions.

The small update to some of the tests in cmov.ll, sel1c.ll and sel2c.ll was needed
otherwise the optimization implemented in this patch would have been triggered
(difference between the operands was 1) and that would have changed the semantic
of the tests.

llvm-svn: 196498
2013-12-05 12:07:05 +00:00
Matheus Almeida
adbbd704d1 [mips] Add some comments related to the optimization performed in performSELECTCombine.
The structure of the code was slightly modified so that the next patch is easier to read/review.

No functional changes.

llvm-svn: 196496
2013-12-05 11:56:56 +00:00
Matheus Almeida
f0fc3cf095 [mips][msa] Fix issue with immediate fields of LD/ST instructions
not being correctly encoded/decoded.
In more detail, immediate fields of LD/ST instructions should be
divided/multiplied by the size of the data format before encoding and
after decoding, respectively.

llvm-svn: 196494
2013-12-05 11:06:22 +00:00
Tim Northover
d04bb11dd7 ARM: fix yet another stack-folding bug
We were trying to fold the stack adjustment into the wrong instruction in the
situation where the entire basic-block was epilogue code. Really, it can only
ever be valid to do the folding precisely where the "add sp, ..." would be
placed so there's no need for a separate iterator to track that.

Should fix PR18136.

llvm-svn: 196493
2013-12-05 11:02:02 +00:00
David Blaikie
042cd582a0 DwarfDebug/DwarfUnit: Push abbreviation structures down into DwarfUnits to reduce duplication
llvm-svn: 196479
2013-12-05 07:43:55 +00:00