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Author SHA1 Message Date
Duraid Madina
b8dfae92e9 oops, this stopped us turning movl r4=0xFFFFFFFF;; and rX, r4 into zxt4 
llvm-svn: 21299
 2005-04-14 10:06:35 +00:00
Nate Begeman
604895b03c Implement multi-way branches through logical ops on condition registers. 
This can generate considerably shorter code, reducing the size of crafty
by almost 1%.  Also fix the printing of mcrf.  The code is currently
disabled until it gets a bit more testing, but should work as-is.

llvm-svn: 21298
 2005-04-14 09:45:08 +00:00
Nate Begeman
ce63e383b8 Add a couple missing transforms in getSetCC that were triggering assertions 
in the PPC Pattern ISel

llvm-svn: 21297
 2005-04-14 08:56:52 +00:00
Duraid Madina
eb4c15b42c we have zextloads, not sextloads! 
llvm-svn: 21296
 2005-04-14 08:37:32 +00:00
Nate Begeman
b707ec16b4 Add the necessary support to codegen condition register logical ops with 
register allocated condition registers.  Make sure that the printed
  output is gas compatible.

llvm-svn: 21295
 2005-04-14 03:20:38 +00:00
Nate Begeman
99a9840b56 Start allocating condition registers. Almost all explicit uses of CR0 are 
now gone.  Next step is to get rid of the remaining ones and then start
allocating bools to CRs where appropriate.

llvm-svn: 21294
 2005-04-13 23:15:44 +00:00
Nate Begeman
ae49d52006 Implement the fold shift X, zext(Y) -> shift X, Y at the target level, 
where it is safe to do so.

llvm-svn: 21293
 2005-04-13 22:14:14 +00:00
Nate Begeman
33b835c553 Add CodeGen tests for the recent SelectionDAG transforms 
llvm-svn: 21292
 2005-04-13 21:45:13 +00:00
Nate Begeman
20b3399465 Disbale the broken fold of shift + sz[ext] for now 
Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
  always produces zero or one.

llvm-svn: 21291
 2005-04-13 21:23:31 +00:00
Chris Lattner
89f7e115a4 fix an infinite loop 
llvm-svn: 21289
 2005-04-13 20:06:29 +00:00
Chris Lattner
475fe85ddf fix some serious miscompiles on ia64, alpha, and ppc 
llvm-svn: 21288
 2005-04-13 19:53:40 +00:00
Chris Lattner
03d675414e avoid work when possible, perhaps fix the problem nate and andrew are seeing 
with != 0 comparisons vanishing.

llvm-svn: 21287
 2005-04-13 19:41:05 +00:00
Andrew Lenharth
cbf7a52768 WOW, function calls still seem to work after this. 
llvm-svn: 21286
 2005-04-13 17:17:28 +00:00
Andrew Lenharth
d1fee6d24a prepare for func call optimization 
llvm-svn: 21285
 2005-04-13 16:19:50 +00:00
Andrew Lenharth
69541f896f regression case for faster call sequence 
llvm-svn: 21284
 2005-04-13 16:16:01 +00:00
Andrew Lenharth
18f93d4455 check that casts still use zap 
llvm-svn: 21283
 2005-04-13 13:00:16 +00:00
Duraid Madina
b9d2d9ac63 * add the shladd instruction 
* fold left shifts of 1, 2, 3 or 4 bits into adds

  This doesn't save much now, but should get a serious workout once
  multiplies by constants get converted to shift/add/sub sequences.
  Hold on! :)

llvm-svn: 21282
 2005-04-13 06:12:04 +00:00
Andrew Lenharth
ec33ab6a2f add matches for SxADDL and company, as well as simplify the SxADDQ code 
llvm-svn: 21281
 2005-04-13 05:19:55 +00:00
Chris Lattner
9540cf8c7e Implement expansion of unsigned i64 -> FP. 
Note that this probably only works for little endian targets, but is enough
to get siod working :)

llvm-svn: 21280
 2005-04-13 05:09:42 +00:00
Duraid Madina
67e553e521 * if ANDing with a constant of the form: 
0x00000..00FFF..FF
      ^      ^
      ^      ^
    any number of
    0's followed by
    some number of
    1's

    then we use dep.z to just paste zeros over the input. For the special
    cases where this is zxt1/zxt2/zxt4, we use those instructions instead,
    because we're all about readability!!!
    that's what it's about!! readability!

  *twitch* ;D

llvm-svn: 21279
 2005-04-13 04:50:54 +00:00
Andrew Lenharth
9be54f8a6a added s4addl matching test 
llvm-svn: 21277
 2005-04-13 04:41:06 +00:00
Andrew Lenharth
510db15268 added all flavors of zap for anding 
llvm-svn: 21276
 2005-04-13 03:47:03 +00:00
Chris Lattner
1a6247ff51 Make expansion of uint->fp cast assert out instead of infinitely recurse. 
llvm-svn: 21275
 2005-04-13 03:42:14 +00:00
Chris Lattner
85c6a7bed0 Fix some mysteriously missing {}'s which cause the miscompilation of 
Olden/mst, Ptrdist/bc, Obsequi, etc.

llvm-svn: 21274
 2005-04-13 03:29:53 +00:00
Chris Lattner
63450e87d9 add back the optimization that Nate added for shl X, (zext_inreg y) 
llvm-svn: 21273
 2005-04-13 02:58:13 +00:00
Chris Lattner
759afe07d7 Oops, remove these too. 
llvm-svn: 21272
 2005-04-13 02:47:57 +00:00
Chris Lattner
8489ac991d remove one more occurance of this that snuck in 
llvm-svn: 21271
 2005-04-13 02:46:17 +00:00
Chris Lattner
5fdb103328 Remove support for ZERO_EXTEND_INREG. This pessimizes code, genering stuff 
like this:

        ldah $1,1($31)
        lda $1,-1($1)
        and $0,$1,$24

instead of this:

        zap $0,252,$24

To get this back, the selector should recognize the ISD::AND case where this
happens and emit the appropriate ZAP instruction.

llvm-svn: 21270
 2005-04-13 02:43:40 +00:00
Chris Lattner
a2e92e69da Remove special handling of ZERO_EXTEND_INREG. This pessimizes code, causing 
things like this:

       mov r9 = 65535;;
       and r8 = r8, r9;;

To be emitted instead of:

        zxt2 r8 = r8;;

To get this back, the selector for ISD::AND should recognize this case.

llvm-svn: 21269
 2005-04-13 02:41:52 +00:00
Chris Lattner
26c7c9150a Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit 
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.

llvm-svn: 21268
 2005-04-13 02:40:26 +00:00
Chris Lattner
f25fefd9cf Z_E_I is gone 
llvm-svn: 21267
 2005-04-13 02:39:05 +00:00
Chris Lattner
4f188f949c Instead of making ZERO_EXTEND_INREG nodes, use the helper method in 
SelectionDAG to do the job with AND.  Don't legalize Z_E_I anymore as
it is gone

llvm-svn: 21266
 2005-04-13 02:38:47 +00:00
Chris Lattner
bce0030a88 Remove all foldings of ZERO_EXTEND_INREG, moving them to work for AND nodes 
instead.  OVerall, this increases the amount of folding we can do.

llvm-svn: 21265
 2005-04-13 02:38:18 +00:00
Chris Lattner
41aabb9427 Add a new helper method which returns the and that is equivalent to what 
ZERO_EXTEND_INREG was.

llvm-svn: 21264
 2005-04-13 02:37:19 +00:00
Chris Lattner
f5fe51581b Remove the ZERO_EXTEND_INREG node which is redundant with AND 
llvm-svn: 21263
 2005-04-13 02:36:41 +00:00
Nate Begeman
38d8248a9e Fold shift x, [sz]ext(y) -> shift x, y 
llvm-svn: 21262
 2005-04-12 23:32:28 +00:00
Nate Begeman
a56527ea5f Fold shift by size larger than type size to undef 
Make llvm undef values generate ISD::UNDEF nodes

llvm-svn: 21261
 2005-04-12 23:12:17 +00:00
Nate Begeman
79c8b8fd1c Implement setcc op, -1 sequences 
Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm

llvm-svn: 21260
 2005-04-12 21:22:28 +00:00
Chris Lattner
58f72ab722 promote extload i1 -> extload i8 
llvm-svn: 21258
 2005-04-12 20:30:10 +00:00
Chris Lattner
7c88662870 add an argument to allow avoiding deleting phi nodes. 
llvm-svn: 21255
 2005-04-12 18:52:14 +00:00
Chris Lattner
ff1eca851a add an argument. 
llvm-svn: 21254
 2005-04-12 18:51:53 +00:00
Chris Lattner
ee06161a63 Get rid of this for_each loop 
llvm-svn: 21253
 2005-04-12 18:51:33 +00:00
Duraid Madina
39fcec1541 * OK, after changing to use liveIn/liveOut instead of IDEFs, 
to avoid redundant mov out3=r44 type instructions, we need to
tell the register allocator the truth about out? registers.

FIXME: unfortunately, since the list of allocatable registers is immutable,
we can't simply 'delete r127' from the allocation order, say, if 'out0' is
used. The only correct thing we can do is have a linear order of regs:

out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127

and slide a 'window' of 96 registers along this line, depending on how many
of the out? regs a function actually uses. The only downside of this is
that the out? registers will be allocated _first_, which makes the
resulting assembly ugly. :( Note this in the README. Hope this gets fixed
soon. :) (note the 3rd person speech there)

llvm-svn: 21252
 2005-04-12 18:42:59 +00:00
Andrew Lenharth
174d44f223 Get rid of idefs for arguments (oops) 
llvm-svn: 21251
 2005-04-12 17:47:57 +00:00
Andrew Lenharth
1b8a8331c9 Get rid of idefs for arguments 
llvm-svn: 21250
 2005-04-12 17:35:16 +00:00
Chris Lattner
be2dceff48 Put out* into the allocation order, allowing the register allocator to 
coallesce moves into outgoing args.

llvm-svn: 21249
 2005-04-12 15:12:51 +00:00
Chris Lattner
37712352c0 Make sure to realize that calls use their argument regs 
llvm-svn: 21248
 2005-04-12 15:12:19 +00:00
Duraid Madina
2821f99f19 stop emitting IDEFs for args - change to using liveIn/liveOut 
llvm-svn: 21247
 2005-04-12 14:54:44 +00:00
Nate Begeman
f96b42f1b6 Initial support for allocation condition registers 
llvm-svn: 21246
 2005-04-12 07:04:16 +00:00
Chris Lattner
f8d9224d8c Fix a crash analyzing MultiSource/Benchmarks/MallocBench/gs 
llvm-svn: 21245
 2005-04-12 03:59:27 +00:00