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14134 Commits

Author SHA1 Message Date
Eric Christopher
63beefefa6 Remove migrated or obsolete tests. 
llvm-svn: 138149
 2011-08-19 23:41:50 +00:00
Devang Patel
e4127d626e Do not use named md nodes to track variables that are completely optimized. This does not scale while doing LTO with debug info. New approach is to include list of variables in the subprogram info directly. 
llvm-svn: 138145
 2011-08-19 23:28:12 +00:00
Jim Grosbach
be94868d66 Thumb parsing and encoding support for NOP. 
The irony is not lost that this is not a completely trivial patchset.

llvm-svn: 138143
 2011-08-19 23:24:36 +00:00
Eric Christopher
acc50c59d7 Remove obsolete test. 
llvm-svn: 138141
 2011-08-19 23:18:12 +00:00
Eric Christopher
4757132347 Remove migrated test. 
llvm-svn: 138140
 2011-08-19 23:18:10 +00:00
Jim Grosbach
969c7a9037 Use regex to remove false dependencies on register allocation. 
llvm-svn: 138137
 2011-08-19 23:10:31 +00:00
Eric Christopher
5ee860b0ca Remove obsolete or migrated tests. 
llvm-svn: 138135
 2011-08-19 23:08:41 +00:00
Jim Grosbach
326e78be7a Thumb assembly parsing and encoding for NEG. 
llvm-svn: 138131
 2011-08-19 22:51:03 +00:00
Jim Grosbach
a97661cac4 Be more lenient on tied operand matching for MUL. 
llvm-svn: 138124
 2011-08-19 22:30:46 +00:00
Bruno Cardoso Lopes
9979e44f1b Re-write part of VEX encoding logic, to be more easy to read! Also fix 
a bug and add a testcase!

llvm-svn: 138123
 2011-08-19 22:27:29 +00:00
Eric Christopher
eab05a72ef Remove tests migrated to clang. 
llvm-svn: 138121
 2011-08-19 22:26:09 +00:00
Eric Christopher
2c909109c5 Remove previously migrated test. 
llvm-svn: 138120
 2011-08-19 22:26:06 +00:00
Jim Grosbach
5481e15390 Update tests. 
llvm-svn: 138116
 2011-08-19 22:19:48 +00:00
Eric Christopher
0514063325 Remove tests migrated to clang or are unnecessary. 
llvm-svn: 138115
 2011-08-19 22:17:09 +00:00
Jim Grosbach
c1186a4afb Thumb assembly parsing and encoding for MVN. 
llvm-svn: 138109
 2011-08-19 22:09:23 +00:00
Jim Grosbach
8e2d4a63dc Thumb assembly parsing and encoding for MUL. 
llvm-svn: 138108
 2011-08-19 22:07:46 +00:00
Eric Christopher
dbd4cacba4 Remove this test. The feature and test have already been migrated to clang. 
llvm-svn: 138101
 2011-08-19 21:51:41 +00:00
Eric Christopher
15ebc094a8 Remove tests migrated to clang. 
llvm-svn: 138100
 2011-08-19 21:51:39 +00:00
Eric Christopher
a3a78f5b56 Remove 2009-09-04-modify-crash.cpp as clang doesn't support 32-bit kext. 
llvm-svn: 138087
 2011-08-19 21:21:28 +00:00
Eric Christopher
fef8e7ac9d Remove migrated tests. 
llvm-svn: 138086
 2011-08-19 21:21:26 +00:00
Eric Christopher
624d962a50 Remove migrated test. 
llvm-svn: 138085
 2011-08-19 21:21:24 +00:00
Eric Christopher
e34873f1b0 Remove this test. There are other, duplicates, in the clang test suite. 
llvm-svn: 138084
 2011-08-19 21:21:21 +00:00
Eric Christopher
28fddb0c70 Add file. 
llvm-svn: 138083
 2011-08-19 21:21:20 +00:00
Eric Christopher
4378a0e35c Move 2010-03-22-empty-baseclass.cpp from a frontend+opt test to just 
an opt test.

llvm-svn: 138082
 2011-08-19 21:21:14 +00:00
Jim Grosbach
71ef1b39b1 Add FIXME. 
llvm-svn: 138077
 2011-08-19 20:48:54 +00:00
Jim Grosbach
cf35d78b16 Thumb assembly parsing and encoding for MOV. 
llvm-svn: 138076
 2011-08-19 20:46:54 +00:00
Jim Grosbach
a32aa55506 Thumb assembly parsing and encoding for LSR. 
llvm-svn: 138065
 2011-08-19 19:34:22 +00:00
Jim Grosbach
ea8b606660 Thumb assembly parsing and encoding for LSL(register). 
llvm-svn: 138064
 2011-08-19 19:30:58 +00:00
Jim Grosbach
7d707b4fb1 Thumb assembly parsing and encoding for LSL(immediate). 
llvm-svn: 138063
 2011-08-19 19:29:25 +00:00
Jim Grosbach
9174714826 Thumb assembly parsing and encoding for LDRSB and LDRSH. 
llvm-svn: 138061
 2011-08-19 19:17:58 +00:00
Jim Grosbach
27001ee5fd Thumb assembly parsing and encoding for LDRH. 
llvm-svn: 138060
 2011-08-19 18:55:51 +00:00
Jim Grosbach
36fb75a109 Thumb assembly parsing and encoding for LDRB. 
llvm-svn: 138059
 2011-08-19 18:49:59 +00:00
Jim Grosbach
5a05787b9a Thumb assembly parsing and encoding for LDR(register). 
llvm-svn: 138056
 2011-08-19 18:35:06 +00:00
Jim Grosbach
6d9a3e68bb Thumb assembly parsing and encoding for LDR(literal). 
llvm-svn: 138052
 2011-08-19 18:20:48 +00:00
Jim Grosbach
d429ab26cb Thumb assembly parsing and encoding for LDR(immediate) form T2. 
llvm-svn: 138050
 2011-08-19 18:13:48 +00:00
Jim Grosbach
35b968afdc Thumb assembly parsing and encoding for LDR(immediate) form T1. 
llvm-svn: 138047
 2011-08-19 17:55:24 +00:00
Craig Topper
f68d77215d Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler 
llvm-svn: 138034
 2011-08-19 05:28:50 +00:00
Jakob Stoklund Olesen
f847cb77db Add test case for r138018. 
llvm-svn: 138033
 2011-08-19 04:30:24 +00:00
Bruno Cardoso Lopes
306110c29a Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the 
implementation!

llvm-svn: 138029
 2011-08-19 02:23:56 +00:00
Dan Gohman
c5d64c76e0 Track a retain+release nesting level independently of the 
known-incremented level, because the two concepts can be used
to prove the saftey of a retain+release removal in different
ways.

llvm-svn: 138016
 2011-08-19 00:26:36 +00:00
Akira Hatanaka
163382894e Use subword loads instead of a 4-byte load when the size of a structure (or a 
piece of it) that is being passed by value is smaller than a word.

llvm-svn: 138007
 2011-08-18 23:39:37 +00:00
Owen Anderson
421e30086e STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. 
Found by randomized testing.

llvm-svn: 138003
 2011-08-18 22:47:44 +00:00
Owen Anderson
d113a59074 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. 
llvm-svn: 138000
 2011-08-18 22:31:17 +00:00
Owen Anderson
d121f0e77c Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. 
Fixes a large class of disassembler crashes found by randomized testing.

llvm-svn: 137995
 2011-08-18 22:11:02 +00:00
Ivan Krasin
338df71d60 FastISel: avoid function calls between the materialization of the constant and its use. 
llvm-svn: 137993
 2011-08-18 22:06:10 +00:00
Jim Grosbach
7ecefeb594 Thumb assembly parsing and encoding for LDM instruction. 
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.

llvm-svn: 137986
 2011-08-18 21:50:53 +00:00
Owen Anderson
b4bc7704ec More Thumb1 decoding tests. 
llvm-svn: 137974
 2011-08-18 20:05:06 +00:00
Devang Patel
89c3e65b97 Add another test. 
llvm-svn: 137969
 2011-08-18 18:50:25 +00:00
Devang Patel
63300edc64 Add test to check type uniquing. 
llvm-svn: 137968
 2011-08-18 18:40:49 +00:00
Jim Grosbach
e5d4c35c23 Thumb assembly parsing and encoding for EOR. 
llvm-svn: 137964
 2011-08-18 18:10:38 +00:00
Jim Grosbach
d14d4c0aa8 Thumb assembly parsing and encoding for CMP. 
llvm-svn: 137963
 2011-08-18 18:08:29 +00:00
James Molloy
5d9ba3b5aa Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed. 
llvm-svn: 137960
 2011-08-18 18:03:02 +00:00
Jim Grosbach
a76d04e29e Thumb assembly parsing and encoding test for CMN. 
llvm-svn: 137957
 2011-08-18 17:55:03 +00:00
Owen Anderson
366ac95879 Port over BL/BLX to disassembly tests. 
llvm-svn: 137954
 2011-08-18 17:43:52 +00:00
Jim Grosbach
54d054dba4 ARM assembly parsing and encoding test for BX/BLX (register). 
llvm-svn: 137949
 2011-08-18 17:02:28 +00:00
Jim Grosbach
1a63bca66c ARM assembly parsing and encoding test for BL/BLX (immediate). 
llvm-svn: 137948
 2011-08-18 17:00:09 +00:00
Richard Osborne
415c5ff412 Add intrinsics for SETEV, GETED, GETET. 
llvm-svn: 137938
 2011-08-18 13:00:48 +00:00
Bruno Cardoso Lopes
c174d8ac48 Cleanup vector logical ops in AVX and add use int versions for simple 
v2i64

llvm-svn: 137919
 2011-08-18 02:11:34 +00:00
Owen Anderson
eb5c093d8d Port new Thumb1 encoding tests over to decoding tests. 
llvm-svn: 137902
 2011-08-17 23:37:33 +00:00
Jim Grosbach
d4e9b9844d ARM assembly parsing and encoding test for BKPT. 
llvm-svn: 137898
 2011-08-17 23:11:13 +00:00
Jim Grosbach
fefc732dd9 ARM assembly parsing and encoding test for BIC. 
llvm-svn: 137895
 2011-08-17 23:00:53 +00:00
Jim Grosbach
b0e8cd2bfa Thumb assembly parsing and encoding for B. 
llvm-svn: 137891
 2011-08-17 22:57:40 +00:00
Jim Grosbach
1b761bd2d5 Thumb assembly parsing and encoding for ASR. 
llvm-svn: 137889
 2011-08-17 22:49:09 +00:00
Eli Friedman
775a316a06 Atomic load/store handling for the passes using memdep (GVN, DSE, memcpyopt). 
llvm-svn: 137888
 2011-08-17 22:22:24 +00:00
Bruno Cardoso Lopes
82795e6b41 Fix PR10688. Add support for spliting 256-bit vector shifts when the 
shift amount is variable

llvm-svn: 137885
 2011-08-17 22:12:20 +00:00
Jim Grosbach
0115c6f75b Thumb assembly parsing and encoding for ADR. 
llvm-svn: 137864
 2011-08-17 20:37:40 +00:00
Jim Grosbach
20329b9f8e Add a couple of FIXMEs. 
llvm-svn: 137861
 2011-08-17 20:35:57 +00:00
Devang Patel
d9104c08d8 Fix test case. 
llvm-svn: 137847
 2011-08-17 18:48:28 +00:00
Devang Patel
7163bf87f3 Remove superficial test. 
llvm-svn: 137846
 2011-08-17 18:39:13 +00:00
Devang Patel
9dc352faf3 Robustify test. 
llvm-svn: 137845
 2011-08-17 18:38:44 +00:00
Owen Anderson
4c26beae4c Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file. 
llvm-svn: 137840
 2011-08-17 18:21:36 +00:00
Eli Friedman
e1655eebc3 Silly mistake from r137777; restore significant isStructTy() checks. While here, be a bit more defensive 
with unknown instructions.

Fixes PR10687.

llvm-svn: 137836
 2011-08-17 18:10:43 +00:00
Jim Grosbach
39af673350 Thumb assembly parsing and encoding for ADC(register) instruction. 
llvm-svn: 137833
 2011-08-17 17:55:28 +00:00
Jim Grosbach
c93201cb25 Add missing '@' delimiter. 
llvm-svn: 137832
 2011-08-17 17:46:01 +00:00
Owen Anderson
3146968039 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 
Patch by James Molloy.

llvm-svn: 137830
 2011-08-17 17:44:15 +00:00
Bruno Cardoso Lopes
98531dfd08 Introduce matching patterns for vbroadcast AVX instruction. The idea is to 
match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.

llvm-svn: 137810
 2011-08-17 02:29:19 +00:00
Bruno Cardoso Lopes
0a3b3123fd Update test to not use the scalar type to splat from a load 
llvm-svn: 137809
 2011-08-17 02:29:15 +00:00
Bruno Cardoso Lopes
4ff4ed28af Now that we have a canonical way to handle 256-bit splats: 
vinsertf128 $1 + vpermilps $0, remove the old code that used to first
do the splat in a 128-bit vector and then insert it into a larger one.
This is better because the handling code gets simpler and also makes a
better room for the upcoming vbroadcast!

llvm-svn: 137807
 2011-08-17 02:29:10 +00:00
Akira Hatanaka
0179c7fa68 Add support for ext and ins. 
llvm-svn: 137804
 2011-08-17 02:05:42 +00:00
Jim Grosbach
ae9f7f938f Thumb ADD(immediate) parsing support. 
llvm-svn: 137788
 2011-08-16 23:57:34 +00:00
Eli Friedman
32bc68c480 An additional atomic test; related to r137662. 
llvm-svn: 137786
 2011-08-16 23:29:17 +00:00
Jim Grosbach
7a5c6948ca Thumb parsing diagnostics for low-reg requirements on ADD and MOV. 
llvm-svn: 137779
 2011-08-16 22:20:01 +00:00
Eli Friedman
b4733f623f A bunch of misc fixes to SCCPSolver::ResolvedUndefsIn, including a fix to stop 
making random bad assumptions about instructions which are not explicitly listed.  

Includes fix for rdar://9956541, a version of "undef ^ undef should return
0 because it's easier than arguing with users".

llvm-svn: 137777
 2011-08-16 22:06:31 +00:00
Eric Christopher
16a70911af Remove tests that have been obsoleted or migrated to clang/optimizer tests. 
llvm-svn: 137775
 2011-08-16 21:46:25 +00:00
Jim Grosbach
850f937ecc Thumb assembly parsing and encoding for ADD(register) instruction. 
llvm-svn: 137759
 2011-08-16 21:34:08 +00:00
Eli Friedman
e0095e4339 Minor bug in SCCP found by inspection. (I don't think it's possible to hit this with a normal pass pipeline, but fixing for completeness.) 
llvm-svn: 137755
 2011-08-16 21:12:35 +00:00
Jim Grosbach
192f298228 Add testcase for r137746. 
llvm-svn: 137754
 2011-08-16 21:11:21 +00:00
Jim Grosbach
06f3a3b427 Tidy up formatting. 
llvm-svn: 137747
 2011-08-16 20:55:41 +00:00
Jim Grosbach
8d67a0e07c ARM thumb assembly parsing for arithmetic flag setting instructions. 
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.

llvm-svn: 137746
 2011-08-16 20:45:50 +00:00
Bruno Cardoso Lopes
d64294fb0a Instead of always leaving the work to the generic legalizer when 
there is no support for native 256-bit shuffles, be more smart in some
cases, for example, when you can extract specific 128-bit parts and use
regular 128-bit shuffles for them. Example:

For this shuffle:
  shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32>
                <i32 1, i32 0, i32 7, i32 6>

This was expanded to:
  vextractf128  $1, %ymm1, %xmm2
  vpextrq $0, %xmm2, %rax
  vmovd %rax, %xmm1
  vpextrq $1, %xmm2, %rax
  vmovd %rax, %xmm2
  vpunpcklqdq %xmm1, %xmm2, %xmm1
  vpextrq $0, %xmm0, %rax
  vmovd %rax, %xmm2
  vpextrq $1, %xmm0, %rax
  vmovd %rax, %xmm0
  vpunpcklqdq %xmm2, %xmm0, %xmm0
  vinsertf128 $1, %xmm1, %ymm0, %ymm0
  ret

Now we get:
  vshufpd $1, %xmm0, %xmm0, %xmm0
  vextractf128  $1, %ymm1, %xmm1
  vshufpd $1, %xmm1, %xmm1, %xmm1
  vinsertf128 $1, %xmm1, %ymm0, %ymm0

llvm-svn: 137733
 2011-08-16 18:21:54 +00:00
Akira Hatanaka
dcbf455b98 Add test case for r137711. 
llvm-svn: 137725
 2011-08-16 17:32:01 +00:00
Jim Grosbach
90387c44f4 ARM .align NOP padding uses different encoding pre-ARMv6. 
Patch by Kristof Beyls and James Malloy.

llvm-svn: 137723
 2011-08-16 17:06:20 +00:00
Akira Hatanaka
12df91513e Fix handling of double precision loads and stores when Mips1 is targeted. 
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711
 2011-08-16 03:51:51 +00:00
Eli Friedman
6e402678c8 Fix test. 
llvm-svn: 137703
 2011-08-16 01:42:56 +00:00
Eli Friedman
66e399697a Revert a bit of r137667; the logic in question can safely handle atomic load/store. 
llvm-svn: 137702
 2011-08-16 01:28:22 +00:00
Eric Christopher
a1ecf16bfd Migrate this test from llvm/test/FrontendC++/ptr-to-method-devirt.cpp and 
FileCheckize. It is more properly an optimizer test.

llvm-svn: 137700
 2011-08-16 01:17:17 +00:00
Eli Friedman
6a475e691d Update SimplifyCFG for atomic operations. 
This commit includes a mention of the landingpad instruction, but it's not
changing the behavior around it.  I think the current behavior is correct,
though.  Bill, can you double-check that?

llvm-svn: 137691
 2011-08-15 23:59:28 +00:00
Eli Friedman
f0e7c084ea Add comments and test for atomic load/store and mem2reg. 
llvm-svn: 137690
 2011-08-15 23:55:52 +00:00
Owen Anderson
6549866051 Add a test file for Thumb2 NEON. 
llvm-svn: 137687
 2011-08-15 23:42:20 +00:00
Bruno Cardoso Lopes
1e817d1451 Reorder declarations of vmovmskp* and also put the necessary AVX 
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.

llvm-svn: 137684
 2011-08-15 23:36:45 +00:00
Eli Friedman
36ef5fd140 Update instcombine for atomic load/store. 
llvm-svn: 137664
 2011-08-15 22:09:40 +00:00
Bruno Cardoso Lopes
b81c3ed76d Fix PR10656. It's only profitable to use 128-bit inserts and extracts 
when AVX mode is one. Otherwise is just more work for the type
legalizer.

llvm-svn: 137661
 2011-08-15 21:45:54 +00:00
Owen Anderson
54ded8463c Add some more comprehensive VFP decoding tests. 
llvm-svn: 137657
 2011-08-15 21:29:01 +00:00
Eric Christopher
1bb5eaa978 Fix this test to avoid leaving a temporary file behind. 
llvm-svn: 137651
 2011-08-15 20:55:03 +00:00
Eli Friedman
e18709e5b2 Atomic load/store support in LICM. 
llvm-svn: 137648
 2011-08-15 20:52:09 +00:00
Owen Anderson
42946000dd Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 
Patch by James Molloy.

llvm-svn: 137647
 2011-08-15 20:51:32 +00:00
Eric Christopher
92ee29dfc7 Add an ipsccp test. Migrated from test/FrontendC++. 
llvm-svn: 137646
 2011-08-15 20:50:36 +00:00
Owen Anderson
43b6d1c14e Add a test for Thumb1 LDRSH decoding. 
llvm-svn: 137645
 2011-08-15 20:15:43 +00:00
Owen Anderson
aed8eff14b Add testcase for STRH. Patch by James Molloy. 
llvm-svn: 137644
 2011-08-15 20:12:03 +00:00
Owen Anderson
4854258d9c Fix incorrect encoding of UMAAL and friends. Patch by James Molloy. 
llvm-svn: 137641
 2011-08-15 20:08:25 +00:00
Owen Anderson
cd94fca93d Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy. 
llvm-svn: 137636
 2011-08-15 19:00:06 +00:00
Owen Anderson
894585de33 Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. 
llvm-svn: 137635
 2011-08-15 18:44:44 +00:00
Nick Lewycky
e020632f7e This transform is not safe. Thanks to Eli for pointing that out! 
llvm-svn: 137575
 2011-08-14 04:51:49 +00:00
Nick Lewycky
0326303a7a Don't attempt to add 'nsw' when intermediate instructions had no such guarantee. 
llvm-svn: 137572
 2011-08-14 03:41:33 +00:00
Nick Lewycky
b6a9488190 Teach instcombine to preserve the nsw bit by doing an after-the-fact analysis 
when combining add and sub instructions. Patch by Pranav Bhandarkar!

llvm-svn: 137570
 2011-08-14 01:45:19 +00:00
Eli Friedman
1dc4fa369c Fix test. 
llvm-svn: 137556
 2011-08-13 17:06:34 +00:00
Bob Wilson
90799621b3 Expand VMOVQQQQ pseudo instructions. 
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed.  Our register allocator must be awesome!

llvm-svn: 137551
 2011-08-13 05:14:55 +00:00
Eli Friedman
baf0f69f9a Move "atomic" and "volatile" designations on instructions after the opcode 
of the instruction.

Note that this change affects the existing non-atomic load and store
instructions; the parser now accepts both forms, and the change is noted
in the release notes.

llvm-svn: 137527
 2011-08-12 22:50:01 +00:00
Bruno Cardoso Lopes
2d100ca13c The VPERM2F128 is a AVX instruction which permutes between two 256-bit 
vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.

llvm-svn: 137519
 2011-08-12 21:48:26 +00:00
Akira Hatanaka
c9c0190cbe Define unaligned load and store. 
llvm-svn: 137515
 2011-08-12 21:30:06 +00:00
Owen Anderson
2ea55a0881 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. 
llvm-svn: 137502
 2011-08-12 20:36:11 +00:00
Owen Anderson
9d85cab3d5 Port over the basic ARM encodings test file to a decoding test file. Greatly increases our test coverage of basic ARM-mode instructions. 
llvm-svn: 137495
 2011-08-12 19:42:45 +00:00
Akira Hatanaka
6caf61a6ac Test case for 137484 
llvm-svn: 137486
 2011-08-12 18:12:06 +00:00
Jim Grosbach
d154fc4c8f Tidy up formatting. 
llvm-svn: 137471
 2011-08-12 17:43:31 +00:00
Jim Grosbach
1cfe8c24d5 Tidy up formatting. 
llvm-svn: 137464
 2011-08-12 17:01:02 +00:00
Benjamin Kramer
e404b3e2d1 MachOWriter: Don't crash on fixups with arithmetic, emit a relocation instead. This matches what as does. 
llvm-svn: 137414
 2011-08-12 01:51:29 +00:00
Dan Gohman
c188a47b62 Don't convert objc_autoreleaseReturnValue to objc_autorelease if the result 
is returned through a bitcast.

llvm-svn: 137402
 2011-08-12 00:36:31 +00:00
Dan Gohman
783fdc6375 Don't let arbitrary calls disrupt nested retain+release pairs if 
the retains and releases all use the same SSA pointer value.

Also, don't let CFG hazards disrupt nested retain+release pair
optimizations.

llvm-svn: 137399
 2011-08-12 00:26:31 +00:00
Jim Grosbach
ade39d38e1 Clean up formatting a bit. 
llvm-svn: 137393
 2011-08-11 23:57:17 +00:00
Jim Grosbach
d17df06881 ARM vector compare to zero instruction assembly parsing support. 
llvm-svn: 137389
 2011-08-11 23:51:13 +00:00
Andrew Trick
d251d23191 A slew of unit tests for the recent LoopInfo::updateUnloop feature 
checked in at r137276 and r137341.

llvm-svn: 137385
 2011-08-11 23:38:09 +00:00
Andrew Trick
5a5a5ebe68 Allow loop unrolling to get known trip counts from ScalarEvolution. 
SCEV unrolling can unroll loops with arbitrary induction variables. It
is a prerequisite for -disable-iv-rewrite performance. It is also
easily handles loops of arbitrary structure including multiple exits
and is generally more robust.

This is under a temporary option to avoid affecting default
behavior for the next couple of weeks. It is needed so that I can
checkin unit tests for updateUnloop.

llvm-svn: 137384
 2011-08-11 23:36:16 +00:00
Akira Hatanaka
b787f8a8a5 Enclose directive .cprestore with .set macro and nomacro to silence assembler 
warning. 

llvm-svn: 137378
 2011-08-11 22:42:31 +00:00
Jim Grosbach
41ef68eb17 Fix tests per now-correct encoding as of r137371. 
llvm-svn: 137376
 2011-08-11 22:31:48 +00:00
Jim Grosbach
edefbb31c3 ARM STRT assembly parsing and encoding. 
llvm-svn: 137372
 2011-08-11 22:18:00 +00:00
Jim Grosbach
ed8a320007 ARM load shifted register pre-index fix shift value asm parser encoding. 
llvm-svn: 137367
 2011-08-11 22:05:09 +00:00
Bruno Cardoso Lopes
328a6a980b Add a dag combine to xform 256-bit shuffles into simple vector 
inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.

llvm-svn: 137362
 2011-08-11 21:50:44 +00:00
Bruno Cardoso Lopes
884d8b9cb5 Fix the test added by Nadav in r137308. Make it more strict: 
1) check for the "v" version of movaps
2) add a couple of CHECK-NOT to guarantee the behavior
3) move to a more appropriate test file

llvm-svn: 137361
 2011-08-11 21:50:35 +00:00
Jim Grosbach
609316e481 ARM STRHT assembly parsing and encoding. 
llvm-svn: 137358
 2011-08-11 21:39:41 +00:00
Jim Grosbach
5c12d41c95 ARM STRH assembly parsing and encoding. 
llvm-svn: 137353
 2011-08-11 21:17:22 +00:00
Owen Anderson
4618d77bcd Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. 
llvm-svn: 137347
 2011-08-11 20:47:56 +00:00
Owen Anderson
1ec4fcb5d3 Improve operand validation for Thumb2 addressing modes. 
llvm-svn: 137344
 2011-08-11 20:40:40 +00:00
Jim Grosbach
81b2835f83 ARM STRD assembly parsing and encoding. 
llvm-svn: 137342
 2011-08-11 20:28:23 +00:00
Owen Anderson
73e7d34732 Continue to tighten decoding by performing more operand validation. 
llvm-svn: 137340
 2011-08-11 20:21:46 +00:00
Jim Grosbach
bfc85134c2 ARM STRBT assembly parsing and encoding. 
llvm-svn: 137337
 2011-08-11 20:04:56 +00:00
Jim Grosbach
87f0f921b5 Add FIXME. 
llvm-svn: 137336
 2011-08-11 19:43:42 +00:00
Jim Grosbach
a6572a1201 ARM STRB assembly parsing and encoding tests. 
llvm-svn: 137335
 2011-08-11 19:42:58 +00:00
Jim Grosbach
9673dc9e01 Fix a copy/paste error so that LDRB(register) actually gets tested. 
llvm-svn: 137333
 2011-08-11 19:34:23 +00:00
Jim Grosbach
986a3eb0b2 ARM STR(register) assembly parsing and encoding tests. 
llvm-svn: 137332
 2011-08-11 19:26:17 +00:00
Jim Grosbach
e6bd3a1ab8 ARM STR(immediate) assembly parsing and encoding. 
llvm-svn: 137331
 2011-08-11 19:22:40 +00:00
Owen Anderson
63ccfdccd1 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. 
llvm-svn: 137325
 2011-08-11 19:00:18 +00:00
Bruno Cardoso Lopes
38d4afa02f Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict. 
llvm-svn: 137324
 2011-08-11 18:59:13 +00:00
Owen Anderson
decc5fcced Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. 
llvm-svn: 137323
 2011-08-11 18:55:42 +00:00
Owen Anderson
707fcaca0e Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me. 
llvm-svn: 137322
 2011-08-11 18:41:59 +00:00
Owen Anderson
8d6b9f063f Improve error checking in the new ARM disassembler. Patch by James Molloy. 
llvm-svn: 137320
 2011-08-11 18:24:51 +00:00
Jim Grosbach
9717a9c0d3 ARM push of a single register encodes as pre-indexed STR. 
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
 2011-08-11 18:07:11 +00:00
Jim Grosbach
abaaf4513f ARM pop of a single register encodes as post-indexed LDR. 
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316
 2011-08-11 17:35:48 +00:00
Nadav Rotem
de1b485f3f [AVX] If the data which is going to be saved is already in two XMM registers 
(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.

Before:
                vinsertf128         $1, %xmm3, %ymm0, %ymm3
                vinsertf128         $0, %xmm1, %ymm3, %ymm1
                vmovaps              %ymm1, 416(%rsp)

After:
                vmovaps              %xmm3, 416+16(%rsp)
                vmovaps              %xmm1, 416(%rsp)

llvm-svn: 137308
 2011-08-11 16:41:21 +00:00
Chris Lattner
3ae8704c4f add missing colon, thanks peter. 
llvm-svn: 137306
 2011-08-11 16:15:10 +00:00
Chris Lattner
575057916a fix PR10605 / rdar://9930964 by adding a pretty scary missed check. 
It's somewhat surprising anything works without this.  Before we would
compile the testcase into:

test:                                   # @test
	movl	$4, 8(%rdi)
	movl	8(%rdi), %eax
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2

now we produce:

test:                                   # @test
	movl	8(%rdi), %eax
	movl	$4, 8(%rdi)
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2
llvm-svn: 137303
 2011-08-11 06:26:54 +00:00
Bruno Cardoso Lopes
8674ddf55a Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causing 
infinite recursive calls in legalize. Fix PR10562

llvm-svn: 137296
 2011-08-11 02:49:44 +00:00
Bruno Cardoso Lopes
954ac403c7 Use the splat index to generate the desired shuffle. Otherwise we 
could only get undefs and the vector shuffle becomes an undef,
generating wrong code.

llvm-svn: 137295
 2011-08-11 02:49:41 +00:00
Eli Friedman
17bd9e5d7c Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2). 
Fixes PR9693.

llvm-svn: 137292
 2011-08-11 01:48:05 +00:00
Jim Grosbach
eb96dd6c99 ARM tests for LDRSHT assembly parsing and encoding. 
llvm-svn: 137274
 2011-08-10 23:18:30 +00:00
Jim Grosbach
e2cc6866d1 ARM tests for LDRSH assembly parsing and encoding. 
llvm-svn: 137272
 2011-08-10 23:12:25 +00:00
Jim Grosbach
f65a625648 ARM tests for LDRSBT assembly parsing and encoding. 
llvm-svn: 137271
 2011-08-10 23:08:56 +00:00
Jim Grosbach
e22ad37645 ARM tests for LDRSB assembly parsing and encoding. 
llvm-svn: 137270
 2011-08-10 23:06:44 +00:00
Jim Grosbach
f291232aa1 Add FIXME. 
llvm-svn: 137265
 2011-08-10 22:56:43 +00:00
Jim Grosbach
5c5f1c8305 ARM tests for LDRHT assembly parsing and encoding. 
llvm-svn: 137263
 2011-08-10 22:55:38 +00:00
NAKAMURA Takumi
5d316f7632 test/CodeGen/X86/opt-shuff-tstore.ll: Add explicit -mtriple=x86_64-linux. 
llvm-svn: 137262
 2011-08-10 22:52:48 +00:00
Jim Grosbach
7c1596bf26 ARM tests for LDRH(register) assembly parsing and encoding. 
llvm-svn: 137261
 2011-08-10 22:45:42 +00:00
Jim Grosbach
e0ccd6b34e ARM LDRH(immediate) assembly parsing and encoding support. 
llvm-svn: 137260
 2011-08-10 22:42:16 +00:00
Jim Grosbach
e0c10a6d0c Add FIXME 
llvm-svn: 137258
 2011-08-10 22:20:38 +00:00
Jim Grosbach
4ad2dc8bb2 ARM LDRD(register) assembly parsing and encoding. 
Add support for literal encoding of #-0 along the way.

llvm-svn: 137254
 2011-08-10 21:56:18 +00:00
Devang Patel
393d6e1fd0 While extending definition range of a debug variable, consult lexical scopes also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases. 
llvm-svn: 137250
 2011-08-10 21:25:34 +00:00
Jim Grosbach
bbef0044c8 ARM LDRD(immediate) assembly parsing and encoding support. 
llvm-svn: 137244
 2011-08-10 20:29:19 +00:00
Nadav Rotem
1b3075c0ab Fix the test. Add cpu target. 
llvm-svn: 137241
 2011-08-10 19:49:19 +00:00
Nadav Rotem
4a8d78d24a When performing a truncating store, it is sometimes possible to rearrange the 
data in-register prior to saving to memory.  When we reorder the data in memory
we prevent the need to save multiple scalars to memory, making a single regular
store.

llvm-svn: 137238
 2011-08-10 19:30:14 +00:00
Owen Anderson
0fde7a84ee Add initial support for decoding NEON instructions in Thumb2 mode. 
llvm-svn: 137236
 2011-08-10 19:01:10 +00:00
Bruno Cardoso Lopes
565ab1542a The following X86 pattern is incorrect: 
def : Pat<(X86Movss VR128:$src1,
                   (bc_v4i32 (v2i64 (load addr:$src2)))),
          (MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.

llvm-svn: 137227
 2011-08-10 17:45:17 +00:00
Rafael Espindola
45cd7316b5 Add support for the R and Q constraints. 
llvm-svn: 137217
 2011-08-10 16:26:42 +00:00
Andrew Trick
4a938add93 Invoke SimplifyIndVar when we partially unroll a loop. Fixes PR10534. 
llvm-svn: 137203
 2011-08-10 04:29:49 +00:00
Bruno Cardoso Lopes
4a435a361d Fix a bug in vpermilps mask checking. Fix PR10560 
llvm-svn: 137194
 2011-08-10 01:54:17 +00:00
Peter Collingbourne
7f188438d5 Remove the build_unwind function from the OCaml bindings. 
llvm-svn: 137193
 2011-08-10 01:10:17 +00:00
Andrew Trick
3ed0cd3cb6 Fix the LoopUnroller to handle nontrivial loops and partial unrolling. 
These are not individual bug fixes. I had to rewrite a good chunk of
the unroller to make it sane. I think it was getting lucky on trivial
completely unrolled loops with no early exits. I included some fairly
simple unit tests for partial unrolling. I didn't do much stress
testing, so it may not be perfect, but should be usable now.

llvm-svn: 137190
 2011-08-10 00:28:10 +00:00
Owen Anderson
87b5ce880a Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 
llvm-svn: 137189
 2011-08-10 00:03:03 +00:00
Owen Anderson
b717d71aa1 Tighten operand checking of register-shifted-register operands. 
llvm-svn: 137180
 2011-08-09 23:33:27 +00:00
Bruno Cardoso Lopes
9a695724bd Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556 
llvm-svn: 137179
 2011-08-09 23:27:13 +00:00
Owen Anderson
62faf296dd Tighten operand checking on memory barrier instructions. 
llvm-svn: 137176
 2011-08-09 23:25:42 +00:00
Owen Anderson
869ce85500 Tighten operand checking on CPS instructions. 
llvm-svn: 137172
 2011-08-09 23:05:39 +00:00
Owen Anderson
8ad37f68a2 Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. 
llvm-svn: 137168
 2011-08-09 22:48:45 +00:00
Bruno Cardoso Lopes
7461b930f3 Add v16i16 and v32i8 store patterns 
llvm-svn: 137166
 2011-08-09 22:39:53 +00:00
Bruno Cardoso Lopes
028c6aa951 Use fp unpack instructions to unpack int types. Until we have AVX2, this 
is the best we can do for these patterns. This fix PR10554.

llvm-svn: 137161
 2011-08-09 22:18:37 +00:00
Eli Friedman
44fd5b2b59 Fix a couple ridiculous copy-paste errors. rdar://9914773 . 
llvm-svn: 137160
 2011-08-09 22:17:39 +00:00
Benjamin Kramer
ca48bdfd5b ARM Disassembler: sign extend branch immediates. 
Not sure about BLXi, but this is what the old disassembler did.

llvm-svn: 137156
 2011-08-09 22:02:50 +00:00
Owen Anderson
2aa4c7e391 Tighten Thumb1 branch predicate decoding. 
llvm-svn: 137146
 2011-08-09 21:07:45 +00:00
Owen Anderson
ffe1c55752 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144
 2011-08-09 20:55:18 +00:00
Bill Wendling
250ea7930e Revert r137134. It breaks some code as Eli pointed out. 
llvm-svn: 137135
 2011-08-09 18:56:35 +00:00
Bill Wendling
ca256c0d2d Print out the variable declaration only if it is a declaration. Otherwise, a 
'static' variable will be emitted twice.
PR10081

llvm-svn: 137134
 2011-08-09 18:31:50 +00:00
Jakob Stoklund Olesen
e43aca1c39 Inflate register classes after coalescing. 
Coalescing can remove copy-like instructions with sub-register operands
that constrained the register class.  Examples are:

  x86: GR32_ABCD:sub_8bit_hi -> GR32
  arm: DPR_VFP2:ssub0 -> DPR

Recompute the register class of any virtual registers that are used by
less instructions after coalescing.

This affects code generation for the Cortex-A8 where we use NEON
instructions for f32 operations, c.f. fp_convert.ll:

  vadd.f32  d16, d1, d0
  vcvt.s32.f32  d0, d16

The register allocator is now free to use d16 for the temporary, and
that comes first in the allocation order because it doesn't interfere
with any s-registers.

llvm-svn: 137133
 2011-08-09 18:19:41 +00:00
Bruno Cardoso Lopes
633400ee00 Reapply a more appropriate solution than in r137114. AVX supports 
v4f64 = sitofp v4i32. This fix PR10559.
Also add support for v4i32 = fptosi v4f64.

llvm-svn: 137128
 2011-08-09 17:39:13 +00:00
Bruno Cardoso Lopes
1962a341d8 Revert r137114 
llvm-svn: 137127
 2011-08-09 17:39:01 +00:00
Justin Holewinski
021ab783b7 PTX: Add initial support for device function calls 
- Calls are supported on SM 2.0+ for function with no return values

llvm-svn: 137125
 2011-08-09 17:36:31 +00:00
Bruno Cardoso Lopes
5dac86dac6 Handle sitofp between v4f64 <- v4i32. Fix PR10559 
llvm-svn: 137114
 2011-08-09 05:48:01 +00:00
Bruno Cardoso Lopes
d521431558 Add support for avx vector fextend 
llvm-svn: 137105
 2011-08-09 03:04:29 +00:00
Bruno Cardoso Lopes
81534df169 Rename and tidy up tests 
llvm-svn: 137103
 2011-08-09 03:04:23 +00:00
Bruno Cardoso Lopes
1025d1eb3b Add two patterns to match special vmovss and vmovsd cases. Also fix 
the patterns already there to be more strict regarding the predicate.
This fixes PR10558

llvm-svn: 137100
 2011-08-09 01:43:09 +00:00
Bruno Cardoso Lopes
d7eac41193 Make LowerVSETCC aware of AVX types and add patterns to match them. 
llvm-svn: 137090
 2011-08-09 00:46:57 +00:00
Dan Gohman
a716e5c67e Tidy up these testcases to look more like real code does. 
llvm-svn: 137085
 2011-08-09 00:33:11 +00:00
Jim Grosbach
d6da18cf19 ARM parsing and encoding for LDRBT instruction. 
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.

llvm-svn: 137074
 2011-08-08 23:28:47 +00:00
Jim Grosbach
dce26073db ARM parsing and encoding for LDRB instruction. 
llvm-svn: 137071
 2011-08-08 22:37:06 +00:00
Jim Grosbach
1dbe50798e Add FIXME. 
llvm-svn: 137070
 2011-08-08 22:11:33 +00:00
Bruno Cardoso Lopes
d8534855ff Add support for several vector shifts operations while in AVX mode. Fix PR10581 
llvm-svn: 137067
 2011-08-08 21:31:08 +00:00
Eli Friedman
7a34419c6f Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611. 
llvm-svn: 137061
 2011-08-08 19:49:37 +00:00
Jakob Stoklund Olesen
85931574b0 Don't clobber pending ST regs when FP regs are killed. 
X86FloatingPoint keeps track of pending ST registers for an upcoming
inline asm instruction with fixed stack register constraints.  It does
this by remembering which FP register holds the value that should appear
at a fixed stack position for the inline asm.

When that FP register is killed before the inline asm, make sure to
duplicate it to a scratch register, so the ST register still has a live
FP reference.

This could happen when the same FP register was copied to two ST
registers, or when a spill instruction is inserted between the ST copy
and the inline asm.

This fixes PR10602.

llvm-svn: 137050
 2011-08-08 17:15:43 +00:00
Andrew Trick
a7fc7983d4 Made SCEV's UDiv expressions more canonical. When dividing a 
recurrence, the initial values low bits can sometimes be ignored.

To take advantage of this, added FoldIVUser to IndVarSimplify to fold
an IV operand into a udiv/lshr if the operator doesn't affect the
result.

-indvars -disable-iv-rewrite now transforms

i = phi i4
i1 = i0 + 1
idx = i1 >> (2 or more)
i4 = i + 4

into

i = phi i4
idx = i0 >> ...
i4 = i + 4

llvm-svn: 137013
 2011-08-06 07:00:37 +00:00
Jim Grosbach
00c4316907 ARM load instruction shifted register index operands. 
Parsing and encoding for shifted index operands for load instructions.

llvm-svn: 136986
 2011-08-05 22:03:36 +00:00
Jim Grosbach
40a7e379c4 ARM indexed load assembly parsing and encoding. 
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.

llvm-svn: 136982
 2011-08-05 21:28:30 +00:00
Jim Grosbach
861430e0bb Add ARM LDR parsing tests. 
llvm-svn: 136977
 2011-08-05 20:33:39 +00:00
Devang Patel
e5379a1a5d We need to map DebugLoc. It leads to Fuction * (through subprogram entry node) which should be appropriately mapped. 
llvm-svn: 136910
 2011-08-04 20:02:18 +00:00
Devang Patel
17d9346546 Linke NamedMDNodes after linking global values as comment suggests. 
llvm-svn: 136909
 2011-08-04 19:44:28 +00:00
Rafael Espindola
b16f4e78a4 Fix the bitwidth of the remaining fields. 
llvm-svn: 136884
 2011-08-04 17:00:11 +00:00
Rafael Espindola
2da6e6a1d8 print st_shndx with the correct number of bits. 
llvm-svn: 136880
 2011-08-04 15:50:13 +00:00
Rafael Espindola
c1a076eeb1 print st_other with the correct number of bits. 
llvm-svn: 136877
 2011-08-04 15:38:19 +00:00
Rafael Espindola
368850841d print st_type with the correct number of bits. 
llvm-svn: 136875
 2011-08-04 15:24:00 +00:00
Rafael Espindola
e08bb3d50f Print st_bind with the correct number of bits. 
llvm-svn: 136874
 2011-08-04 15:10:35 +00:00
Rafael Espindola
865ab6cb05 Print r_sym with the correct number of bits. 
llvm-svn: 136873
 2011-08-04 14:48:27 +00:00
Rafael Espindola
f65dd30907 Print r_type with the correct number of bits. 
llvm-svn: 136872
 2011-08-04 14:39:30 +00:00
Rafael Espindola
c5a30ed713 Another counter goes decimal. 
llvm-svn: 136871
 2011-08-04 14:27:46 +00:00
Rafael Espindola
edfafcbfb0 Change anther counter to decimal. 
llvm-svn: 136870
 2011-08-04 14:01:03 +00:00
Rafael Espindola
3e8393e6f7 Don't print a counter in hex. 
llvm-svn: 136869
 2011-08-04 13:39:15 +00:00
Rafael Espindola
a910136fe2 Print all the bits in the addend. 
llvm-svn: 136867
 2011-08-04 13:00:24 +00:00
Jason W Kim
18ca6290c9 Fix http://llvm.org/bugs/show_bug.cgi?id=10568 
Move the reloc size assert into AsmBackend - where it is more apropos.

llvm-svn: 136855
 2011-08-04 00:38:45 +00:00
Bill Wendling
60e17f8212 Only access both operands of an INSERT_SUBVECTOR if it is an INSERT_SUBVECTOR. 
Fixes PR10527.

llvm-svn: 136853
 2011-08-04 00:32:58 +00:00
Jim Grosbach
767e9d16e6 ARM refactoring assembly parsing of memory address operands. 
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845
 2011-08-03 23:50:40 +00:00
Benjamin Kramer
d93ac7d0b6 Remove underscore that's breaking linux buildbots. 
llvm-svn: 136833
 2011-08-03 23:13:01 +00:00
Jakub Staszak
9d083611d4 Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics. 
llvm-svn: 136826
 2011-08-03 22:34:43 +00:00
Bill Wendling
fdea9930ac Remove the LowerSetJmp pass. It wasn't used effectively by any of the targets. 
This is some of my original LLVM code. *wipes tear*

llvm-svn: 136821
 2011-08-03 22:18:20 +00:00
Andrew Trick
bbb5c7b0aa SCEV: Use AssertingVH to catch dangling BasicBlock* when passes forget 
to notify SCEV of a change. Add forgetLoop in a couple of those places.

llvm-svn: 136797
 2011-08-03 18:32:11 +00:00
Jakob Stoklund Olesen
002075193b Handle IMPLICIT_DEF instructions in X86FloatingPoint. 
This fixes PR10575.

llvm-svn: 136787
 2011-08-03 16:33:19 +00:00
Chris Lattner
d4b0ee77a9 fix PR10286, a problem with the .ll printer handling block addresses that are out-of-scope. 
llvm-svn: 136768
 2011-08-03 06:15:41 +00:00
Devang Patel
99a2f0d98c Use byte offset, instead of element number, to access merged global. 
llvm-svn: 136759
 2011-08-03 01:25:46 +00:00
Nick Lewycky
82418c24b8 Fix logical error when detecting lifetime intrinsics. 
Don't replace a gep/bitcast with 'undef' because that will form a "free(undef)"
which in turn means "unreachable". What we wanted was a no-op. Instead, analyze
the whole tree and look for all the instructions we need to delete first, then
delete them second, not relying on the use_list to stay consistent.

llvm-svn: 136752
 2011-08-03 00:43:35 +00:00
Nick Lewycky
05fed81aa9 Teach InstCombine that lifetime intrincs aren't a real user on the result of a 
malloc call.

llvm-svn: 136732
 2011-08-02 22:08:01 +00:00
Nick Lewycky
2f04a6b411 Lifetime intrinsics on undef are dead. 
llvm-svn: 136722
 2011-08-02 21:19:27 +00:00
Rafael Espindola
cefc38659a Assume .cfi_startproc is the first thing in a function. If the function is 
externally visable, create a local symbol to use in the CFE. If not, use the
function label itself.

Fixes PR10420.

llvm-svn: 136716
 2011-08-02 20:24:22 +00:00
Bruno Cardoso Lopes
ac0984dc7e Make this kind of lowering to be supported by 256-bit instructions: 
shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
To:
  shuffle (vload ptr)), undef, <1, 1, 1, 1>
Fix PR10494

llvm-svn: 136691
 2011-08-02 16:06:18 +00:00
Benjamin Kramer
5aff5a9498 Remove empty test. 
llvm-svn: 136675
 2011-08-02 02:47:45 +00:00
Owen Anderson
1d291c9425 Revert r136503 and r136480 in an effort to fix non-determinism in the llvm-gcc buildbots on i386. Devang is looking into the root cause. 
llvm-svn: 136674
 2011-08-02 02:23:42 +00:00
Bruno Cardoso Lopes
771876cade Add v4f64 -> v2f32 fp_round support. Also add a testcase to exercise 
the legalizer. This commit together with the two previous ones fixes
PR10495.

llvm-svn: 136654
 2011-08-01 21:54:09 +00:00