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Commit Graph

219204 Commits

Author SHA1 Message Date
Fangrui Song
05f5a9a949 [clang] -falign-loops= 2021-07-23 09:50:43 -07:00
Fraser Cormack
65b887fbf8 [RISCV] Add a test showing an incorrect vsetvli insertion
This patch adds a reduced test case which identifies an illegal vsetvli
inserted by the compiler. The compiler emits a vsetvli which is intended
to preserve VL with the SEW/LMUL ratio e32/m1 when in fact the VL could
have been set by e64/m2 in a predecessor block.

Differential Revision: https://reviews.llvm.org/D106286
2021-07-23 09:27:06 -07:00
LLVM GN Syncbot
cf4b05e2f6 [gn build] Port e5d8b93e5a25 2021-07-23 16:13:25 +00:00
LLVM GN Syncbot
5c1975283a [gn build] Port 0ad562b48bfd 2021-07-23 16:13:24 +00:00
Craig Topper
a4ed0c97a6 [RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the sew/lmul ratio is constant.
Since we're changing VTYPE, we may change VLMAX which could
invalidate the previous VL. If we can't tell if it is safe we
should use an AVL of 1 instead of keeping the old VL.

This is a quick fix. We may want to thread VL to the pseudo
instruction instead of making up a value. That will require ISD
opcode changes and changes to the C intrinsic interface.

This fixes the issue raised in D106286.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D106403
2021-07-23 09:12:05 -07:00
Craig Topper
da55d61e8f [X86] Fix a bug in TEST with immediate creation
This code tries to form a TEST from CMP+AND with an optional
truncate in between. If we looked through the truncate, we may
have extra bits in the AND mask that shouldn't participate in
the checks. Normally SimplifyDemendedBits takes care of this, but
the AND may have another user. So manually mask out any extra bits.

Fixes PR51175.

Differential Revision: https://reviews.llvm.org/D106634
2021-07-23 09:03:53 -07:00
luxufan
42d771a8d4 [JITLink] Add riscv.cpp 2021-07-23 23:57:44 +08:00
luxufan
85def5bf4e [JITLink][RISCV] Initial Support RISCV64 in JITLink
This patch is the initial support, it implements translation from object file to JIT link graph, and very few relocations were supported. Currently, the test file ELF_pc_indirect.s is passed, the HelloWorld program(compiled with mno-relax flag) can be linked correctly and run on instruction emulator correctly.

In the downstream implementation, I have implemented the GOT, PLT function, and EHFrame and some optimization will be implement soon. I will organize the code in to patches, then gradually send it to upstream.

Differential Revision: https://reviews.llvm.org/D105429
2021-07-23 23:47:30 +08:00
Fangrui Song
43ffee6b95 [llvm-symbolizer] Remove one-dash long options
Most modern tools only accept two-dash long options. Remove one-dash
long options which are not recognized by GNU style `getopt_long`.
This ensures long options cannot collide with grouped short options.

Note: llvm-symbolizer has `-demangle={true,false}` for pprof compatibility
(for a while). They are kept.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D106377
2021-07-23 08:35:45 -07:00
Kazu Hirata
73fafa5526 [ARM] Remove getHWDivName (NFC)
This function seems to be unused for at least 5 years.
2021-07-23 07:44:23 -07:00
Benjamin Kramer
f11d6ca5ae [llvm][sve] Silence unused variable warning in Release builds. NFC 2021-07-23 16:16:35 +02:00
Hubert Tong
63a85da461 [ORC] Work around AIX build compiler: Replace lambda; NFC
By replacing a lambda expression with a functor class instance, this
patch works around an issue encountered on AIX where the IBM XL compiler
appears to make no progress for many hours.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D106554
2021-07-23 10:12:26 -04:00
Sanjay Patel
845cd9f16b [x86] improve CMOV codegen by pushing add into operands
This is not the transform direction we want in general,
but by the time we have a CMOV, we've already tried
everything else that could be better.
The transform increases the uses of the other add operand,
but that is safe according to Alive2:
https://alive2.llvm.org/ce/z/Yn6p-A

We could probably extend this to other binops (not just add).
This is the motivating pattern discussed in:
https://llvm.org/PR51069

The test with i8 shows a missed fold because there's a trunc
sitting in front of the add. That can be handled with a small
follow-up.

Differential Revision: https://reviews.llvm.org/D106607
2021-07-23 09:39:32 -04:00
Sanjay Patel
caa4165d5e [x86] add tests for add X, (cmov constants); NFC 2021-07-23 09:39:32 -04:00
David Truby
130948388d [llvm][sve] Lowering for VLS truncating stores
This adds custom lowering for truncating stores when operating on
fixed length vectors in SVE. It also includes a DAG combine to
fold extends followed by truncating stores into non-truncating
stores in order to prevent this pattern appearing once truncating
stores are supported.

Currently truncating stores are not used in certain cases where
the size of the vector is larger than the target vector width.

Differential Revision: https://reviews.llvm.org/D104471
2021-07-23 14:04:55 +01:00
Giorgis Georgakoudis
85a5c6ecfe [OpenMPOpt] Move dedup runtime calls after init for target regions
Deduplication in OpenMPOpt finds redundant OpenMP runtime calls and replaces them with a single call placed in the earliest safe location in the IR. When deduplication happens in a target region this patch makes sure replacement calls are put after target_init.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106556
2021-07-23 05:54:01 -07:00
Simon Pilgrim
2e0db61480 [X86][AVX] lowerV2X128Shuffle - attempt to recognise broadcastf128 subvector load
As noticed on PR50053 we were failing to recognise when a shuffle of a load was really a subvector broadcast load
2021-07-23 13:10:38 +01:00
Roman Lebedev
cc9b4acc5c [NFC][SimplifyCFG] Add test for SpeculativelyExecuteBB() with prof md 2021-07-23 14:25:53 +03:00
Dylan Fleming
8a94b4239a [SVE][IR] Fix Binary op matching in PatternMatch::m_VScale
Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D105978
2021-07-23 11:39:13 +01:00
Dmitry Preobrazhensky
1d7a6567dd [AMDGPU][MC][GFX9][NFC][DOC] Updated AMD GPU assembler syntax description.
Fixed bugs 48639, 49447, 49448, 49449.
2021-07-23 12:59:42 +03:00
Dawid Jurczak
c98a4cb73f Revert "[DSE] Transform memset + malloc --> calloc (PR25892)"
This reverts commit 43234b1595125ba2b5c23e7b28f5a67041c77673.

Reason: We should detect that we are implementing 'calloc' and bail out.
2021-07-23 11:51:59 +02:00
Vitaly Buka
b04b0cb1ff [hwasan] Fix uninitialized DisableOptimization 2021-07-23 02:25:33 -07:00
David Green
f41dff2733 [AArch64] Add worst case shuffle costs
This adds some missing single source shuffle costs for AArch64, of i16
and i8 vectors. v4i16 are the same as v4i32 with a worse case cost of 3
coming from the perfect shuffle tables. The larger vector sizes expand
into a constant pool, plus a load (and adrp) and a tbl. I arbitrarily
chose 8 for the cost to be expensive but not too expensive.

Differential Revision: https://reviews.llvm.org/D106241
2021-07-23 09:01:58 +01:00
Serge Pavlov
865c54f488 [ConstantFolding] Fold constrained arithmetic intrinsics
Constfold constrained variants of operations fadd, fsub, fmul, fdiv,
frem, fma and fmuladd.

The change also sets up some means to support for removal of unused
constrained intrinsics. They are declared as accessing memory to model
interaction with floating point environment, so they were not removed,
as they have side effect. Now constrained intrinsics that have
"fpexcept.ignore" as exception behavior are removed if they have no uses.
As for intrinsics that have exception behavior other than "fpexcept.ignore",
they can be removed if it is known that they do not raise floating point
exceptions. It happens when doing constant folding, attributes of such
intrinsic are changed so that the intrinsic is not claimed as accessing
memory.

Differential Revision: https://reviews.llvm.org/D102673
2021-07-23 14:39:51 +07:00
Sebastian Neubauer
0e5d17756d [AMDGPU] Fix running ResourceUsageAnalysis
Clear the map when running the analysis multiple times.
The assertion that should ensure that every function is only
analyzed once triggered sometimes (once every ~70 compiles of some
graphics pipelines) when two functions of subsequent runs were allocated
at the same address.

Differential Revision: https://reviews.llvm.org/D106452
2021-07-23 09:25:15 +02:00
LLVM GN Syncbot
5995d46a94 [gn build] Port 0118a649348b 2021-07-23 07:19:25 +00:00
Carl Ritson
924e1a4716 [AMDGPU] Add maximum NSA size limit ISA feature
Add maximum NSA size limit as an ISA feature.
Use this to reduce NSA usage on GFX10.1 to avoid stability issues
with 4 and 5 dwords NSA instructions.
Maintain use of longer NSA instructions on GFX10.3.

Note: this also contains some minor fixes for GlobalISel which
did not work correctly with non-NSA form instructions on GFX10.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D103348
2021-07-23 16:16:06 +09:00
Cullen Rhodes
9458751292 [AArch64][AsmParser] NFC: when creating a token IsSuffix=false should be default
Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D106568
2021-07-23 06:36:06 +00:00
Fraser Cormack
2db8b2b6fc [NFC] Fix early line-break in doxygen comment 2021-07-23 07:16:05 +01:00
Craig Topper
aabc612e68 [X86] Add test case simplified from PR51175. NFC 2021-07-22 23:22:39 -07:00
Fraser Cormack
a7f631c814 [SelectionDAG][RISCV] Add tests showing missed scalable-splat optimizations
These tests show missed opportunities in the SelectionDAG layer when
dealing with scalable-vector splats. All of these are handled for the
equivalent `ISD::BUILD_VECTOR` code, and the tests have largely been
translated from the equivalent X86 tests.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106574
2021-07-23 06:58:16 +01:00
Johannes Doerfert
2051c9341b [Attributor] If provided, only look at simplification callbacks not IR
A simplification callback can mean that the IR value is modified beyond
the apparent IR semantics. That is, a `i1 true` could be replaced by an
`i1 false` based on high-level domain-specific information. If a user
provides a simplification callback we will not look at the IR but
instead give up if the callback returns a nullptr.
2021-07-22 23:57:37 -05:00
Hsiangkai Wang
21b283ef66 [RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.
Differential Revision: https://reviews.llvm.org/D105086
2021-07-23 11:35:19 +08:00
Tom Stellard
85eff83056 cmake: Remove unused property on some targets: LLVM_LINK_LIBS
This doesn't appear to be used anywhere.

Reviewed By: serge-sans-paille

Differential Revision: https://reviews.llvm.org/D100021
2021-07-22 20:00:18 -07:00
Nico Weber
69627dbd2f [gn build] Allow use_asan=true on macOS
Seems to work.

(I only tried macOS, not iOS, but need to allow both because
the iOS toolchain used to build compiler-rt asserts otherwise.)
2021-07-22 21:38:02 -04:00
Nico Weber
afc8458e8c [gn build] Reformat all gn files
Ran `git ls-files '*.gn' '*.gni' | xargs llvm/utils/gn/gn.py format`.
2021-07-22 21:35:35 -04:00
Giorgis Georgakoudis
6805993080 [Attributor][Fix] Add overrides for AA2HS analysis 2021-07-22 18:20:14 -07:00
Kai Luo
f31782b163 [PowerPC] Implement XL compatible behavior of __compare_and_swap
According to https://www.ibm.com/docs/en/xl-c-and-cpp-aix/16.1?topic=functions-compare-swap-compare-swaplp
XL's `__compare_and_swap` has a weird behavior that

> In either case, the contents of the memory location specified by addr are copied into the memory location specified by old_val_addr.

(unlike c11 `atomic_compare_exchange` specified in http://www.open-std.org/jtc1/sc22/wg14/www/docs/n1548.pdf)

This patch let clang's implementation follow this behavior.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D106344
2021-07-23 01:16:02 +00:00
Giorgis Georgakoudis
d1dd1d3743 [OpenMP] Use AAHeapToStack/AAHeapToShared analysis in SPMDization
SPMDization D102307 detects incompatible OpenMP runtime calls to abort converting a target region to SPMD mode. Calls to memory allocation/de-allocation routines kmpc_alloc_shared, kmpc_free_shared are incompatible unless they are removed by AAHeapToStack/AAHeapToShared analysis. This patch extends SPMDization detection to include AAHeapToStack/AAHeapToShared analysis results for enlarging the scope of possible SPMDized regions detected.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D105634
2021-07-22 18:08:37 -07:00
Vitaly Buka
381f03cdf9 [NFC][asan] Always pass Dominator Trees into forAllReachableExits 2021-07-22 18:01:38 -07:00
Thomas Johnson
4866aceb76 [ARC] Add tablegen definition for the Find Leading Set (FLS) instruction
Differential Revision: https://reviews.llvm.org/D106602
2021-07-22 17:42:25 -07:00
Gulfem Savrun Yeniceri
4e540995b1 [profile] Add binary id into profiles
This patch adds binary id into profiles to easily associate binaries
with the corresponding profiles. There is an RFC that discusses
the motivation, design and implementation in more detail:
https://lists.llvm.org/pipermail/llvm-dev/2021-June/151154.html

Differential Revision: https://reviews.llvm.org/D102039
2021-07-23 00:19:12 +00:00
Hongtao Yu
03b82baf95 [CSSPGO] Fix a typo in SampleContextTracker
Fixing a typo in SampleContextTracker to use debug name when debug linkage name is no present. This should only affect C programs.

Saw 0.6% perf win on Cinder which is mostly C code.

Reviewed By: wenlei, wmi

Differential Revision: https://reviews.llvm.org/D106599
2021-07-22 16:44:50 -07:00
Nico Weber
5e2439abcf [gn build] (manually) port f8c6515554cc (libLLVMDWP) 2021-07-22 19:38:50 -04:00
Mara Sophie Grosch
f0b7862d3f Add llvm-readobj and binutils symlinks to LLVM_TOOLCHAIN_TOOLS
This patch adds llvm-readobj and the binutils symlink for readelf to
LLVM_TOOLCHAIN_TOOLS.

Tvoid *thread, void *attr,hey are required by some (most?)
autoconf-built libraries, adding these allows me to build newlib with
the toolchain generated this way.

Also opened an issue for that some days ago, see
https://bugs.llvm.org/show_bug.cgi?id=50698

Reviewed By: sbc100

Differential Revision: https://reviews.llvm.org/D104957
2021-07-22 16:33:51 -07:00
Mircea Trofin
081fb59169 [MLGO] Strip TF_PIP cmake variable
This should fix build breaks for 'development' mode. The other modes
were unaffected - 'release' because it doesn't use TFUtils.cpp, and the
mixed mode because the AOT compiled code brings in the necessary include
dirs anyway.
2021-07-22 16:28:13 -07:00
Florian Mayer
b276efa2ab [hwasan] Use stack safety analysis.
This avoids unnecessary instrumentation.

Reviewed By: eugenis, vitalybuka

Differential Revision: https://reviews.llvm.org/D105703
2021-07-22 16:20:27 -07:00
Mircea Trofin
cbaf468075 [docs] Add the compiler-rt requirement to the test suite doc
Differential Revision: https://reviews.llvm.org/D101467
2021-07-22 16:03:45 -07:00
Eli Friedman
299e6ad121 [AArch64] Regenerate test arm64-ccmp.ll 2021-07-22 15:03:05 -07:00
Roman Lebedev
78acee8f2c [SimplifyCFG] SimplifyCondBranchToTwoReturns(): really only deal with different ret blocks
This function is called when some predecessor of an empty return block
ends with a conditional branch, with both successors being empty ret blocks.

Now, because of the way SimplifyCFG works, it might happen to simplify
one of the blocks in a way that makes a conditional branch
into an unconditional one, since it's destinations are now identical,
but it might not have actually simplified said conditional branch
into an unconditional one yet.

So, we have to check that ourselves first,
especially now that SimplifyCFG aggressively tail-merges
all ret and resume blocks.

Even if it was an unconditional branch already,
`SimplifyCFGOpt::simplifyReturn()` doesn't call `FoldReturnIntoUncondBranch()`
by default.
2021-07-23 00:36:59 +03:00