RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 20:43:44 +02:00
Code Issues Projects Releases Wiki Activity
81,162 Commits 4 Branches 5 Tags 704 MiB
bf6a47d0ec
Commit Graph

498 Commits

Author SHA1 Message Date
Craig Topper
bf6a47d0ec Prune some includes 
llvm-svn: 153502
 2012-03-27 07:54:11 +00:00
Kevin Enderby
b87e1e0bfd Fix assembling ARM vst2 instructions with double-spaced registers. 
llvm-svn: 153099
 2012-03-20 17:41:51 +00:00
Jim Grosbach
65c7d4dab9 ARM assembly, accept optional '#' on lane index number. 
rdar://11057160

llvm-svn: 153053
 2012-03-19 20:39:53 +00:00
Jim Grosbach
af19922301 ARM ldm/stm register lists can be out of order. 
It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.

rdar://11064740

llvm-svn: 152943
 2012-03-16 20:48:38 +00:00
Jim Grosbach
e821ce3e5f Remove inadvertant commit. 
llvm-svn: 152870
 2012-03-15 23:00:30 +00:00
Jim Grosbach
3812c82b92 ARM case-insensitive checking for APSR_nzcv. 
rdar://11056591

llvm-svn: 152846
 2012-03-15 21:34:14 +00:00
Jim Grosbach
04f671dced ARM aliases for pre-unified syntax fcmpz[sd] mnemonics. 
rdar://11056647

llvm-svn: 152834
 2012-03-15 20:48:18 +00:00
Jim Grosbach
3b5f99f716 ARM more NEON VLD/VST composite physical register refactoring. 
Register pair, all lanes subscripting.

llvm-svn: 152157
 2012-03-06 23:10:38 +00:00
Jim Grosbach
a3eeee8a91 ARM refactor more NEON VLD/VST instructions to use composite physregs 
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

llvm-svn: 152150
 2012-03-06 22:01:44 +00:00
Jim Grosbach
a6b09b4691 ARM Refactor VLD/VST spaced pair instructions. 
Use the new composite physical registers.

llvm-svn: 152063
 2012-03-05 21:43:40 +00:00
Jim Grosbach
d0fb2e7c99 ARM Remove a bit of dead code. 
llvm-svn: 152061
 2012-03-05 21:09:58 +00:00
Jim Grosbach
fdfaed95ae ARM refactor away a bunch of VLD/VST pseudo instructions. 
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

llvm-svn: 152045
 2012-03-05 19:33:30 +00:00
Craig Topper
11bcb12b5e Convert assert(0) to llvm_unreachable 
llvm-svn: 149961
 2012-02-07 02:50:20 +00:00
Jim Grosbach
b4cc72d103 Tidy up. One more return type mismatch fix. 
llvm-svn: 149452
 2012-01-31 23:51:09 +00:00
Jim Grosbach
44913df963 Keep source information, if available, around for ARM Fixups. 
Adjust an example MachObjectWriter diagnostic to use the information
to issue a better message.

Before:
LLVM ERROR: unknown ARM fixup kind!

After:
x.s:6:5: error: unsupported relocation on symbol
    beq bar
    ^

rdar://9800182

llvm-svn: 149093
 2012-01-26 23:20:15 +00:00
Jim Grosbach
45722b499a Tidy up. Fix mismatched return types for error handling. 
llvm-svn: 149062
 2012-01-26 15:56:45 +00:00
Jim Grosbach
20a6580dff ARM assemly parsing and validation of IT instruction. 
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."

PR11853

llvm-svn: 148969
 2012-01-25 19:52:01 +00:00
Jim Grosbach
e8095f3b49 NEON VLD4(all lanes) assembly parsing and encoding. 
llvm-svn: 148884
 2012-01-25 00:01:08 +00:00
Jim Grosbach
f478b2a706 NEON VLD3(all lanes) assembly parsing and encoding. 
llvm-svn: 148882
 2012-01-24 23:47:04 +00:00
Jim Grosbach
e151b15949 NEON VST4(one lane) assembly parsing and encoding. 
llvm-svn: 148836
 2012-01-24 18:53:13 +00:00
Jim Grosbach
a78348fcda NEON VLD4(one lane) assembly parsing and encoding. 
llvm-svn: 148832
 2012-01-24 18:37:25 +00:00
Jim Grosbach
3be662b372 NEON VST4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148764
 2012-01-24 00:58:13 +00:00
Jim Grosbach
ca32a49eb5 NEON VLD4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148762
 2012-01-24 00:43:17 +00:00
Jim Grosbach
345c1df4df Tidy up. Remove some vertical space for readability. 
llvm-svn: 148761
 2012-01-24 00:43:12 +00:00
Jim Grosbach
a4687dcf5a NEON VST3(single element from one lane) assembly parsing. 
llvm-svn: 148755
 2012-01-24 00:07:41 +00:00
Jim Grosbach
048162ddf9 NEON VST3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148748
 2012-01-23 23:45:44 +00:00
Jim Grosbach
8035fac461 NEON VLD3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148745
 2012-01-23 23:20:46 +00:00
Jim Grosbach
dd667a11d3 NEON VLD3 lane-indexed assembly parsing and encoding. 
llvm-svn: 148734
 2012-01-23 21:53:26 +00:00
Jim Grosbach
0eeacbfe2e Simplify some NEON assembly pseudo definitions. 
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

llvm-svn: 148718
 2012-01-23 19:39:08 +00:00
Jim Grosbach
5100c10a17 Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction. 
llvm-svn: 148601
 2012-01-21 00:07:56 +00:00
David Blaikie
06ecc99a56 More dead code removal (using -Wunreachable-code) 
llvm-svn: 148578
 2012-01-20 21:51:11 +00:00
Jim Grosbach
4579f05f36 NEON use vmov.i32 to splat some f32 values into vectors. 
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556
 2012-01-20 18:09:51 +00:00
Jim Grosbach
8a63389253 ARM assembly diagnostic caret in better position for FPImm. 
llvm-svn: 148459
 2012-01-19 02:47:30 +00:00
Jim Grosbach
b7ab9edb4e Thumb2 alternate syntax for LDR(literal) and friends. 
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

llvm-svn: 148432
 2012-01-18 22:46:46 +00:00
David Blaikie
067ad0b263 Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly. 
(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)

llvm-svn: 148262
 2012-01-16 23:24:27 +00:00
Matt Beaumont-Gay
4896c33378 Fix malformed assert. 
If anybody has strong feelings about 'default: assert(0 && "blah")' vs
'default: llvm_unreachable("blah")', feel free to regularize the instances of
each in this file.

llvm-svn: 147459
 2012-01-03 19:03:59 +00:00
Jim Grosbach
a678ad9ecc ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). 
rdar://10558523

llvm-svn: 147189
 2011-12-22 22:19:05 +00:00
Jim Grosbach
59fccb5809 Tidy up. Use predicate function a bit more liberally. 
llvm-svn: 147184
 2011-12-22 22:02:35 +00:00
Jim Grosbach
970c4cab9e ARM pre-UAL aliases. fcmp[sd]. 
llvm-svn: 147158
 2011-12-22 19:20:45 +00:00
Jim Grosbach
100e3aaffa ARM assembler should accept shift-by-zero for any shifted-immediate operand. 
Just treat it as-if the shift wasn't there at all. 'as' compatibility.

rdar://10604767

llvm-svn: 147153
 2011-12-22 18:04:04 +00:00
Jim Grosbach
90f8398ee6 ARM assembly parser canonicallize on 'lsl' for shift-by-zero form. 
llvm-svn: 147152
 2011-12-22 17:37:00 +00:00
Jim Grosbach
8ca95cbf58 Tidy up. Trailing whitespace. 
llvm-svn: 147151
 2011-12-22 17:17:10 +00:00
Jim Grosbach
65cd6c7acc Nuke invalid comment from copy/paste. 
llvm-svn: 147150
 2011-12-22 17:04:50 +00:00
Jim Grosbach
88eacffd72 ARM asm parser should be more lenient w/ .thumb_func directive. 
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.

rdar://10611140

llvm-svn: 147100
 2011-12-21 22:30:16 +00:00
Jim Grosbach
2bbc41fa26 Thumb2 assembly parsing of 'mov rd, rn, rrx'. 
Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

llvm-svn: 147096
 2011-12-21 21:04:19 +00:00
Jim Grosbach
91faf5d15f Thumb2 assembly parsing of 'mov(register shifted register)' aliases. 
These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

llvm-svn: 147094
 2011-12-21 20:54:00 +00:00
Jim Grosbach
2c2140a128 ARM assembly parsing allows constant expressions for lane indices. 
llvm-svn: 147028
 2011-12-21 01:19:23 +00:00
Jim Grosbach
6bd1044b03 ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
llvm-svn: 147025
 2011-12-21 00:38:54 +00:00
Jim Grosbach
7baaa0fc64 ARM .req register name aliases are case insensitive, just like regnames. 
llvm-svn: 147009
 2011-12-20 23:11:00 +00:00
Jim Grosbach
ff31b81fe2 Move comment to appropriate place. 
llvm-svn: 147000
 2011-12-20 22:26:38 +00:00