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1628 Commits

Author SHA1 Message Date
Bob Wilson
00d605d359 Add missing chain operands for VLD* and VST* instructions. 
Set "mayLoad" and "mayStore" on the load/store instructions.

llvm-svn: 78761
 2009-08-12 00:49:01 +00:00
Evan Cheng
a29ee9f509 Shrinkify Thumb2 r = add sp, imm. 
llvm-svn: 78745
 2009-08-11 23:00:31 +00:00
Chris Lattner
a74023896f Change the asmprinter to print the comment character before the 
"inlineasmstart/end" strings so that the contents of the directive
are separate from the comment character.  This lets elf targets
get #APP/#NOAPP for free even if they don't use "#" as the comment
character.  This also allows hoisting the darwin stuff up to the
shared TAI class.

llvm-svn: 78737
 2009-08-11 22:39:40 +00:00
David Goodwin
2686178489 Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter. 
llvm-svn: 78736
 2009-08-11 22:38:43 +00:00
Chris Lattner
f27d5f6662 factorize more darwin TAI stuff. Note that this gives 
darwin/arm support for .no_dead_strip

llvm-svn: 78734
 2009-08-11 22:31:42 +00:00
Chris Lattner
7015f75b6a factorize darwin ProtectedDirective and SetDirective. 
llvm-svn: 78732
 2009-08-11 22:22:44 +00:00
Chris Lattner
bf7a1a3e38 all darwin targets have .space and .zerofill, pull up. 
llvm-svn: 78730
 2009-08-11 22:17:31 +00:00
Chris Lattner
44a2fda8c1 eliminate template from arm TAI 
llvm-svn: 78729
 2009-08-11 22:14:59 +00:00
Chris Lattner
8c7eb509d3 move LCOMMDirective = "\t.lcomm\t" up to DarwinTAI, eliminate 
template in PPC backend for TAI.

llvm-svn: 78727
 2009-08-11 22:06:07 +00:00
Evan Cheng
783028063e Shrinkify Thumb2 load / store multiple instructions. 
llvm-svn: 78717
 2009-08-11 21:11:32 +00:00
Owen Anderson
48f2f0ae72 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
 2009-08-11 20:47:22 +00:00
Chris Lattner
30d9c39337 pass the TargetTriple down from each target ctor to the 
LLVMTargetMachine ctor.  It is currently unused.

llvm-svn: 78711
 2009-08-11 20:42:37 +00:00
Chris Lattner
45bdc96988 split "JumpTableDirective" (an existing hack) into a PIC and nonPIC 
version.  This allows TAI implementations to specify the directive to use
based on the mode being codegen'd for.

The real fix for this is to remove JumpTableDirective, but I don't feel
like diving into the jumptable snarl just now.

llvm-svn: 78709
 2009-08-11 20:30:58 +00:00
Jim Grosbach
67841ae0a8 Add Thumb2 eh_sjlj_setjmp implementation 
llvm-svn: 78701
 2009-08-11 19:42:21 +00:00
Jim Grosbach
c80da41574 fix GetInstSizeInBytes for eh_sjlj_setjmp 
llvm-svn: 78683
 2009-08-11 17:08:15 +00:00
Benjamin Kramer
0481803d2a This void is implicit in C++. 
llvm-svn: 78678
 2009-08-11 16:03:08 +00:00
Jim Grosbach
3c898a99bd Whitespace cleanup. Remove trailing whitespace. 
llvm-svn: 78666
 2009-08-11 15:33:49 +00:00
Jim Grosbach
d5fc7e81b2 Move ~ARMConstantPoolValue() to the .cpp file to avoid needing to include <cstdlib> in the header. 
llvm-svn: 78665
 2009-08-11 15:26:27 +00:00
Evan Cheng
249f07cf57 Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions. 
llvm-svn: 78659
 2009-08-11 09:37:40 +00:00
Evan Cheng
434a66fa9b Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to 
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.

llvm-svn: 78658
 2009-08-11 08:52:18 +00:00
Evan Cheng
9fdf9b4435 80 column violation. 
llvm-svn: 78657
 2009-08-11 08:47:46 +00:00
Evan Cheng
766c076bea Cosmetic changes. 
llvm-svn: 78655
 2009-08-11 07:36:14 +00:00
Evan Cheng
dbccf353d1 Adding a blank line back. 
llvm-svn: 78654
 2009-08-11 07:32:58 +00:00
Bob Wilson
d64e304671 Use vAny type to get rid of Neon intrinsics that differed only in whether 
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.

If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.

llvm-svn: 78646
 2009-08-11 05:39:44 +00:00
Bob Wilson
1c75a23299 Use new EVT::vAny type to combine Neon intrinsics for VPADD. 
llvm-svn: 78632
 2009-08-11 01:15:26 +00:00
David Goodwin
8ca187462c Fix bug in NEON convert for single-precision FP. This also fixes the tblgen warnings. 
llvm-svn: 78629
 2009-08-11 01:07:38 +00:00
Jim Grosbach
c2fd915309 Add stdlib.h 
llvm-svn: 78627
 2009-08-11 00:20:00 +00:00
Jim Grosbach
c9a1dd9291 SjLj based exception handling unwinding support. This patch is nasty, brutish 
and short. Well, it's kinda short. Definitely nasty and brutish.

The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.

Built on Darwin and verified no llvm-core "make check" regressions.

llvm-svn: 78625
 2009-08-11 00:09:57 +00:00
Evan Cheng
49aac700f4 Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck. 
llvm-svn: 78622
 2009-08-10 23:56:04 +00:00
Dan Gohman
888bcd3483 Fix a bug where DAGCombine was producing an illegal ConstantFP 
node after legalize, and remove the workaround code from the
ARM backend.

llvm-svn: 78615
 2009-08-10 23:15:10 +00:00
Owen Anderson
b4bce99769 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
llvm-svn: 78610
 2009-08-10 22:56:29 +00:00
David Goodwin
36a5b02e4f Use NEON for single-precision int<->FP conversions. 
llvm-svn: 78604
 2009-08-10 22:17:39 +00:00
Owen Anderson
30bf6c8dab SimpleValueType-ify a few more methods on TargetLowering. 
llvm-svn: 78595
 2009-08-10 20:46:15 +00:00
Evan Cheng
f0bb0f5204 Handle the constantfp created during post-legalization dag combiner phase. 
llvm-svn: 78594
 2009-08-10 20:25:59 +00:00
Owen Anderson
cf56d576eb Continue the SimpleValueType-ification. 
llvm-svn: 78593
 2009-08-10 20:18:46 +00:00
Chris Lattner
3e6da637f6 split MachO section handling stuff out to its out .h/.cpp file. 
llvm-svn: 78576
 2009-08-10 18:15:01 +00:00
Chris Lattner
7abff8fdb4 arm only needs to emit one .align directive for hidden nlp's, not one 
per pointer.

llvm-svn: 78574
 2009-08-10 18:02:16 +00:00
Chris Lattner
b89551026b make sure that arm nonlazypointers are aligned properly 
llvm-svn: 78573
 2009-08-10 18:01:34 +00:00
David Goodwin
b2f53ed68a Checkpoint scheduling itinerary changes. 
llvm-svn: 78564
 2009-08-10 15:56:13 +00:00
Evan Cheng
0a08d1bb9c Watch out for empty BB. 
llvm-svn: 78562
 2009-08-10 08:10:13 +00:00
Evan Cheng
1ecffadc8d rev, rev16, and revsh do not set CPSR. 
llvm-svn: 78561
 2009-08-10 07:58:45 +00:00
Evan Cheng
87030de948 Duh. Most 16-bit Thumb rr instructions are two-address. Fix table. 
llvm-svn: 78560
 2009-08-10 07:20:37 +00:00
Evan Cheng
e76bc4a520 CPSR can be livein; transfer predicate operands correctly; tMUL is two-address. 
llvm-svn: 78559
 2009-08-10 06:57:42 +00:00
Evan Cheng
b0a0b99918 Add support for folding loads / stores into 16-bit moves used by Thumb2. 
llvm-svn: 78558
 2009-08-10 06:32:05 +00:00
Evan Cheng
b05ad1d066 80 col violation. 
llvm-svn: 78557
 2009-08-10 05:51:48 +00:00
Evan Cheng
f54e50e4e8 Use tMOVgpr2gpr instead of t2MOVr. 
llvm-svn: 78556
 2009-08-10 05:49:43 +00:00
Evan Cheng
ad380aa97a Add support to reduce most of 32-bit Thumb2 arithmetic instructions. 
llvm-svn: 78550
 2009-08-10 02:37:24 +00:00
Evan Cheng
09cacea9fb Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr. 
llvm-svn: 78549
 2009-08-10 02:06:53 +00:00
Chris Lattner
cc70d578be Make the big switch: Change MCSectionMachO to represent a section *semantically* 
instead of syntactically as a string.  This means that it keeps track of the 
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and 
"attribute(section)", so we should now start getting errors about invalid 
section attributes from the compiler instead of the assembler on darwin.

Still todo: 
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
   S_GB_ZEROFILL segment type?

llvm-svn: 78547
 2009-08-10 01:39:42 +00:00
Evan Cheng
390e1927bf Add support to convert 32-bit instructions to 16-bit non-two-address ones. 
llvm-svn: 78540
 2009-08-09 19:17:19 +00:00
Anton Korobeynikov
44fa9f179c Use subclassing to print lane-like immediates (w/o hash) eliminating 
'no_hash' modifier. Hopefully this will make Daniel happy :)

llvm-svn: 78514
 2009-08-08 23:10:41 +00:00
Chris Lattner
2849883bd5 1. Make MCSection an abstract class. 
2. Move section switch printing to MCSection virtual method which takes a
   TAI.  This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and 
   TLOFELF::AtIsCommentChar.

llvm-svn: 78510
 2009-08-08 22:41:53 +00:00
Chris Lattner
1e8ed03507 now that getOrCreateSection is all object-file specific, 
give the impls an object-file-specific name.  In the future
they can take different arguments etc.

llvm-svn: 78495
 2009-08-08 20:22:20 +00:00
Daniel Dunbar
63159fdd2c Update CMake 
llvm-svn: 78475
 2009-08-08 17:03:13 +00:00
Anton Korobeynikov
f8256ecbb5 Add insert_elt / extract_elt patterns for v4f32 stuff. 
Did anyone tests v4f32 ever?

llvm-svn: 78470
 2009-08-08 14:06:07 +00:00
Anton Korobeynikov
0471ef8dd6 Lane number should be printed w/o hash 
llvm-svn: 78469
 2009-08-08 14:05:53 +00:00
Anton Korobeynikov
ae22c37afb Use VLDM / VSTM to spill/reload 128-bit Neon registers 
llvm-svn: 78468
 2009-08-08 13:35:48 +00:00
Bob Wilson
88fafd84ea Implement Neon VZIP and VUZP instructions. These are very similar to VTRN, 
so I generalized the class for VTRN in the .td file to handle all 3 of them.

llvm-svn: 78460
 2009-08-08 06:13:25 +00:00
Bob Wilson
935ee0c122 Implement Neon VTRN instructions. For now, anyway, these are selected 
directly from the intrinsics produced by the frontend.  If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.

llvm-svn: 78459
 2009-08-08 05:53:00 +00:00
Evan Cheng
d19807e327 Add a skeleton Thumb2 instruction size reduction pass. 
llvm-svn: 78456
 2009-08-08 03:21:23 +00:00
Evan Cheng
4046c75e96 Code refactoring. No functionality change. 
llvm-svn: 78455
 2009-08-08 03:20:32 +00:00
Evan Cheng
fb833354b6 tADDhirr should target GPR, not tGPR. 
llvm-svn: 78454
 2009-08-08 03:19:44 +00:00
Evan Cheng
fe745cba18 I can type. 
llvm-svn: 78453
 2009-08-08 02:54:37 +00:00
Chris Lattner
7bf6e40552 make printInstruction return void since its result is omitted. Make the 
error condition get trapped with an assert.

llvm-svn: 78449
 2009-08-08 01:32:19 +00:00
David Goodwin
c0fe95d8ce Make NEON single-precision FP support the default for cortex-a8 (again). 
llvm-svn: 78430
 2009-08-07 23:32:33 +00:00
Anton Korobeynikov
2dfb75ca36 Unbreak the stuff 
llvm-svn: 78425
 2009-08-07 22:51:13 +00:00
Anton Korobeynikov
9b52601704 2 more vdup.32 cases 
llvm-svn: 78419
 2009-08-07 22:36:50 +00:00
Evan Cheng
897663328b A big oops. Thumb1 default CC is a def of CPSR, not a use of CPSR. 
llvm-svn: 78418
 2009-08-07 22:36:37 +00:00
Evan Cheng
2bdb247c12 Thumb2 32-bit ldm / stm needs .w suffix if submode is ia. 
llvm-svn: 78410
 2009-08-07 21:19:10 +00:00
Evan Cheng
7a2e5ba404 This is done. 
llvm-svn: 78399
 2009-08-07 19:34:52 +00:00
Evan Cheng
9c51e8f1fa Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode. 
llvm-svn: 78398
 2009-08-07 19:34:35 +00:00
Evan Cheng
0dab4cc8a0 Fix support to use NEON for single precision fp math. 
llvm-svn: 78397
 2009-08-07 19:30:41 +00:00
Evan Cheng
ece37695db Error out, rather than infinite looping, if constant island pass can't converge. 
llvm-svn: 78377
 2009-08-07 07:35:21 +00:00
Evan Cheng
5af3c8154b tBfar is bl, which clobbers LR. 
llvm-svn: 78370
 2009-08-07 05:45:07 +00:00
Dan Gohman
1c41d60c4a Fix a bunch of namespace pollution. 
llvm-svn: 78363
 2009-08-07 01:32:21 +00:00
Evan Cheng
48b49cf5b9 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. 
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361
 2009-08-07 00:34:42 +00:00
Bob Wilson
bd7627b23e Implement Neon VST[234] operations. 
llvm-svn: 78330
 2009-08-06 18:47:44 +00:00
David Goodwin
3aafcc1dd2 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary. 
llvm-svn: 78321
 2009-08-06 16:52:47 +00:00
Bob Wilson
905678ab37 Neon does not actually have VLD{234}.64 instructions. 
These operations will have to be synthesized from other instructions.

llvm-svn: 78263
 2009-08-06 00:24:27 +00:00
Bob Wilson
6ee52e0047 Add a new pre-allocation pass to assign adjacent registers for Neon instructions 
that have that constraint.  This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.

llvm-svn: 78256
 2009-08-05 23:12:45 +00:00
David Goodwin
6e4065d7c6 When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns. 
llvm-svn: 78244
 2009-08-05 21:02:22 +00:00
Anton Korobeynikov
7a0835dec5 Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly 
hardfloat case.

llvm-svn: 78237
 2009-08-05 20:15:19 +00:00
Anton Korobeynikov
7f9b6ff4a3 Unbreak the stuff, this is ugly, but we cannot do better for now with 'plain' C calling conv. 
llvm-svn: 78232
 2009-08-05 19:40:16 +00:00
Anton Korobeynikov
07ce0611d9 Missed pieces for ARM HardFP ABI. 
Patch by Sandeep Patel!

llvm-svn: 78225
 2009-08-05 19:04:42 +00:00
Daniel Dunbar
3d2ac751da Remove some dead code. 
llvm-svn: 78219
 2009-08-05 18:12:37 +00:00
Bob Wilson
c0e1bed13f Remove a redundant declaration. 
llvm-svn: 78216
 2009-08-05 17:39:44 +00:00
David Goodwin
9013115518 Disable NEON single-precision FP support for Cortex-A8, for now... 
llvm-svn: 78209
 2009-08-05 16:40:57 +00:00
Devang Patel
fde898c9f1 Remove dead code. MDNode and MDString are not Constant anymore. 
llvm-svn: 78207
 2009-08-05 16:40:02 +00:00
David Goodwin
47064aa1c6 By default, for cortex-a8 use NEON for single-precision FP. 
llvm-svn: 78200
 2009-08-05 16:01:19 +00:00
Evan Cheng
a27fac5075 80 col violations. 
llvm-svn: 78175
 2009-08-05 06:41:25 +00:00
Bob Wilson
15c5c15ccb Oops. I didn't mean to commit this piece yet. 
llvm-svn: 78146
 2009-08-05 02:47:13 +00:00
Dan Gohman
5d566d918b Major calling convention code refactoring. 
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.

This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.

This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.

llvm-svn: 78142
 2009-08-05 01:29:28 +00:00
Dan Gohman
4b2748d474 Don't flush the raw_ostream between each MachineFunction. These flush 
calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.

llvm-svn: 78137
 2009-08-05 00:49:25 +00:00
Bob Wilson
1fe51064ba Change DAG nodes for Neon VLD2/3/4 operations to return multiple results. 
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions.  The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.

llvm-svn: 78136
 2009-08-05 00:49:09 +00:00
Evan Cheng
e366789b50 Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode. 
llvm-svn: 78126
 2009-08-04 23:47:55 +00:00
Bob Wilson
3607eeebfa Replace dregsingle operand modifier with explicit escaped curly brackets. 
For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.

llvm-svn: 78109
 2009-08-04 21:39:33 +00:00
Evan Cheng
2ec9ab08d8 Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet. 
llvm-svn: 78104
 2009-08-04 21:12:13 +00:00
David Goodwin
648590849c Add NEON single-precision FP support for fabs and fneg. 
llvm-svn: 78101
 2009-08-04 20:39:05 +00:00
Evan Cheng
29fe8806d5 In thumb mode, r7 is used as frame register. This fixes pr4681. 
llvm-svn: 78086
 2009-08-04 18:46:17 +00:00
David Goodwin
5efde448fa Match common pattern for FNMAC. Add NEON SP support. 
llvm-svn: 78085
 2009-08-04 18:44:29 +00:00
David Goodwin
99adffe5f2 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. 
llvm-svn: 78081
 2009-08-04 17:53:06 +00:00
Anton Korobeynikov
10f01c8dd7 Ooops, I was too fast to commit the wrong fix :( 
llvm-svn: 78060
 2009-08-04 11:18:31 +00:00
Anton Korobeynikov
41ba9004b6 Fix a typo - this unbreaks llvm-gcc build on arm 
llvm-svn: 78059
 2009-08-04 11:12:51 +00:00
Evan Cheng
04035adc46 Thumb2 does not have ib (increment before) and da (decrement after) forms of ldm / stm. 
llvm-svn: 78057
 2009-08-04 08:34:18 +00:00
Evan Cheng
38da233adf Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler. 
llvm-svn: 78032
 2009-08-04 01:56:09 +00:00
Evan Cheng
5711586a17 Load / store multiple pass fixes for Thumb2. Not enabled yet. 
llvm-svn: 78031
 2009-08-04 01:43:45 +00:00
Evan Cheng
817618d570 Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction. 
llvm-svn: 78030
 2009-08-04 01:41:15 +00:00
Bob Wilson
fe37bdfdd8 Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate the 
results to fixed registers.

llvm-svn: 78025
 2009-08-04 00:36:16 +00:00
Bob Wilson
154afab758 Minor cleanup. No functional changes intended. 
llvm-svn: 78024
 2009-08-04 00:25:01 +00:00
Chris Lattner
5247ac71e5 use TLOF to compute the section for a function instead of 
replicating the logic manually.

llvm-svn: 78011
 2009-08-03 22:32:50 +00:00
Chris Lattner
7d2dd6deac convert macho stub emission to use SwitchToSection instead of 
textual sections.

llvm-svn: 78007
 2009-08-03 22:18:15 +00:00
Bob Wilson
eb3b616a7e Lower CONCAT_VECTOR during legalization instead of matching it during isel. 
Add a testcase.

llvm-svn: 77992
 2009-08-03 20:36:38 +00:00
Benjamin Kramer
7869bad67e llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:". 
llvm-svn: 77971
 2009-08-03 13:33:33 +00:00
Evan Cheng
600312b878 These are done. 
llvm-svn: 77949
 2009-08-03 04:08:36 +00:00
Evan Cheng
27ee95d344 Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well. 
llvm-svn: 77939
 2009-08-03 02:38:06 +00:00
Daniel Dunbar
9e079eec0c Move most targets TargetMachine constructor to only taking a target triple. 
- The C, C++, MSIL, and Mips backends still need the module.

llvm-svn: 77927
 2009-08-02 23:37:13 +00:00
Daniel Dunbar
0b82c938fe Normalize Subtarget constructors to take a target triple string instead of 
Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.

llvm-svn: 77918
 2009-08-02 22:11:08 +00:00
Chris Lattner
738a9ba448 move dwarf debug info section selection stuff from TAI to 
TLOF, unifying all the dwarf targets at the same time.

llvm-svn: 77889
 2009-08-02 07:24:22 +00:00
Chris Lattner
bbe55a038a ARM TAI no longer needs a TM, but createTargetAsmInfo() still does. 
llvm-svn: 77878
 2009-08-02 05:23:52 +00:00
Chris Lattner
c388490738 Move the getInlineAsmLength virtual method from TAI to TII, where 
the only real caller (GetFunctionSizeInBytes) uses it.

The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain.  It should be removed 
IMNSHO, but I'll leave that to ARMish folks to decide.

llvm-svn: 77877
 2009-08-02 05:20:37 +00:00
Chris Lattner
5ee7fa1d02 turn some templated inline functions into static functions. 
llvm-svn: 77873
 2009-08-02 04:52:00 +00:00
Chris Lattner
f13912f657 remove the dead ELFTargetAsmInfo.h/cpp file. TargetAsmInfo 
defaults to being ELF.

llvm-svn: 77866
 2009-08-02 04:33:09 +00:00
Chris Lattner
b5ceb50677 remove TargetAsmInfo::TM, which is now dead. The basic TAI class now 
no longer depends on TM!

llvm-svn: 77863
 2009-08-02 04:27:24 +00:00
Chris Lattner
06d8ca1f56 convert ctors/dtors section to be in TLOF instead of 
TAI.

llvm-svn: 77842
 2009-08-02 00:34:36 +00:00
Chris Lattner
4cbb1c0c3f REmove dead fields of TAI. 
llvm-svn: 77820
 2009-08-01 22:40:22 +00:00
Evan Cheng
b9b4b9aa15 Workaround a couple of Darwin assembler bugs. 
llvm-svn: 77781
 2009-08-01 06:13:52 +00:00
Evan Cheng
c165700a7f Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate. 
llvm-svn: 77764
 2009-08-01 01:43:45 +00:00
Evan Cheng
5ef6928dff Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same 
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.

llvm-svn: 77756
 2009-08-01 00:16:10 +00:00
Evan Cheng
cb1704f904 t2BR_JT is mov pc, it's 2 byte long, not 4. 
llvm-svn: 77744
 2009-07-31 22:22:22 +00:00
Evan Cheng
88a27caaaf Thumb2 movcc need .w suffix. 
llvm-svn: 77743
 2009-07-31 22:21:55 +00:00
Chris Lattner
75b7692e66 switch off of 'Section' onto MCSection. We're not properly using 
MCSection subclasses yet, but this is a step in the right direction.

llvm-svn: 77708
 2009-07-31 18:48:30 +00:00
Evan Cheng
0c9705feed Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align 
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.

llvm-svn: 77705
 2009-07-31 18:35:56 +00:00
Evan Cheng
038a564156 - Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset 
is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.

llvm-svn: 77701
 2009-07-31 18:28:05 +00:00
Chris Lattner
c156a00641 refactor section construction in TLOF to be through an explicit 
initialize method, which can be called when an MCContext is available.

llvm-svn: 77687
 2009-07-31 17:42:42 +00:00
Evan Cheng
c9f31ae969 When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. 
llvm-svn: 77642
 2009-07-30 23:29:25 +00:00
David Goodwin
ef70179502 Remove redundant match for frame index from imm8 addrmode, it is handled by the imm12 addrmode. 
llvm-svn: 77632
 2009-07-30 22:45:52 +00:00
David Goodwin
62efc71b9f Darwin assembler now recognizes "orn", so remove workaround. 
llvm-svn: 77627
 2009-07-30 21:51:41 +00:00
David Goodwin
d29f81da16 Darwin assembler now supports "rrx", so remove workaround. 
llvm-svn: 77625
 2009-07-30 21:38:40 +00:00
David Goodwin
2eaffa79af Cleanup and include code selection for some frame index cases. 
llvm-svn: 77622
 2009-07-30 18:56:48 +00:00
David Goodwin
30429aef93 Add missing D* register clobbers for Thumb-2 call. 
llvm-svn: 77611
 2009-07-30 18:01:09 +00:00
Chris Lattner
edb8650e80 add a random codegen deficiency. 
llvm-svn: 77598
 2009-07-30 16:08:58 +00:00
Daniel Dunbar
4d07efb3c4 Switch obvious clients to Twine instead of utostr (when they were already using 
a Twine, e.g., for names).
 - I am a little ambivalent about this; we don't want the string conversion of
   utostr, but using overload '+' mixed with string and integer arguments is
   sketchy. On the other hand, this particular usage is something of an idiom.

llvm-svn: 77579
 2009-07-30 04:20:37 +00:00
Bob Wilson
8624e45518 Lower a 128-bit BUILD_VECTOR with 2 elements to a pair of INSERT_VECTOR_ELTs. 
llvm-svn: 77557
 2009-07-30 00:31:25 +00:00
Evan Cheng
31ac181755 tbb / tbh instructions only branch forward, not backwards. 
llvm-svn: 77522
 2009-07-29 23:20:20 +00:00
Evan Cheng
fabbd6219a Add VFP3 D registers to the DPR register class. 
llvm-svn: 77521
 2009-07-29 23:03:41 +00:00
Evan Cheng
90a1ca6e17 Make sure Thumb2 uses the right call instructions. 
llvm-svn: 77507
 2009-07-29 21:26:42 +00:00
Chris Lattner
18af1b233a Give getPointerRegClass() a "kind" value so that targets can 
support multiple different pointer register classes.

llvm-svn: 77501
 2009-07-29 20:31:52 +00:00
Evan Cheng
c8d3891c87 - Fix an obvious copy and paste error. 
- Darwin Thumb2 call clobbers r9.

llvm-svn: 77500
 2009-07-29 20:10:36 +00:00
Bob Wilson
355e0b70e0 Change Neon VLDn intrinsics to return multiple values instead of really 
wide vectors.  Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct.  Adjust tests accordingly.

llvm-svn: 77468
 2009-07-29 16:39:22 +00:00
Chris Lattner
5c3e1e0d0c pass the mangler down into the various SectionForGlobal methods. 
No functionality change.

llvm-svn: 77432
 2009-07-29 05:09:30 +00:00
Evan Cheng
fc846dd401 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. 
llvm-svn: 77422
 2009-07-29 02:18:14 +00:00
David Goodwin
65028e2427 Thumb-2: fix typo that caused incorrect stack elimination for VFP operations and very large stack frames. 
llvm-svn: 77401
 2009-07-28 23:52:33 +00:00
Devang Patel
cb23671431 Rename MDNode.h header. It defines MDnode and other metadata classes. 
New name is Metadata.h.

llvm-svn: 77370
 2009-07-28 21:49:47 +00:00
Evan Cheng
cf483eb0c0 In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
llvm-svn: 77364
 2009-07-28 20:53:24 +00:00
David Goodwin
0c9e96bf09 Remove support for ORN to workaround <rdar://problem/7096522>. 
llvm-svn: 77363
 2009-07-28 20:51:25 +00:00
Chris Lattner
8972d46576 more simplifications and cleanup. :) 
llvm-svn: 77350
 2009-07-28 18:48:43 +00:00
David Goodwin
dbc23ece04 Add workaround for <rdar://problem/7098328>. 
llvm-svn: 77340
 2009-07-28 18:15:38 +00:00
Chris Lattner
c74586940a the apple "ld_classic" linker doesn't support .literal16 in 32-bit 
mode, and "ld64" (the default linker) falls back to it in -static
mode.

llvm-svn: 77334
 2009-07-28 17:50:28 +00:00
David Goodwin
e94d490b89 Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag. 
llvm-svn: 77329
 2009-07-28 17:06:49 +00:00
Evan Cheng
05555a7d31 tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have. 
llvm-svn: 77305
 2009-07-28 07:38:35 +00:00
Evan Cheng
93c1b56fe9 Code clean up. No functionality changes. 
llvm-svn: 77301
 2009-07-28 06:24:12 +00:00
Evan Cheng
b740190d2e - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300
 2009-07-28 05:48:47 +00:00
Chris Lattner
55461787cc Rip all of the global variable lowering logic out of TargetAsmInfo. Since 
it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.

Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.

This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
   pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
   CStringSection_.  Factor the code better.
5. fixes some bugs in string lowering on ELF targets.

llvm-svn: 77294
 2009-07-28 03:13:23 +00:00
David Goodwin
0bcb94eeff ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM. 
llvm-svn: 77275
 2009-07-27 23:34:12 +00:00
David Goodwin
6ff3fd8021 Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2). 
llvm-svn: 77242
 2009-07-27 19:59:26 +00:00
Chris Lattner
4ff7e1300f remove dead code. 
llvm-svn: 77233
 2009-07-27 19:00:33 +00:00
Evan Cheng
718ab76a04 More DCE. 
llvm-svn: 77231
 2009-07-27 18:48:45 +00:00
Evan Cheng
a702481089 convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions). 
llvm-svn: 77230
 2009-07-27 18:44:00 +00:00
Evan Cheng
fa630cca3f Get rid of more dead code. 
llvm-svn: 77227
 2009-07-27 18:38:54 +00:00
Evan Cheng
55e369a447 Cosmetic change. 
llvm-svn: 77222
 2009-07-27 18:31:40 +00:00
Evan Cheng
03307125f5 Clean up. 
llvm-svn: 77221
 2009-07-27 18:25:24 +00:00
Evan Cheng
a773ae7a39 Get rid of some more getOpcode calls. 
This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.

llvm-svn: 77218
 2009-07-27 18:20:05 +00:00
David Goodwin
bbab77cdda Thumb-2 does not have RSC. 
llvm-svn: 77201
 2009-07-27 16:39:05 +00:00
David Goodwin
471e9f5b8d Add ".w" suffix for wide thumb-2 instructions. 
llvm-svn: 77199
 2009-07-27 16:31:55 +00:00
Chris Lattner
cd7d963b75 Eliminate getNamed/getUnnamedSection, adding a new and unified getOrCreateSection 
instead.

llvm-svn: 77186
 2009-07-27 06:17:14 +00:00
Chris Lattner
a2b00bdd7a Eliminate SectionFlags, just embed a SectionKind into Section 
instead and drive things based off of that.

llvm-svn: 77184
 2009-07-27 05:32:16 +00:00
Evan Cheng
657ef082f0 If CPSR is modified but the def is dead, then it's ok to fold the load / store. 
llvm-svn: 77182
 2009-07-27 04:18:04 +00:00
Evan Cheng
674c4d47b9 Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls. 
llvm-svn: 77181
 2009-07-27 03:14:20 +00:00
Evan Cheng
0cdbde1adf Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements. 
llvm-svn: 77175
 2009-07-27 00:33:08 +00:00
Evan Cheng
61765ac517 Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target. 
llvm-svn: 77174
 2009-07-27 00:24:36 +00:00
Evan Cheng
b1ab426733 Just use a single isMoveInstr to catch all the cases. 
llvm-svn: 77173
 2009-07-27 00:05:15 +00:00
Evan Cheng
a6737e21cf Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir. 
llvm-svn: 77172
 2009-07-26 23:59:01 +00:00
Chris Lattner
0f4d60ca90 untangle a TargetAsmInfo hack where ELFTargetAsmInfo would create a 
'unnamed' bss section, but some impls would want a named one.  Since
they don't have consistent behavior, just make each target do their
own thing, instead of doing something "sortof common" then having
targets change immutable objects later.

llvm-svn: 77165
 2009-07-26 19:23:28 +00:00
Evan Cheng
d555fec28c Refactor. Get rid of a few more getOpcode() calls. 
llvm-svn: 77164
 2009-07-26 18:55:14 +00:00
Daniel Dunbar
75a66c519b Eliminate some uses of DOUT, cerr, and getNameStart(). 
llvm-svn: 77145
 2009-07-26 07:49:05 +00:00
Daniel Dunbar
a7a01acc7c Factor commonality in triple match routines into helper template for registering 
classes, and migrate existing targets over.

llvm-svn: 77126
 2009-07-26 05:03:33 +00:00
Daniel Dunbar
49987490c2 Kill Target specific ModuleMatchQuality stuff. 
- This was overkill and inconsistently implemented.

llvm-svn: 77114
 2009-07-26 02:22:58 +00:00
Bob Wilson
ec256c8938 Add support for ARM Neon VREV instructions. 
Patch by Anton Korzh, with some modifications from me.

llvm-svn: 77101
 2009-07-26 00:39:34 +00:00
Daniel Dunbar
038a7f0d35 Remove Value::{isName, getNameRef}. 
Also, change MDString to use a StringRef.

llvm-svn: 77098
 2009-07-25 23:55:21 +00:00
Daniel Dunbar
d699ffc2ac Simplify JIT target selection. 
- Instead of requiring targets to define a JIT quality match function, we just
   have them specify if they support a JIT.

 - Target selection for the JIT just gets the host triple and looks for the best
   target which matches the triple and has a JIT.

llvm-svn: 77060
 2009-07-25 10:09:50 +00:00
Daniel Dunbar
284fe09fe4 Add new helpers for registering targets. 
- Less boilerplate == good.

llvm-svn: 77052
 2009-07-25 06:49:55 +00:00
Evan Cheng
0f605005c5 80 col violation. 
llvm-svn: 77041
 2009-07-25 01:55:25 +00:00
Evan Cheng
5468ef5230 Get rid of a couple of unnecessary getOpcode calls. 
llvm-svn: 77035
 2009-07-25 01:25:08 +00:00
Evan Cheng
e3a37c42fb Another TODO. 
llvm-svn: 77026
 2009-07-25 00:39:37 +00:00
Evan Cheng
d615e606c4 Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024
 2009-07-25 00:33:29 +00:00
Daniel Dunbar
8496064116 More migration to raw_ostream, the water has dried up around the iostream hole. 
- Some clients which used DOUT have moved to DEBUG. We are deprecating the
   "magic" DOUT behavior which avoided calling printing functions when the
   statement was disabled. In addition to being unnecessary magic, it had the
   downside of leaving code in -Asserts builds, and of hiding potentially
   unnecessary computations.

llvm-svn: 77019
 2009-07-25 00:23:56 +00:00
Evan Cheng
cb63bf2810 ARM code emitter can't handle Thumb2 instructions yet. So don't even try. 
llvm-svn: 77018
 2009-07-25 00:13:11 +00:00
Owen Anderson
cc33e89571 Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come. 
llvm-svn: 77011
 2009-07-24 23:12:02 +00:00
Evan Cheng
84cf748468 Uh. It would be useful to actually print the operand. 
llvm-svn: 77004
 2009-07-24 20:47:38 +00:00
Evan Cheng
597bf41097 Disable my constant island pass optimization (to make use soimm more effectively). It caused infinite looping on lencod. 
llvm-svn: 76995
 2009-07-24 19:31:03 +00:00
Evan Cheng
92376f5a32 Add a workaround for Darwin assembler bug where it's not setting the thumb bit in Thumb2 jumptable entries. We now pass Olden. 
llvm-svn: 76991
 2009-07-24 18:54:23 +00:00
Evan Cheng
e01fec5446 Make sure thumb2 jumptable entries are aligned. 
llvm-svn: 76986
 2009-07-24 18:20:44 +00:00
Evan Cheng
c4221e9b04 Clean up. 
llvm-svn: 76984
 2009-07-24 18:20:16 +00:00
Evan Cheng
5bab9444f9 Replace use of std::set with SmallPtrSet. 
llvm-svn: 76983
 2009-07-24 18:19:46 +00:00
Eli Friedman
1be7dfb1aa Remove unused member functions. 
llvm-svn: 76960
 2009-07-24 07:43:59 +00:00
Chris Lattner
13611a24d8 use section flags more correctly. 
llvm-svn: 76944
 2009-07-24 04:08:17 +00:00
Chris Lattner
6339e5e786 reduce api exposure: clients shouldn't call SectionKindForGlobal directly. 
llvm-svn: 76941
 2009-07-24 03:49:17 +00:00
Evan Cheng
d18a7fc185 Thumb2 should use the register scavenger. 
llvm-svn: 76930
 2009-07-24 01:05:51 +00:00
Evan Cheng
d13b8f8353 FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets. 
llvm-svn: 76925
 2009-07-24 00:53:56 +00:00
David Goodwin
85bcdffa4f Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen. 
llvm-svn: 76919
 2009-07-24 00:16:18 +00:00
Evan Cheng
90f66e1c4e Thumb2 does not allow the use of "pc" register as part of the load / store address. 
llvm-svn: 76909
 2009-07-23 23:09:51 +00:00
Evan Cheng
f6b88eae82 Fix up ARM constant island pass for Thumb2. 
Also fixed up code to fully use the SoImm field for ADR on ARM mode.

llvm-svn: 76890
 2009-07-23 18:27:47 +00:00
Evan Cheng
8997f6bfc1 Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address. 
Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.

llvm-svn: 76889
 2009-07-23 18:26:03 +00:00
David Goodwin
f3c839e0b9 Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. 
llvm-svn: 76883
 2009-07-23 17:06:46 +00:00
Evan Cheng
c21e149091 80 col violation. 
llvm-svn: 76872
 2009-07-23 07:58:08 +00:00
David Goodwin
6fa63db9be Fix typo in addrmode definition. 
llvm-svn: 76806
 2009-07-22 22:24:31 +00:00
Evan Cheng
4a77f28c47 Use getTargetConstant instead of getConstant since it's meant as an constant operand. 
llvm-svn: 76803
 2009-07-22 22:03:29 +00:00
Evan Cheng
ae91b0616b Eliminate a redudant check Eli pointed out. 
llvm-svn: 76762
 2009-07-22 18:08:05 +00:00
Evan Cheng
34576850e1 Don't forget D16 - D31 are clobbered by calls and sjlj eh. 
llvm-svn: 76729
 2009-07-22 06:46:53 +00:00
Evan Cheng
4fdb43a89d Add R12 to the list of registers clobbered by 16-bit Thumb calls as a pre-caution. r12 could be live once we have mixed 32-bit and 16-bit instructions. 
llvm-svn: 76728
 2009-07-22 06:37:28 +00:00
Evan Cheng
2e2a1cbab7 Fix a obvious copy-n-paste bug. 
llvm-svn: 76727
 2009-07-22 06:12:40 +00:00
Evan Cheng
005330f8a0 Get rid one of the getRegisterNumbering. Also add D16 - D31. 
llvm-svn: 76725
 2009-07-22 05:55:18 +00:00
Evan Cheng
f0af946ac8 Add an entry. 
llvm-svn: 76711
 2009-07-22 00:58:27 +00:00
Owen Anderson
cc287b28c9 Get rid of the Pass+Context magic. 
llvm-svn: 76702
 2009-07-22 00:24:57 +00:00
Evan Cheng
b639684766 Fixing cp island pass. Step 1: Determine whether the constant pool offset can be 
negative on an individual bases rather than basing on whether it's in thumb
mode.

llvm-svn: 76698
 2009-07-21 23:56:01 +00:00
Evan Cheng
149b0d4cf1 Fix comment. 
llvm-svn: 76693
 2009-07-21 23:54:22 +00:00
Chris Lattner
fb908d7671 no really, I can spell! 
llvm-svn: 76679
 2009-07-21 23:36:01 +00:00
Chris Lattner
11b49ed2ce add an API so target-independent codegen can determine if a constant 
pool entry will require relocations against it.  I implemented this
conservatively for ARM, someone who is knowledgable about it should
see if this can be improved.

llvm-svn: 76678
 2009-07-21 23:34:23 +00:00
Evan Cheng
66f1d7a0e1 Add fake v7 itineraries for now. 
llvm-svn: 76612
 2009-07-21 18:54:14 +00:00
Chris Lattner
3d4ab7a231 make AsmPrinter::doFinalization iterate over the global variables 
and call PrintGlobalVariable, allowing elimination and simplification
of various targets.

llvm-svn: 76604
 2009-07-21 18:38:57 +00:00
Evan Cheng
192fc19379 Do not select tSXTB / tSXTH in thumb2 mode. 
llvm-svn: 76600
 2009-07-21 18:15:26 +00:00
Evan Cheng
949c2404a2 Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. 
llvm-svn: 76520
 2009-07-21 00:31:12 +00:00
David Goodwin
c5ee8fbaa7 CMP and TST define CPSR, not use it. 
llvm-svn: 76489
 2009-07-20 22:13:31 +00:00
Bill Wendling
0407ebb4f7 Rename Mangler linkage enums to something less gross. 
llvm-svn: 76456
 2009-07-20 19:41:27 +00:00
David Goodwin
d5865e6c60 Use t2LDRri12 for frame index loads. 
llvm-svn: 76424
 2009-07-20 15:55:39 +00:00
Evan Cheng
2125e12632 Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub fp, #c. 
llvm-svn: 76401
 2009-07-20 06:59:32 +00:00
Evan Cheng
2f6b299d6f Model fpscr to prevent fcmped / fcmpezs etc from being deleted. 
llvm-svn: 76390
 2009-07-20 02:12:31 +00:00
Bill Wendling
1a10a060cb Add plumbing for the `linker_private' linkage type. This type is meant for 
"private" symbols which the assember shouldn't strip, but which the linker may
remove after evaluation. This is mostly useful for Objective-C metadata.

This is plumbing, so we don't have a use of it yet. More to come, etc.

llvm-svn: 76385
 2009-07-20 01:03:30 +00:00
Evan Cheng
fd384e9493 Fix a regression from 76124. Thumb1 instructions default to S bit being true. 
llvm-svn: 76374
 2009-07-19 19:16:46 +00:00
Daniel Dunbar
aca95eac72 Add dependencies from TargetInfo onto .td generation. 
- Shouldn't really be necessary, but currently .inc files get included into
   some main target headers.

llvm-svn: 76349
 2009-07-19 00:21:12 +00:00
Daniel Dunbar
960ef321ca Put Target definitions inside Target specific header, and llvm namespace. 
llvm-svn: 76344
 2009-07-18 23:03:22 +00:00
Jeffrey Yasskin
1669f312b5 r76102 added the MachineCodeEmitter::processDebugLoc call and called it from 
the X86 Emitter.  This patch extends that to the rest of the targets that can
write to a MachineCodeEmitter: ARM, Alpha, and PPC.

llvm-svn: 76211
 2009-07-17 18:49:39 +00:00
Evan Cheng
490d2cc5a4 Fix tSUBspi operand definition. It reads and writes sp, which is a high register. 
llvm-svn: 76155
 2009-07-17 05:43:12 +00:00
Anton Korobeynikov
dc39f4fff8 Emit cross regclass register moves for thumb2. 
Minor code duplication cleanup.

llvm-svn: 76124
 2009-07-16 23:26:06 +00:00
Evan Cheng
7a6b20df7f Let callers decide the sub-register index on the def operand of rematerialized instructions. 
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.

llvm-svn: 75900
 2009-07-16 09:20:10 +00:00
Daniel Dunbar
90536f6737 Kill off <TARGET>MachineModule variables, and <TARGETASMPRINTER>ForceLink 
variables.
 - Module initialization functions supplanted the need for these.

llvm-svn: 75886
 2009-07-16 01:55:13 +00:00
Daniel Dunbar
4771afe104 Lift addAssemblyEmitter into LLVMTargetMachine. 
- No functionality change.

llvm-svn: 75859
 2009-07-15 23:34:19 +00:00
Daniel Dunbar
d85e8b6334 Lift DumpAsm / -print-emitted-asm functionality into LLVMTargetMachine. 
- No intended functionality change.

llvm-svn: 75848
 2009-07-15 22:33:19 +00:00
Daniel Dunbar
3cff9fe21d Remove old style hacks to register AsmPrinter into TargetMachine. 
- No intended functionality change.

llvm-svn: 75843
 2009-07-15 22:01:32 +00:00
Daniel Dunbar
5707dd7f73 Reapply TargetRegistry refactoring commits. 
--- Reverse-merging r75799 into '.':
 U   test/Analysis/PointerTracking
U    include/llvm/Target/TargetMachineRegistry.h
U    include/llvm/Target/TargetMachine.h
U    include/llvm/Target/TargetRegistry.h
U    include/llvm/Target/TargetSelect.h
U    tools/lto/LTOCodeGenerator.cpp
U    tools/lto/LTOModule.cpp
U    tools/llc/llc.cpp
U    lib/Target/PowerPC/PPCTargetMachine.h
U    lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U    lib/Target/PowerPC/PPCTargetMachine.cpp
U    lib/Target/PowerPC/PPC.h
U    lib/Target/ARM/ARMTargetMachine.cpp
U    lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U    lib/Target/ARM/ARMTargetMachine.h
U    lib/Target/ARM/ARM.h
U    lib/Target/XCore/XCoreTargetMachine.cpp
U    lib/Target/XCore/XCoreTargetMachine.h
U    lib/Target/PIC16/PIC16TargetMachine.cpp
U    lib/Target/PIC16/PIC16TargetMachine.h
U    lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U    lib/Target/Alpha/AlphaTargetMachine.cpp
U    lib/Target/Alpha/AlphaTargetMachine.h
U    lib/Target/X86/X86TargetMachine.h
U    lib/Target/X86/X86.h
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U    lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
U    lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U    lib/Target/X86/X86TargetMachine.cpp
U    lib/Target/MSP430/MSP430TargetMachine.cpp
U    lib/Target/MSP430/MSP430TargetMachine.h
U    lib/Target/CppBackend/CPPTargetMachine.h
U    lib/Target/CppBackend/CPPBackend.cpp
U    lib/Target/CBackend/CTargetMachine.h
U    lib/Target/CBackend/CBackend.cpp
U    lib/Target/TargetMachine.cpp
U    lib/Target/IA64/IA64TargetMachine.cpp
U    lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U    lib/Target/IA64/IA64TargetMachine.h
U    lib/Target/IA64/IA64.h
U    lib/Target/MSIL/MSILWriter.cpp
U    lib/Target/CellSPU/SPUTargetMachine.h
U    lib/Target/CellSPU/SPU.h
U    lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U    lib/Target/CellSPU/SPUTargetMachine.cpp
U    lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
U    lib/Target/Mips/MipsTargetMachine.cpp
U    lib/Target/Mips/MipsTargetMachine.h
U    lib/Target/Mips/Mips.h
U    lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U    lib/Target/Sparc/SparcTargetMachine.cpp
U    lib/Target/Sparc/SparcTargetMachine.h
U    lib/ExecutionEngine/JIT/TargetSelect.cpp
U    lib/Support/TargetRegistry.cpp

llvm-svn: 75820
 2009-07-15 20:24:03 +00:00