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Commit Graph

203818 Commits

Author SHA1 Message Date
Simon Pilgrim
c3b840e49c InstCombiner.h - remove unnecessary KnownBits forward declaration. NFCI.
We already include KnownBits.h
2020-09-19 12:53:07 +01:00
Joachim Meyer
d06a70e02e Add -Wno-error=unknown flag to clang-format.
Currently newer clang-format options cannot be included in .clang-format files, if not all users can be forced to use an updated version.
This patch tries to solve this by adding an option to clang-format, enabling to ignore unknown (newer) options.

Differential Revision: https://reviews.llvm.org/D86137
2020-09-19 10:17:57 +02:00
Craig Topper
cba5d6bed8 [X86] Return from SimplifyDemandedBitsForTargetNode after calculating known bits for VSHLI/VSRAI/VSRLI.
We were breaking out of the switch which falls into the default
implementation of SimplifyDemandedBitsForTargetNode which is a
wrapper around computeKnownBits. So we end up doing the recursion
and known bits calculation all over again. Instead we should return
with the known bits we calculated in the switch.
2020-09-18 23:57:01 -07:00
Amara Emerson
3e4cfa99b8 [AArch64][GlobalISel] Add legalization and selection support for <4 x s16> G_SHL. 2020-09-18 23:32:01 -07:00
Xun Li
bc3710453a [ASAN] Properly deal with musttail calls in ASAN
When address sanitizing a function, stack unpinsoning code is inserted before each ret instruction. However if the ret instruciton is preceded by a musttail call, such transformation broke the musttail call contract and generates invalid IR.
This patch fixes the issue by moving the insertion point prior to the musttail call if there is one.

Differential Revision: https://reviews.llvm.org/D87777
2020-09-18 23:10:34 -07:00
Andrew Litteken
c53dab65b4 [IRSim] Adding ilist for IRInstructionData.
The IRInstructionData structs are a different representation of the
program.  This list treats the program as if it was "flattened" and
the only parent is this list.  This lets us easily create ranges of
instructions.

Differential Revision: https://reviews.llvm.org/D86969
2020-09-19 00:18:39 -05:00
Craig Topper
e9b884a465 [X86] Fix copy paste mistake in @ccnp flag.
We were treating @ccp and @ccnp the same.
2020-09-18 21:28:01 -07:00
Craig Topper
2ad28d9322 [X86] Invert the compares in inline-asm-flag-output.ll so that the setcc instruction condition matches the test name. NFC
Also add nounwind to the tests to remove cfi directives.
2020-09-18 21:23:53 -07:00
David Blaikie
4e8a4f6d62 DebugInfo: Cleanup RLE dumping, using a length-constrained DataExtractor rather than carrying the end offset separately 2020-09-18 19:32:38 -07:00
Nico Weber
a5b0afab2f [gn build] (manually) port 5495b691646 2020-09-18 21:27:49 -04:00
Alexander Shaposhnikov
8837f43bbb [llvm-objcopy][MachO] Clean up the interface of Object
Remove the method addLoadCommand which was used only in a single place.
NFC.

Test plan: make check-all
2020-09-18 18:23:27 -07:00
Nico Weber
6200c8c5c9 Revert "[gn build] (manually) port 9b6765e784b3" anf follow-ups
9b6765e784b3 was reverted in 549e55b3d5634.

This reverts commit 442801a7b9b5460114498c48c12b8af40e495188.
This reverts commit 929d91a55616d4fcf4754044b063644807b87fbe.
This reverts commit 7c2d83347f4ea146af1aca72fe289294aaf212be.
2020-09-18 21:14:27 -04:00
Alexander Shaposhnikov
a6c5914f99 [llvm-objcopy][MachO] Add llvm-bitcode-strip driver
This diff adds llvm-bitcode-strip driver to llvm-objcopy.
In the future this will enable us to build a replacement for the tool bitcode_strip.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D87212
2020-09-18 18:13:05 -07:00
Eric Christopher
907ccb4712 Temporarily Revert "RegAllocFast: Rewrite and improve"
as it's breaking a few tests in the lldb test suite.

Bot: http://lab.llvm.org:8011/builders/lldb-arm-ubuntu/builds/4226/steps/test/logs/stdio

This reverts commit c8757ff3aa7dd7a25a6343f6ef74a70c7be04325.
2020-09-18 18:11:21 -07:00
Alexander Shaposhnikov
01222be640 [llvm-install-name-tool] Validate -id value early
The code which validates the value of -id is moved into the function parseInstallNameToolOptions.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D87855
2020-09-18 17:50:08 -07:00
Fangrui Song
90b9ef1425 [LiveDebugValues] Add #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) to suppress -Wunused-function 2020-09-18 17:25:37 -07:00
Amara Emerson
61a3b2fb2b [AArch64][GlobalISel] Add tests for pre-existing selection support for <4 x s16> arithmetic/bitwise ops. 2020-09-18 17:13:55 -07:00
Amara Emerson
7600b7ba0c [AArch64][GlobalISel] Legalize arithmetic ops for <4 x s16> 2020-09-18 17:13:55 -07:00
Vitaly Buka
f298c20805 [NFC][StackSafety] Replace auto with type
Fixes static analyzer is warning.
2020-09-18 17:10:28 -07:00
Fangrui Song
07bdca3215 [SCEV] Fix an unused variable in -DLLVM_ENABLE_ASSERTIONS=off build 2020-09-18 16:19:05 -07:00
Amara Emerson
c373bb64ff [GlobalISel] Add lowering support for G_ABS and use for AArch64.
Differential Revision: https://reviews.llvm.org/D87952
2020-09-18 16:17:18 -07:00
Amy Kwan
be427da523 [PowerPC] Implement Move to VSR Mask builtins in LLVM/Clang
This patch implements the vec_gen[b|h|w|d|q]m function prototypes in altivec.h
in order to utilize the move to VSR with mask instructions introduced in Power10.

Differential Revision: https://reviews.llvm.org/D82725
2020-09-18 18:16:14 -05:00
Philip Reames
eaea7ba7a7 [instcombine][x86] Converted pdep/pext with shifted mask to simple arithmetic
If the mask of a pdep or pext instruction is a shift masked (i.e. one contiguous block of ones) we need at most one and and one shift to represent the operation without the intrinsic. One all platforms I know of, this is faster than the pdep/pext.

The cost modelling for multiple contiguous blocks might be worth exploring in a follow up, but it's not relevant for my current use case. It would almost certainly be a win on AMDs where these are really really slow though.

Differential Revision: https://reviews.llvm.org/D87861
2020-09-18 14:54:24 -07:00
Arthur Eubanks
d4bfedd5af [test][InstrProf] Fix always_inline.ll under NPM
NPM's inliner does not clean up dead functions.

Differential Revision: https://reviews.llvm.org/D87922
2020-09-18 14:50:47 -07:00
Reid Kleckner
e747f6900b [COFF] Move per-global .drective emission from AsmPrinter to TLOFCOFF
This changes the order of output sections and the output assembly, but
is otherwise NFC.

It simplifies the TLOF interface by removing two COFF-only methods.
2020-09-18 14:31:01 -07:00
Vedant Kumar
ea70c5e0ce [llvm-cov] Allow commas in filenames passed to -object flag
Currently, -object takes a comma separated list of objects as an
argument, which prevents it working with path names that contain a
comma. Drop comma-separated support, which requires to set pass the
-object flag multiple times to set multiple objects.

Patch by Andrew Gallagher!

Differential Revision: https://reviews.llvm.org/D87003
2020-09-18 13:46:29 -07:00
Nico Weber
6640720520 clang: Make changes in 7c8bb409f31e py2.7-compatible 2020-09-18 16:15:37 -04:00
Sanjay Patel
8bd14e026c [InstSimplify] add tests for constant folding fmin/fmax with undef op; NFC 2020-09-18 16:09:44 -04:00
Nico Weber
671cddeebe [gn build] add file i forgot to add in 929d91a55616 2020-09-18 16:01:00 -04:00
Nico Weber
28eea2351a [gn build] (manually) port 9b6765e784b3 more 2020-09-18 15:56:34 -04:00
Eric Christopher
f617455845 Temporarily Revert "[SLP] Allow reordering of vectorization trees with reused instructions."
as it's infinite looping on occasion.

This reverts commit 455ca0ebb69210046928fedffe292420a30f89ad.
2020-09-18 12:50:04 -07:00
Nico Weber
9376a275d8 [gn build] Do not sync filenames containing variable references 2020-09-18 15:34:33 -04:00
Krzysztof Parzyszek
f161c48716 Pre-commit test for CSEing masked loads/stores 2020-09-18 14:30:53 -05:00
Nico Weber
cbeef0ae5c [gn build] (manually) port 9b6765e784b3 2020-09-18 15:26:58 -04:00
Simon Pilgrim
327da60d2d [X86][AVX] lowerBuildVectorAsBroadcast - improve BROADCASTM lowering on non-VLX targets
Broadcast to a ZMM type then extract the low subvector.
2020-09-18 19:52:02 +01:00
Arthur Eubanks
b57fa43169 [test][TSan] Fix tests under NPM
Under NPM, the TSan passes are split into a module and function pass. A
couple tests were testing for inserted module constructors, which is
only part of the module pass.
2020-09-18 11:37:55 -07:00
Huihui Zhang
3c26b4961e [InstCombine][SVE] Skip scalable type for InstCombiner::getFlippedStrictnessPredicateAndConstant.
We cannot iterate on scalable vector, the number of elements is unknown at compile-time.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87918
2020-09-18 11:26:36 -07:00
David Blaikie
4972772ef0 Linewrap & remove some dead typedefs from previous commit
Cleanup for 51a505340dfdfdfd9ab32c7267a74db3cdeefa56
2020-09-18 11:22:37 -07:00
David Blaikie
c717659738 DebugInfo: Simplify line table parsing to take all the units together, rather than CUs and TUs separately 2020-09-18 11:18:23 -07:00
James Y Knight
3c2a4cc1bc PR47468: Fix findPHICopyInsertPoint, so that copies aren't incorrectly inserted after an INLINEASM_BR.
findPHICopyInsertPoint special cases placement in a block with a
callbr or invoke in it. In that case, we must ensure that the copy is
placed before the INLINEASM_BR or call instruction, if the register is
defined prior to that instruction, because it may jump out of the
block.

Previously, the code placed it immediately after the last def _or
use_. This is wrong, if the use is the instruction which may jump.  We
could correctly place it immediately after the last def (ignoring
uses), but that is non-optimal for register pressure.

Instead, place the copy after the last def, or before the
call/inlineasm_br, whichever is later.

Differential Revision: https://reviews.llvm.org/D87865
2020-09-18 14:14:04 -04:00
Simon Pilgrim
4b7fc5190e [X86][AVX] Add missing non AVX512VL broadcastm test coverage 2020-09-18 19:11:29 +01:00
Matt Arsenault
c40596b921 CodeGen: Move split block utility to MachineBasicBlock
AMDGPU needs this in several places, so consolidate them here.
2020-09-18 14:05:18 -04:00
Matt Arsenault
b5d406c600 RegAllocFast: Rewrite and improve
This rewrites big parts of the fast register allocator. The basic
strategy of doing block-local allocation hasn't changed but I tweaked
several details:

Track register state on register units instead of physical
registers. This simplifies and speeds up handling of register aliases.
Process basic blocks in reverse order: Definitions are known to end
register livetimes when walking backwards (contrary when walking
forward then uses may or may not be a kill so we need heuristics).

Check register mask operands (calls) instead of conservatively
assuming everything is clobbered.  Enhance heuristics to detect
killing uses: In case of a small number of defs/uses check if they are
all in the same basic block and if so the last one is a killing use.
Enhance heuristic for copy-coalescing through hinting: We check the
first k defs of a register for COPYs rather than relying on there just
being a single definition.  When testing this on the full llvm
test-suite including SPEC externals I measured:

average 5.1% reduction in code size for X86, 4.9% reduction in code on
aarch64. (ranging between 0% and 20% depending on the test) 0.5%
faster compiletime (some analysis suggests the pass is slightly slower
than before, but we more than make up for it because later passes are
faster with the reduced instruction count)

Also adds a few testcases that were broken without this patch, in
particular bug 47278.

Patch mostly by Matthias Braun
2020-09-18 14:05:18 -04:00
Matt Arsenault
a428a9d8a7 Reapply "RegAllocFast: Record internal state based on register units"
The regressions this caused should be fixed when
https://reviews.llvm.org/D52010 is applied.

This reverts commit a21387c65470417c58021f8d3194a4510bb64f46.
2020-09-18 14:05:18 -04:00
Zequan Wu
59b9ad16d6 [CodeGen] emit CG profile for COFF object file
I forgot to add emission of CG profile for COFF object file, when adding the support (https://reviews.llvm.org/D81775)

Differential Revision: https://reviews.llvm.org/D87811
2020-09-18 10:57:54 -07:00
Arthur Eubanks
df42712ac8 [test][HWAsan] Fix kernel-inline.ll under NPM 2020-09-18 10:56:08 -07:00
David Blaikie
2dc313f897 DebugInfo: Tidy up initializing multi-section contributions in DWARFContext 2020-09-18 10:54:43 -07:00
Arthur Eubanks
145867e5d6 [ASan][NewPM] Fix byref-args.ll under NPM 2020-09-18 10:50:53 -07:00
Matt Arsenault
22a074ddad AMDGPU: Don't sometimes allow instructions before lowered si_end_cf
Since 6524a7a2b9ca072bd7f7b4355d1230e70c679d2f, this would sometimes
not emit the or to exec at the beginning of the block, where it really
has to be. If there is an instruction that defines one of the source
operands, split the block and turn the si_end_cf into a terminator.

This avoids regressions when regalloc fast is switched to inserting
reloads at the beginning of the block, instead of spills at the end of
the block.

In a future change, this should always split the block.
2020-09-18 13:43:01 -04:00
Amara Emerson
09bd06838e [AArch64][GlobalISel] Make <8 x s8> of G_BUILD_VECTOR legal. 2020-09-18 10:32:33 -07:00