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c82243e658
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7005 Commits

Author SHA1 Message Date
Anton Korobeynikov
c82243e658 Add testcase for register scanveger assertion fix in r72755 
(double def due to livevars)

llvm-svn: 73096
 2009-06-08 22:54:15 +00:00
David Greene
1f88852460 Add a more robust !if test. 
llvm-svn: 73091
 2009-06-08 22:34:57 +00:00
David Greene
5b0714ad86 Fix DejaGNU run line to escape special characters. 
llvm-svn: 73090
 2009-06-08 22:20:58 +00:00
David Greene
62a2f2fb97 Make IntInits and ListInits typed. This helps deduce types of !if and 
other operators.  For the rare cases where a list type cannot be
deduced, provide a []<type> syntax, where <type> is the list element
type.

llvm-svn: 73078
 2009-06-08 20:23:18 +00:00
David Greene
21ba6012b2 Add a !regmatch operator to do pattern matching in TableGen. 
llvm-svn: 73074
 2009-06-08 17:00:34 +00:00
Eli Friedman
62028b7323 Fix the run-line for this test to work correctly outside of x86. 
llvm-svn: 73025
 2009-06-07 09:44:19 +00:00
Eli Friedman
2964aa5a38 Tweak the expansion code for BIT_CONVERT to generate better code 
converting from an MMX vector to an i64.

llvm-svn: 73024
 2009-06-07 09:41:57 +00:00
Eli Friedman
d4b463b0dc Slightly generalize the code that handles shuffles of consecutive loads 
on x86 to handle more cases.  Fix a bug in said code that would cause it 
to read past the end of an object.  Rewrite the code in 
SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. 
Remove PerformBuildVectorCombine, which is no longer necessary with 
these changes.  In addition to simplifying the code, with this change, 
we can now catch a few more cases of consecutive loads.

llvm-svn: 73012
 2009-06-07 06:52:44 +00:00
Eli Friedman
2b6cb1684f PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec 
instructions.

llvm-svn: 73009
 2009-06-07 01:07:55 +00:00
Eli Friedman
770f633389 PR4340: Run SimplifyDemandedVectorElts on insertelement instructions; 
sometimes it can find simplifications that won't be found otherwise.

llvm-svn: 73006
 2009-06-06 20:08:03 +00:00
Eli Friedman
2dadbd05f9 Fix the expansion for CONCAT_VECTORS so that it doesn't create illegal 
types.

llvm-svn: 72993
 2009-06-06 07:08:26 +00:00
Eli Friedman
4395222136 Avoid crashing on a variable-index insertelement with element type i16. 
llvm-svn: 72991
 2009-06-06 06:32:50 +00:00
Eli Friedman
e546f94ef5 Get rid of some bogus patterns for X86vzmovl. Don't create VZEXT_MOVL 
nodes for vectors with an i16 element type.  Add an optimization for 
building a vector which is all zeros/undef except for the bottom 
element, where the bottom element is an i8 or i16.

llvm-svn: 72988
 2009-06-06 06:05:10 +00:00
Eli Friedman
539325c8e7 Fix an obvious typo. 
llvm-svn: 72987
 2009-06-06 05:55:37 +00:00
Eli Friedman
1227d199be Get rid of a bogus pattern that interferes with optimization. 
llvm-svn: 72985
 2009-06-06 04:17:04 +00:00
Eli Friedman
05eef883e8 PR2598: make sure to expand illegal forms of integer/floating-point 
conversions for x86, like <2 x i32> -> <2 x float> and <4 x i16> -> 
<4 x float>.

llvm-svn: 72983
 2009-06-06 03:57:58 +00:00
Devang Patel
8d170194e8 Add new function attribute - noimplicitfloat 
Update code generator to use this attribute and remove NoImplicitFloat target option.
Update llc to set this attribute when -no-implicit-float command line option is used.

llvm-svn: 72959
 2009-06-05 21:57:13 +00:00
Nate Begeman
058d4eeccf Adapt the x86 build_vector dagcombine to the current state of the legalizer. 
build vectors with i64 elements will only appear on 32b x86 before legalize.
Since vector widening occurs during legalize, and produces i64 build_vector 
elements, the dag combiner is never run on these before legalize splits them
into 32b elements.

Teach the build_vector dag combine in x86 back end to recognize consecutive 
loads producing the low part of the vector.

Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes
since that was required implicitly.

Add a testcase for the transform.

Old:
	subl	$28, %esp
	movl	32(%esp), %eax
	movl	4(%eax), %ecx
	movl	%ecx, 4(%esp)
	movl	(%eax), %eax
	movl	%eax, (%esp)
	movaps	(%esp), %xmm0
	pmovzxwd	%xmm0, %xmm0
	movl	36(%esp), %eax
	movaps	%xmm0, (%eax)
	addl	$28, %esp
	ret

New:
	movl	4(%esp), %eax
	pmovzxwd	(%eax), %xmm0
	movl	8(%esp), %eax
	movaps	%xmm0, (%eax)
	ret

llvm-svn: 72957
 2009-06-05 21:37:30 +00:00
Evan Cheng
ea31ec569b Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then. 
llvm-svn: 72955
 2009-06-05 19:08:58 +00:00
Dan Gohman
31fc8d27b1 Fix an erroneous check for isFNeg; the FNeg case is handled 
a few lines later on.

llvm-svn: 72904
 2009-06-04 23:43:29 +00:00
Bill Wendling
60f5c8184b Fix these so that they work on non-x86 Darwin machines. 
llvm-svn: 72903
 2009-06-04 23:37:19 +00:00
Bill Wendling
b7c990bc90 Specify that this works for Darwin. 
llvm-svn: 72899
 2009-06-04 22:56:29 +00:00
Dan Gohman
5f6f8101d5 Split the Add, Sub, and Mul instruction opcodes into separate 
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt

llvm-svn: 72897
 2009-06-04 22:49:04 +00:00
Devang Patel
9757e4f9f3 Add new function attribute - noredzone. 
Update code generator to use this attribute and remove DisableRedZone target option.
Update llc to set this attribute when -disable-red-zone command line option is used.

llvm-svn: 72894
 2009-06-04 22:05:33 +00:00
Evan Cheng
dada49d18a RALinScan::attemptTrivialCoalescing() was returning a virtual register instead of the physical register it is allocated to. This resulted in virtual register(s) being added the live-in sets. 
llvm-svn: 72890
 2009-06-04 20:53:36 +00:00
Evan Cheng
8a6c448ab0 A value defined by an implicit_def can be liven to a use BB. This is unfortunate. But register allocator still has to add it to the live-in set of the use BB. 
llvm-svn: 72888
 2009-06-04 20:25:48 +00:00
Dale Johannesen
a9a7e5d234 For XTARGET to work on targets not in the list, 
there must also be an XFAIL line.  Fix a couple
examples of this.

llvm-svn: 72876
 2009-06-04 18:27:43 +00:00
Dan Gohman
05fe1217c7 Check in test changes that I accidentally left out of r72872. 
llvm-svn: 72875
 2009-06-04 18:22:31 +00:00
Eli Friedman
11070e275f PR3739, part 2: Use an explicit store to spill XMM registers. (Previously, 
the code tried to use "push", which doesn't exist for XMM registers.)

llvm-svn: 72836
 2009-06-04 02:32:04 +00:00
Eli Friedman
fd27229206 PR3739, part 1: Disable the red zone on Win64. 
llvm-svn: 72830
 2009-06-04 02:02:01 +00:00
Evan Cheng
e3a05e6690 Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface. 
llvm-svn: 72826
 2009-06-04 01:15:28 +00:00
Eli Friedman
dbf32ddf16 PR4317: Handle splits where the new block is unreachable correctly in 
DominatorTreeBase::Split.

llvm-svn: 72810
 2009-06-03 21:42:06 +00:00
Evan Cheng
b71402d6ae For Darwin / x86_64, override -relocation-model=static to pic if the output is assembly since Darwin assembler does not really support -static codeine. 
I view this as a temporary workaround until the assembler / linker changes.

llvm-svn: 72806
 2009-06-03 21:13:54 +00:00
Dan Gohman
6e9ad19ef7 Don't attempt to simplify an non-affine IV expression if it can't 
be simplified to a loop-invariant value. This fixes PR4315.

llvm-svn: 72798
 2009-06-03 19:11:31 +00:00
Evan Cheng
4e47a019ba Fix for PR4225: When rewriter reuse a value in a physical register , it clear the register kill operand marker and its kill ops information. However, the cleared operand may be a def of a super-register. Clear the kill ops info for the super-register's sub-registers as well. 
llvm-svn: 72758
 2009-06-03 09:00:27 +00:00
Evan Cheng
82f8fa333e Temporarily revert 72756 for now. 
llvm-svn: 72757
 2009-06-03 07:40:47 +00:00
Evan Cheng
5afbef29fa Fold preceding / trailing base inc / dec into the single load / store as well. 
llvm-svn: 72756
 2009-06-03 06:14:58 +00:00
Dan Gohman
609f627ed7 Revert r72734. The Darwin assembler doesn't support the static 
relocation model on x86-64. Higher level logic should override
the relocation model to PIC on x86_64-apple-darwin.

llvm-svn: 72746
 2009-06-03 00:37:20 +00:00
Dan Gohman
f6e6588203 Fix CodeGenPrepare's address-mode sinking to handle unusual 
addresses, involving Base values which do not have Pointer type.
This fixes PR4297.

llvm-svn: 72739
 2009-06-02 21:29:13 +00:00
Evan Cheng
7e66d61bec On Darwin x86_64 small code model doesn't guarantee code address fits in 32-bit. 
llvm-svn: 72734
 2009-06-02 20:09:31 +00:00
Evan Cheng
7875093e82 Avoid infinite looping in AllGlobalLoadUsesSimpleEnoughForHeapSRA(). This can happen when PHI uses are recursively dependent on each other. 
llvm-svn: 72710
 2009-06-02 00:56:07 +00:00
Eli Friedman
2b0edc3327 PR4286: Make RewriteLoadUserOfWholeAlloca and 
RewriteStoreUserOfWholeAlloca deal with tail padding because 
isSafeUseOfBitCastedAllocation expects them to.  Otherwise, we crash 
trying to erase the bitcast.

llvm-svn: 72688
 2009-06-01 09:14:32 +00:00
Owen Anderson
928040c625 Be more aggressive in doing LoadPRE by tracing backwards when a block only has 
a single predecessor.

Patch by Jakub Staszak.

llvm-svn: 72661
 2009-05-31 09:03:40 +00:00
Chris Lattner
8ac63163fe fix PR4284, a bug in simplifylibcalls handling memcmp. Patch by 
Benjamin Kramer!

llvm-svn: 72625
 2009-05-30 18:43:04 +00:00
Duncan Sands
3d77d1fcfc Adjust these tests now that "extern inline" 
functions are being output with bodies and
available_externally linkage.

llvm-svn: 72620
 2009-05-30 13:57:05 +00:00
Evan Cheng
2d198e1bc2 (i64 (zext (srl GR32 8))) -> movzbl AH is not safe since srl 8 only clear the top 8 bits. 
llvm-svn: 72618
 2009-05-30 08:43:27 +00:00
Nick Lewycky
a9de2f1c81 Give embedded metadata its own type instead of relying on EmptyStructTy. 
llvm-svn: 72610
 2009-05-30 05:06:04 +00:00
Duncan Sands
f4fe76d46b Dan noticed that the verifier wasn't thoroughly checking uses of 
invoke results (see the testcases).  Tighten up the checking.

llvm-svn: 72586
 2009-05-29 19:39:36 +00:00
Evan Cheng
57f85a1529 Remove an accidental commit. 
llvm-svn: 72560
 2009-05-29 05:28:52 +00:00
Evan Cheng
550fc9ba9f More h-registers tricks: folding zext nodes. 
llvm-svn: 72558
 2009-05-29 01:44:43 +00:00