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Commit Graph

1767 Commits

Author SHA1 Message Date
Anton Korobeynikov
c82243e658 Add testcase for register scanveger assertion fix in r72755
(double def due to livevars)

llvm-svn: 73096
2009-06-08 22:54:15 +00:00
Eli Friedman
62028b7323 Fix the run-line for this test to work correctly outside of x86.
llvm-svn: 73025
2009-06-07 09:44:19 +00:00
Eli Friedman
2964aa5a38 Tweak the expansion code for BIT_CONVERT to generate better code
converting from an MMX vector to an i64.

llvm-svn: 73024
2009-06-07 09:41:57 +00:00
Eli Friedman
d4b463b0dc Slightly generalize the code that handles shuffles of consecutive loads
on x86 to handle more cases.  Fix a bug in said code that would cause it 
to read past the end of an object.  Rewrite the code in 
SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. 
Remove PerformBuildVectorCombine, which is no longer necessary with 
these changes.  In addition to simplifying the code, with this change, 
we can now catch a few more cases of consecutive loads.

llvm-svn: 73012
2009-06-07 06:52:44 +00:00
Eli Friedman
2b6cb1684f PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec
instructions.

llvm-svn: 73009
2009-06-07 01:07:55 +00:00
Eli Friedman
2dadbd05f9 Fix the expansion for CONCAT_VECTORS so that it doesn't create illegal
types.

llvm-svn: 72993
2009-06-06 07:08:26 +00:00
Eli Friedman
4395222136 Avoid crashing on a variable-index insertelement with element type i16.
llvm-svn: 72991
2009-06-06 06:32:50 +00:00
Eli Friedman
e546f94ef5 Get rid of some bogus patterns for X86vzmovl. Don't create VZEXT_MOVL
nodes for vectors with an i16 element type.  Add an optimization for 
building a vector which is all zeros/undef except for the bottom 
element, where the bottom element is an i8 or i16.

llvm-svn: 72988
2009-06-06 06:05:10 +00:00
Eli Friedman
539325c8e7 Fix an obvious typo.
llvm-svn: 72987
2009-06-06 05:55:37 +00:00
Eli Friedman
1227d199be Get rid of a bogus pattern that interferes with optimization.
llvm-svn: 72985
2009-06-06 04:17:04 +00:00
Eli Friedman
05eef883e8 PR2598: make sure to expand illegal forms of integer/floating-point
conversions for x86, like <2 x i32> -> <2 x float> and <4 x i16> -> 
<4 x float>.

llvm-svn: 72983
2009-06-06 03:57:58 +00:00
Nate Begeman
058d4eeccf Adapt the x86 build_vector dagcombine to the current state of the legalizer.
build vectors with i64 elements will only appear on 32b x86 before legalize.
Since vector widening occurs during legalize, and produces i64 build_vector 
elements, the dag combiner is never run on these before legalize splits them
into 32b elements.

Teach the build_vector dag combine in x86 back end to recognize consecutive 
loads producing the low part of the vector.

Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes
since that was required implicitly.

Add a testcase for the transform.

Old:
	subl	$28, %esp
	movl	32(%esp), %eax
	movl	4(%eax), %ecx
	movl	%ecx, 4(%esp)
	movl	(%eax), %eax
	movl	%eax, (%esp)
	movaps	(%esp), %xmm0
	pmovzxwd	%xmm0, %xmm0
	movl	36(%esp), %eax
	movaps	%xmm0, (%eax)
	addl	$28, %esp
	ret

New:
	movl	4(%esp), %eax
	pmovzxwd	(%eax), %xmm0
	movl	8(%esp), %eax
	movaps	%xmm0, (%eax)
	ret

llvm-svn: 72957
2009-06-05 21:37:30 +00:00
Evan Cheng
ea31ec569b Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
llvm-svn: 72955
2009-06-05 19:08:58 +00:00
Dan Gohman
31fc8d27b1 Fix an erroneous check for isFNeg; the FNeg case is handled
a few lines later on.

llvm-svn: 72904
2009-06-04 23:43:29 +00:00
Dan Gohman
5f6f8101d5 Split the Add, Sub, and Mul instruction opcodes into separate
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt

llvm-svn: 72897
2009-06-04 22:49:04 +00:00
Devang Patel
9757e4f9f3 Add new function attribute - noredzone.
Update code generator to use this attribute and remove DisableRedZone target option.
Update llc to set this attribute when -disable-red-zone command line option is used.

llvm-svn: 72894
2009-06-04 22:05:33 +00:00
Evan Cheng
dada49d18a RALinScan::attemptTrivialCoalescing() was returning a virtual register instead of the physical register it is allocated to. This resulted in virtual register(s) being added the live-in sets.
llvm-svn: 72890
2009-06-04 20:53:36 +00:00
Evan Cheng
8a6c448ab0 A value defined by an implicit_def can be liven to a use BB. This is unfortunate. But register allocator still has to add it to the live-in set of the use BB.
llvm-svn: 72888
2009-06-04 20:25:48 +00:00
Dan Gohman
05fe1217c7 Check in test changes that I accidentally left out of r72872.
llvm-svn: 72875
2009-06-04 18:22:31 +00:00
Eli Friedman
11070e275f PR3739, part 2: Use an explicit store to spill XMM registers. (Previously,
the code tried to use "push", which doesn't exist for XMM registers.)

llvm-svn: 72836
2009-06-04 02:32:04 +00:00
Eli Friedman
fd27229206 PR3739, part 1: Disable the red zone on Win64.
llvm-svn: 72830
2009-06-04 02:02:01 +00:00
Evan Cheng
e3a05e6690 Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.
llvm-svn: 72826
2009-06-04 01:15:28 +00:00
Eli Friedman
dbf32ddf16 PR4317: Handle splits where the new block is unreachable correctly in
DominatorTreeBase::Split.

llvm-svn: 72810
2009-06-03 21:42:06 +00:00
Evan Cheng
b71402d6ae For Darwin / x86_64, override -relocation-model=static to pic if the output is assembly since Darwin assembler does not really support -static codeine.
I view this as a temporary workaround until the assembler / linker changes.

llvm-svn: 72806
2009-06-03 21:13:54 +00:00
Evan Cheng
4e47a019ba Fix for PR4225: When rewriter reuse a value in a physical register , it clear the register kill operand marker and its kill ops information. However, the cleared operand may be a def of a super-register. Clear the kill ops info for the super-register's sub-registers as well.
llvm-svn: 72758
2009-06-03 09:00:27 +00:00
Evan Cheng
82f8fa333e Temporarily revert 72756 for now.
llvm-svn: 72757
2009-06-03 07:40:47 +00:00
Evan Cheng
5afbef29fa Fold preceding / trailing base inc / dec into the single load / store as well.
llvm-svn: 72756
2009-06-03 06:14:58 +00:00
Dan Gohman
609f627ed7 Revert r72734. The Darwin assembler doesn't support the static
relocation model on x86-64. Higher level logic should override
the relocation model to PIC on x86_64-apple-darwin.

llvm-svn: 72746
2009-06-03 00:37:20 +00:00
Dan Gohman
f6e6588203 Fix CodeGenPrepare's address-mode sinking to handle unusual
addresses, involving Base values which do not have Pointer type.
This fixes PR4297.

llvm-svn: 72739
2009-06-02 21:29:13 +00:00
Evan Cheng
7e66d61bec On Darwin x86_64 small code model doesn't guarantee code address fits in 32-bit.
llvm-svn: 72734
2009-06-02 20:09:31 +00:00
Evan Cheng
2d198e1bc2 (i64 (zext (srl GR32 8))) -> movzbl AH is not safe since srl 8 only clear the top 8 bits.
llvm-svn: 72618
2009-05-30 08:43:27 +00:00
Evan Cheng
57f85a1529 Remove an accidental commit.
llvm-svn: 72560
2009-05-29 05:28:52 +00:00
Evan Cheng
550fc9ba9f More h-registers tricks: folding zext nodes.
llvm-svn: 72558
2009-05-29 01:44:43 +00:00
Evan Cheng
a36a15ff66 Do not try to create a MVT type of width 0.
llvm-svn: 72557
2009-05-28 23:52:18 +00:00
Eli Friedman
5a376ed43e Add explicit test for PR4280.
llvm-svn: 72539
2009-05-28 21:04:35 +00:00
Eli Friedman
8b0b7c2d6d Add a testcase which got fixed by recent legalization work.
llvm-svn: 72517
2009-05-28 05:10:20 +00:00
Evan Cheng
40810c4d1b Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.
e.g.
orl     $65536, 8(%rax)
=>
orb     $1, 10(%rax)

Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization.

llvm-svn: 72507
2009-05-28 00:35:15 +00:00
Bill Wendling
2944bcd25c This looks like it passes now.
llvm-svn: 72485
2009-05-27 17:43:21 +00:00
Torok Edwin
99b1003c2e Fix PR4254.
The DAGCombiner created a negative shiftamount, stored in an
unsigned variable. Later the optimizer eliminated the shift entirely as being
undefined.
Example: (srl (shl X, 56) 48). ShiftAmt is 4294967288.
Fix it by checking that the shiftamount is positive, and storing in a signed
variable.

llvm-svn: 72331
2009-05-23 17:29:48 +00:00
Torok Edwin
beb86bd0b4 available_externall linkage is not local, this was confusing the codegenerator,
and it wasn't generating calls through @PLT for these functions.
hasLocalLinkage() is now false for available_externally,
I attempted to fix the inliner and dce to handle available_externally properly.
It passed make check.

llvm-svn: 72328
2009-05-23 14:06:57 +00:00
Eli Friedman
262a99ffed Fix test to account for legalization changes; I think this ends up
running an extra DAGCombine pass which improves the code a bit.

llvm-svn: 72326
2009-05-23 13:15:11 +00:00
Duncan Sands
bbd03677ee Add a new codegen pass that normalizes dwarf exception handling
code in preparation for code generation.  The main thing it does
is handle the case when eh.exception calls (and, in a future
patch, eh.selector calls) are far away from landing pads.  Right
now in practice you only find eh.exception calls close to landing
pads: either in a landing pad (the common case) or in a landing
pad successor, due to loop passes shifting them about.  However
future exception handling improvements will result in calls far
from landing pads:
(1) Inlining of rewinds.  Consider the following case:
In function @f:
...
  invoke @g to label %normal unwind label %unwinds
...
unwinds:
  %ex = call i8* @llvm.eh.exception()
...

In function @g:
...
  invoke @something to label %continue unwind label %handler
...
handler:
  %ex = call i8* @llvm.eh.exception()
... perform cleanups ...
  "rethrow exception"

Now inline @g into @f.  Currently this is turned into:
In function @f:
...
  invoke @something to label %continue unwind label %handler
...
handler:
  %ex = call i8* @llvm.eh.exception()
... perform cleanups ...
  invoke "rethrow exception" to label %normal unwind label %unwinds
unwinds:
  %ex = call i8* @llvm.eh.exception()
...

However we would like to simplify invoke of "rethrow exception" into
a branch to the %unwinds label.  Then %unwinds is no longer a landing
pad, and the eh.exception call there is then far away from any landing
pads.

(2) Using the unwind instruction for cleanups.
It would be nice to have codegen handle the following case:
  invoke @something to label %continue unwind label %run_cleanups
...
handler:
... perform cleanups ...
  unwind

This requires turning "unwind" into a library call, which
necessarily takes a pointer to the exception as an argument
(this patch also does this unwind lowering).  But that means
you are using eh.exception again far from a landing pad.

(3) Bugpoint simplifications.  When bugpoint is simplifying
exception handling code it often generates eh.exception calls
far from a landing pad, which then causes codegen to assert.
Bugpoint then latches on to this assertion and loses sight
of the original problem.

Note that it is currently rare for this pass to actually do
anything.  And in fact it normally shouldn't do anything at
all given the code coming out of llvm-gcc!  But it does fire
a few times in the testsuite.  As far as I can see this is
almost always due to the LoopStrengthReduce codegen pass
introducing pointless loop preheader blocks which are landing
pads and only contain a branch to another block.  This other
block contains an eh.exception call.  So probably by tweaking
LoopStrengthReduce a bit this can be avoided.

llvm-svn: 72276
2009-05-22 20:36:31 +00:00
Eli Friedman
b6fe72e457 Fix for PR4235: to build a floating-point value from integer parts,
build an integer and cast that to a float.  This fixes a crash 
caused by trying to split an f32 into two f16's.

This changes the behavior in test/CodeGen/XCore/fneg.ll because that 
testcase now triggers a DAGCombine which converts the fneg into an integer
operation.  If someone is interested, it's probably possible to tweak 
the test to generate an actual fneg.

llvm-svn: 72162
2009-05-20 06:02:09 +00:00
Evan Cheng
ff129ff17f Fix test on non-darwin hosts.
llvm-svn: 72161
2009-05-20 05:45:36 +00:00
Evan Cheng
e17c02e328 Try again. Allow call to immediate address for ELF or when in static relocation mode.
llvm-svn: 72160
2009-05-20 04:53:57 +00:00
Evan Cheng
8a4887572e Cannot use immediate as call absolute target in PIC mode.
llvm-svn: 72154
2009-05-20 01:11:00 +00:00
Bob Wilson
c6726ecca5 Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and
the stack.  Patch by Sandeep Patel.

llvm-svn: 72106
2009-05-19 10:02:36 +00:00
Bob Wilson
ec676a76e7 Fix pr4091: Add support for "m" constraint in ARM inline assembly.
llvm-svn: 72105
2009-05-19 05:53:42 +00:00
Dan Gohman
904f081ce7 Add nounwind to a few tests.
llvm-svn: 72002
2009-05-18 15:16:49 +00:00
Anton Korobeynikov
85accafcba Mark rotl/rotr as expand. This generates pretty ugly code, but this is better than nothing.
llvm-svn: 71976
2009-05-17 10:16:28 +00:00