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Author SHA1 Message Date
Owen Anderson
d144bb1ddc Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization. 
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.

llvm-svn: 118204
 2010-11-03 23:15:26 +00:00
Owen Anderson
1a89511e5d Add support for code generation of the one register with immediate form of vorr. 
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.

llvm-svn: 118201
 2010-11-03 22:44:51 +00:00
Jim Grosbach
6c197e41bf trailing whitespace 
llvm-svn: 118199
 2010-11-03 22:03:20 +00:00
Eric Christopher
3f1ac311ff Just return undef for invalid masks or elts, and since we're doing that, 
just do it earlier too.

llvm-svn: 118195
 2010-11-03 20:44:42 +00:00
Jakob Stoklund Olesen
13bf5713f2 Let RegAllocBasic require MachineDominators - they are already available and 
splitting needs them.

llvm-svn: 118194
 2010-11-03 20:39:26 +00:00
Jakob Stoklund Olesen
7dc4b810ed Tag debug output as regalloc 
llvm-svn: 118193
 2010-11-03 20:39:23 +00:00
Eric Christopher
6b586a109e Optimize generated code for integer materialization a bit. 
llvm-svn: 118192
 2010-11-03 20:21:17 +00:00
Chris Lattner
5280a84fef rename Operand -> AsmOperand for clarity. 
llvm-svn: 118190
 2010-11-03 19:47:34 +00:00
Evan Cheng
72718cf345 Fix test. 
llvm-svn: 118187
 2010-11-03 18:21:33 +00:00
Owen Anderson
98f9965c89 Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead, 
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.

llvm-svn: 118183
 2010-11-03 18:16:27 +00:00
Dale Johannesen
74ebf1b011 This test assumes SSE is present; that is not the default 
on non-X86 hosts.  Hopefully fixes ppc-host buildbot.

llvm-svn: 118182
 2010-11-03 18:08:41 +00:00
Bob Wilson
f44e708279 Add codegen patterns for VST1-lane instructions. Radar 8599955. 
llvm-svn: 118176
 2010-11-03 16:24:53 +00:00
Bob Wilson
0ec96428ba Check for extractelement with a variable operand for the element number. 
For NEON we had been assuming this was always an immediate constant.

llvm-svn: 118175
 2010-11-03 16:24:50 +00:00
Mikhail Glushenkov
991857f132 Rename FindExecutable to PrependMainExecutablePath. 
Makes it more clear that it is just a path manipulation function.

llvm-svn: 118174
 2010-11-03 16:14:16 +00:00
Mikhail Glushenkov
5cbf236c6a 80-col violations, trailing whitespace. 
llvm-svn: 118173
 2010-11-03 16:14:07 +00:00
Duncan Sands
1028fd63a0 Rename PointsToLocalMemory to PointsToLocalOrConstantMemory to make 
the code more self-documenting.

llvm-svn: 118171
 2010-11-03 14:45:05 +00:00
Duncan Sands
41edf30895 Simplify uses of MVT and EVT. An MVT can be compared directly 
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.

llvm-svn: 118169
 2010-11-03 12:17:33 +00:00
Duncan Sands
4bbe978c7c Fix a comment typo. 
llvm-svn: 118168
 2010-11-03 11:55:03 +00:00
Duncan Sands
f6e5e02c9b Inside the calling convention logic LocVT is always a simple 
value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167
 2010-11-03 11:35:31 +00:00
Eric Christopher
719d9d324b If we have an undef mask our Elt will be -1 for our access, handle 
this by using an undef as a pointer.

Fixes rdar://8625016

llvm-svn: 118164
 2010-11-03 09:36:40 +00:00
Duncan Sands
77fde689d9 Fix typo, pointed out by Trevor Harmon. 
llvm-svn: 118163
 2010-11-03 08:16:50 +00:00
Evan Cheng
eab7251695 Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. 
llvm-svn: 118160
 2010-11-03 06:34:55 +00:00
Evan Cheng
b41703bc2f Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. 
llvm-svn: 118152
 2010-11-03 05:14:24 +00:00
Bill Wendling
3894287c96 Put the PC encoding in the correct bit position. 
llvm-svn: 118151
 2010-11-03 04:57:44 +00:00
Eric Christopher
bc79fa1c9e Invert these branches by default, it makes assembly comparisons a little 
easier to read.

llvm-svn: 118148
 2010-11-03 04:29:11 +00:00
Bill Wendling
34599f4aa8 The MC code couldn't handle ARM LDR instructions with negative offsets: 
vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.

llvm-svn: 118144
 2010-11-03 01:49:29 +00:00
Dan Gohman
8071a75d31 Fix DAGCombiner to avoid going into an infinite loop when it 
encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.

llvm-svn: 118143
 2010-11-03 01:47:46 +00:00
Jim Grosbach
90a084bac2 Remove unused function. 
llvm-svn: 118141
 2010-11-03 01:35:15 +00:00
Jim Grosbach
d3213d4048 Remove the no longer used 'Modifier' optional operand to the ARM 
printOperand() asm printer helper functions. rdar://8425198

llvm-svn: 118140
 2010-11-03 01:11:15 +00:00
Jim Grosbach
4d6b503b4c Remove unused function. 
llvm-svn: 118139
 2010-11-03 01:07:48 +00:00
Jim Grosbach
c10d3f3d4b Break ARM addrmode4 (load/store multiple base address) into its constituent 
parts. Represent the operation mode as an optional operand instead.
rdar://8614429

llvm-svn: 118137
 2010-11-03 01:01:43 +00:00
Evan Cheng
67db408634 Two sets of changes. Sorry they are intermingled. 
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
   "optimize for latency". Call instructions don't have the right latency and
   this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
   not # of micro-ops since multi-latency instructions is completely executed
   even when the predicate is false. Also, some instruction will be "slower"
   when they are predicated due to the register def becoming implicit input.
   rdar://8598427

llvm-svn: 118135
 2010-11-03 00:45:17 +00:00
Evan Cheng
e156473432 Modify scheduling itineraries to correct instruction latencies (not operand 
latencies) of loads.

llvm-svn: 118134
 2010-11-03 00:40:22 +00:00
Dan Gohman
67f95d770b Factor code out of APInt to form a isUIntN helper function. 
llvm-svn: 118133
 2010-11-03 00:38:40 +00:00
Chris Lattner
76a122055f fix typo, patch by Trevor Harmon (PR8537) 
llvm-svn: 118131
 2010-11-03 00:30:29 +00:00
Dan Gohman
69a6379472 Print an error as one big string instead of breaking it up. 
llvm-svn: 118130
 2010-11-03 00:24:33 +00:00
Dan Gohman
36d08298f4 Delete unused variables. 
llvm-svn: 118128
 2010-11-03 00:09:12 +00:00
Dan Gohman
4ad5745d44 Remove several unhelpful checks for isValid from sys::Path. 
llvm-svn: 118127
 2010-11-03 00:01:23 +00:00
Eric Christopher
b817a3e8fe Make sure we're only storing a single bit here. 
llvm-svn: 118126
 2010-11-02 23:59:09 +00:00
Chris Lattner
73111ecc25 per a suggestion by Frits van Bommel, mark all MBlaze Pseudo 
instructions as isCodeGenOnly in the parent class instead of
sprinkling it throughout the .td files.

llvm-svn: 118125
 2010-11-02 23:57:05 +00:00
Chris Lattner
5bf66af7ed chase owen. 
llvm-svn: 118124
 2010-11-02 23:55:24 +00:00
Chris Lattner
e6e3c0e4cf tweak this to pass. 
llvm-svn: 118122
 2010-11-02 23:50:17 +00:00
Owen Anderson
f754738bbb Revert r118097 to fix buildbots. 
llvm-svn: 118121
 2010-11-02 23:47:29 +00:00
Chris Lattner
0cfbc490da temporarily xfail this. 
llvm-svn: 118120
 2010-11-02 23:44:50 +00:00
Chris Lattner
d3f7a5d3bd Completely reject instructions that have an operand in their 
ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).

llvm-svn: 118119
 2010-11-02 23:40:41 +00:00
Jakob Stoklund Olesen
1172cd6d88 Tweak the opt -O2 / opt -O3 inliner thresholds to be the same as llvm-gcc and 
clang are using.

llvm-svn: 118118
 2010-11-02 23:40:28 +00:00
Jakob Stoklund Olesen
ea31f5aadd Let the -inline-threshold command line argument take precedence over the 
threshold given to createFunctionInliningPass().

Both opt -O3 and clang would silently ignore the -inline-threshold option.

llvm-svn: 118117
 2010-11-02 23:40:26 +00:00
Dan Gohman
3a69090d70 Don't try to enforce MAXPATHLEN in sys::Path for Unix. OS's can check 
limits on their own.

llvm-svn: 118113
 2010-11-02 23:19:55 +00:00
Chris Lattner
76b970b846 make MatchableInfo::Validate reject instructions (like LDR_PRE in ARM) 
that have complicated tying going on.

llvm-svn: 118112
 2010-11-02 23:18:43 +00:00
Dan Gohman
ea2d1eb5d4 Simplify. 
llvm-svn: 118110
 2010-11-02 23:16:26 +00:00