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428 Commits

Author SHA1 Message Date
Cameron Zwarich
bf5c9cd119 Roll r127459 back in: 
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127498
 2011-03-11 21:52:04 +00:00
Daniel Dunbar
a02706c889 Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get 
created from the", it broke some GCC test suite tests.

llvm-svn: 127477
 2011-03-11 19:30:30 +00:00
Cameron Zwarich
9ed726c151 Optimize trivial branches in CodeGenPrepare, which often get created from the 
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127459
 2011-03-11 04:54:27 +00:00
Bill Wendling
68934338ab * Correct encoding for VSRI. 
* Add tests for VSRI and VSLI.

llvm-svn: 127297
 2011-03-09 00:33:17 +00:00
Bill Wendling
b790c462c0 Correct the encoding for VRSRA and VSRA instructions. 
llvm-svn: 127294
 2011-03-09 00:00:35 +00:00
Bill Wendling
ab9f04b6d8 * Fix VRSHR and VSHR to have the correct encoding for the immediate. 
* Update the NEON shift instruction test to expect what 'as' produces.

llvm-svn: 127293
 2011-03-08 23:48:09 +00:00
Bill Wendling
0e4923ebe5 A few more tests for instruction encodings. 
llvm-svn: 127209
 2011-03-08 02:51:48 +00:00
Bill Wendling
958e854f40 Rename the narrow shift right immediate operands to "shr_imm*" operands. Also 
expand the testing of the narrowing shift right instructions.

No functionality change.

llvm-svn: 127193
 2011-03-07 23:38:41 +00:00
Bill Wendling
304dda7810 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

llvm-svn: 126723
 2011-03-01 01:00:59 +00:00
Chris Lattner
90c8cff37e split this test into arch specific pieces, so the ARM 
test isn't run when the arm backend isn't built.  This
fixes PR9327

llvm-svn: 126500
 2011-02-25 19:06:35 +00:00
Joerg Sonnenberger
9c30c492df Restore r125595 (reverted in r126336) with modifications: 
Introduce a variable in the AsmParserExtension whether [] is valid in an
expression. If it is true, parse them like (). Enable this for ELF only.

llvm-svn: 126443
 2011-02-24 21:59:22 +00:00
Devang Patel
bac565c8a3 Move arch specific tests in arch specific directories. 
llvm-svn: 126401
 2011-02-24 19:06:27 +00:00
Bruno Cardoso Lopes
ad05904e0b Add assembly parsing support for "msr" and also fix its encoding. Also add 
testcases for the disassembler to make sure it still works for "msr".

llvm-svn: 125948
 2011-02-18 19:45:59 +00:00
Bruno Cardoso Lopes
e65a98b127 Fix encoding and add parsing support for the arm/thumb CPS instruction: 
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
  from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
  wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.

llvm-svn: 125489
 2011-02-14 13:09:44 +00:00
Jim Grosbach
48e8554772 Do AsmMatcher operand classification per-opcode. 
When matching operands for a candidate opcode match in the auto-generated
AsmMatcher, check each operand against the expected operand match class.
Previously, operands were classified independently of the opcode being
handled, which led to difficulties when operand match classes were
more complicated than simple subclass relationships.

llvm-svn: 125245
 2011-02-10 00:08:28 +00:00
Bruno Cardoso Lopes
0ce5b0f4a8 Add support for parsing dmb/dsb instructions 
llvm-svn: 125055
 2011-02-07 22:09:15 +00:00
Jason W Kim
7342155b4c Teach ARM/MC/ELF about gcc compatible reloc output to get past odd linkage 
failures with relocations.

The code committed is a first cut at compatibility for emitted relocations in
ELF .o.

Why do this? because existing ARM tools like emitting relocs symbols as
explicit relocations, not as section-offset relocs.

Result is that with these changes,
1) relocs are now substantially identical what to gcc outputs.
2) larger apps (including many spec2k tests) compile, cross-link, and pass

Added reminder fixme to tests for future conversion to .s form.

llvm-svn: 124996
 2011-02-07 01:11:15 +00:00
Jason W Kim
056e5aacb7 Teach ARM/MC/ELF about EF_ARM_EABI_VERSION. The magic number is set to 
5 to match the current doc.
Added FIXME reminder Make it really configurable later.

llvm-svn: 124899
 2011-02-04 21:41:11 +00:00
Jason W Kim
10c1a81736 Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps. 
(yes, this is different from R_ARM_CALL)

- Adds a new method getARMBranchTargetOpValue() which handles the
  necessary distinction between the conditional and unconditional br/bl
  needed for ARM/ELF

At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...

Added a few FIXME's for future naming fixups in ARMInstrInfo.td

llvm-svn: 124895
 2011-02-04 19:47:15 +00:00
Evan Cheng
dc27913f2d Fix test for non-darwin targets. 
llvm-svn: 124640
 2011-02-01 01:16:18 +00:00
Evan Cheng
2042be8132 Fix PLD encoding. 
llvm-svn: 124458
 2011-01-27 23:48:34 +00:00
Bruno Cardoso Lopes
228d126d6f Add encoding testcases for ARM vcvtr variations 
llvm-svn: 124289
 2011-01-26 13:53:38 +00:00
Bruno Cardoso Lopes
2d6bd03b18 fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions 
llvm-svn: 124288
 2011-01-26 13:28:14 +00:00
Bruno Cardoso Lopes
2f96371a7a Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm", 
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.

llvm-svn: 123975
 2011-01-21 14:07:40 +00:00
Bruno Cardoso Lopes
dc3853d7b5 Add testcases for clz encoding 
llvm-svn: 123937
 2011-01-20 19:27:16 +00:00
Bruno Cardoso Lopes
6aeb2e320f Fix the encoding and parsing of clrex instruction 
llvm-svn: 123936
 2011-01-20 19:18:32 +00:00
Bruno Cardoso Lopes
5f06c0aa3b Add cdp/cdp2 instructions for thumb/thumb2 
llvm-svn: 123929
 2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes
3584c02d83 - Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present 
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.

llvm-svn: 123927
 2011-01-20 18:06:58 +00:00
Bruno Cardoso Lopes
75712e8a7a Add mcr*2 and mr*c2 support to thumb2 targets 
llvm-svn: 123919
 2011-01-20 16:58:48 +00:00
Bruno Cardoso Lopes
f377d1721e Add mcr* and mr*c support to thumb targets 
llvm-svn: 123917
 2011-01-20 16:35:57 +00:00
Bruno Cardoso Lopes
0f7a30b1cb Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc 
llvm-svn: 123837
 2011-01-19 16:56:52 +00:00
Owen Anderson
ed4acd59cb When matching asm operands, always try to match the most restricted type first. 
Unfortunately, while this is the "right" thing to do, it breaks some ARM
asm parsing tests because MemMode5 and ThumbMemModeReg are ambiguous.  This
is tricky to resolve since neither is a subset of the other.

XFAIL the test for now.  The old way was broken in other ways, just ways
we didn't happen to be testing, and our ARM asm parsing is going to require
significant revisiting at a later point anyways.

llvm-svn: 123786
 2011-01-18 23:01:21 +00:00
Bruno Cardoso Lopes
e0f8fee637 Create two new generic classes to represent the following VMRS/VMSR variations: 
vmrs  reg, fpexc
vmrs  reg, fpsid
vmsr  fpexc, reg
vmsr  fpsid, reg

llvm-svn: 123783
 2011-01-18 21:58:20 +00:00
Bruno Cardoso Lopes
82c6fe3dfe Fix MRS encoding for arm and thumb. 
llvm-svn: 123778
 2011-01-18 21:31:35 +00:00
Bruno Cardoso Lopes
6e4c5af01e Fix the encoding of t2ISB by using the right class and also parse it correctly 
llvm-svn: 123776
 2011-01-18 21:17:09 +00:00
Bruno Cardoso Lopes
c1e21b06b9 Follow the current hack set and enable the correct parsing of bkpt while in thumb mode. 
llvm-svn: 123772
 2011-01-18 20:55:11 +00:00
Bruno Cardoso Lopes
94247155c4 Add support for parsing and encoding ARM's official syntax for the BFI instruction 
llvm-svn: 123770
 2011-01-18 20:45:56 +00:00
Daniel Dunbar
ba39b2fdc1 McARM: Start marking T2 address operands as such, for the benefit of the parser. 
llvm-svn: 123722
 2011-01-18 03:06:03 +00:00
Evan Cheng
0cdd5547f1 Completed :lower16: / :upper16: support for movw / movt pairs on Darwin. 
- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.

llvm-svn: 123424
 2011-01-14 02:38:49 +00:00
Evan Cheng
cc474b4864 Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step 
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.

llvm-svn: 123369
 2011-01-13 07:58:56 +00:00
Bill Wendling
e82361731d Sort the register list based on the *actual* register numbers rather than the 
enum values we give to them. <rdar://problem/8823730>

llvm-svn: 123321
 2011-01-12 21:20:59 +00:00
Jason W Kim
ae183f9862 1. Support ELF pcrel relocations for movw/movt: 
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)

llvm-svn: 123294
 2011-01-12 00:19:25 +00:00
Jason W Kim
db6eddeea3 Workaround for bug 8721. 
.s Test added.

llvm-svn: 123292
 2011-01-11 23:53:41 +00:00
Daniel Dunbar
fbc0b96c34 McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the 
carry setting flag from the mnemonic.

Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.

llvm-svn: 123238
 2011-01-11 15:59:50 +00:00
Daniel Dunbar
0e9ece99bb McARM: Flush out hard coded known non-predicated mnemonic list. 
llvm-svn: 123189
 2011-01-10 21:01:03 +00:00
Bob Wilson
438a9a1367 Add Neon VCVT instructions for f32 <-> f16 conversions. 
Clang is now providing intrinsics for these and so we need to support them
in the backend.  Radar 8068427.

llvm-svn: 121902
 2010-12-15 22:14:12 +00:00
Bob Wilson
1082705e72 Fix misspelled target triples in MC/ARM test commands. 
llvm-svn: 121901
 2010-12-15 22:14:01 +00:00
Kevin Enderby
6b3ae489f8 Add some more MC tests for ARM arithmetic instructions that update or don't 
update the condition codes.  These come from my test generator and are just
the ones that MC currently assembles correctly.

llvm-svn: 121830
 2010-12-15 01:24:36 +00:00
Daniel Dunbar
3f9b9dc852 MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup. 
llvm-svn: 121772
 2010-12-14 17:37:16 +00:00
Kevin Enderby
55cb19813e Add support for parsing ARM arithmetic instructions that update or don't update 
the condition codes.  Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix.  The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present.  Four simple test cases added for now, lots more to come.

llvm-svn: 121401
 2010-12-09 19:19:43 +00:00
Jim Grosbach
8cef570ed9 Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order 
halfword being emitted to the stream first. rdar://8728174

llvm-svn: 120848
 2010-12-03 22:31:40 +00:00
Owen Anderson
e2a8781847 Add tests for more forms of Thumb2 loads and stores. 
llvm-svn: 120436
 2010-11-30 18:15:21 +00:00
Bill Wendling
ae920bcc50 Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost 
certainly be made more generic. But it does allow us to parse something like:

          ldr     r3, [r2, r4]

correctly in Thumb mode.

llvm-svn: 120408
 2010-11-30 07:44:32 +00:00
Owen Anderson
b6e1c56c79 Correct Thumb2 encodings for a much wider range of loads and stores. 
llvm-svn: 120364
 2010-11-30 00:14:31 +00:00
Owen Anderson
14abbb1a2e Provide Thumb2 encodings for basic loads and stores. 
llvm-svn: 120340
 2010-11-29 22:44:32 +00:00
Bill Wendling
c0055893db Add more Thumb encodings. 
llvm-svn: 120279
 2010-11-29 01:07:48 +00:00
Bill Wendling
b54752da15 More Thumb encodings. 
llvm-svn: 120278
 2010-11-29 01:00:43 +00:00
Bill Wendling
8f0b624061 Add Thumb encodings for REV instructions. 
llvm-svn: 120277
 2010-11-29 00:42:50 +00:00
Bill Wendling
d233cab1eb Add more Thumb encodings. 
llvm-svn: 120272
 2010-11-29 00:18:15 +00:00
Bill Wendling
a472e7be70 Add encoding for ARM "trap" instruction. 
llvm-svn: 119938
 2010-11-21 11:05:29 +00:00
Bill Wendling
50a1812023 Add MC encodings for some Thumb instructions. Test for a few of them. The "bx 
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...

llvm-svn: 119774
 2010-11-19 01:33:10 +00:00
Bill Wendling
ef43273c51 Add support for parsing the writeback ("!") token. 
llvm-svn: 119761
 2010-11-18 23:43:05 +00:00
Owen Anderson
c0d5d13769 More tests. 
llvm-svn: 119756
 2010-11-18 23:30:10 +00:00
Owen Anderson
ca14474db4 Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2. 
llvm-svn: 119755
 2010-11-18 23:29:56 +00:00
Owen Anderson
25dc3a4fe6 More Thumb2 encodings. 
llvm-svn: 119737
 2010-11-18 21:15:19 +00:00
Owen Anderson
eec8c82d32 Fill out the set of Thumb2 multiplication operator encodings. 
llvm-svn: 119733
 2010-11-18 20:32:18 +00:00
Owen Anderson
b7970b2c6a Try again at providing Thumb2 encodings for basic multiplication operators. 
llvm-svn: 119601
 2010-11-18 01:08:42 +00:00
Owen Anderson
e8906ba112 Revert r119593 while I figure out my testing disagrees with the buildbot. 
llvm-svn: 119597
 2010-11-18 00:42:51 +00:00
Owen Anderson
47a64ab90c Provide correct Thumb2 encodings for basic multiplication operators. 
llvm-svn: 119593
 2010-11-18 00:19:10 +00:00
Owen Anderson
ea6ac4cdff Second attempt at correct encodings for Thumb2 bitfield instructions. 
llvm-svn: 119575
 2010-11-17 22:16:31 +00:00
Owen Anderson
2adebbb603 Revert r119551, which broke buildbots. 
llvm-svn: 119555
 2010-11-17 20:48:51 +00:00
Owen Anderson
c7750780fc Provide Thumb2 encodings for bitfield instructions. 
llvm-svn: 119551
 2010-11-17 20:35:29 +00:00
Owen Anderson
d88cfe5453 More miscellaneous Thumb2 encodings. 
llvm-svn: 119546
 2010-11-17 19:57:38 +00:00
Bill Wendling
f0a1acba8c Proper encoding for VLDM and VSTM instructions. The register lists for these 
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.

llvm-svn: 119460
 2010-11-17 04:32:08 +00:00
Bill Wendling
e15bf6b98d Test encodings for LDM and STM. 
llvm-svn: 119315
 2010-11-16 01:38:20 +00:00
Owen Anderson
686fae59e6 Add Thumb2 encodings for mov and friends. 
llvm-svn: 119295
 2010-11-16 00:29:56 +00:00
Owen Anderson
db1a4541c2 Provide Thumb2 encodings for sxtb and friends. 
llvm-svn: 119185
 2010-11-15 21:12:05 +00:00
Owen Anderson
0bb2efeb7d Add Thumb2 encodings for comparison and shift operators. 
llvm-svn: 119176
 2010-11-15 19:58:36 +00:00
Owen Anderson
5ae5db8931 Add correct Thumb2 encodings for mvn and friends. 
llvm-svn: 119170
 2010-11-15 18:45:17 +00:00
Owen Anderson
f1ffc8fdc9 First stab at providing correct Thumb2 encodings, start with adc. 
llvm-svn: 118924
 2010-11-12 21:12:40 +00:00
Owen Anderson
85cf1b8ff5 Fill out support for Thumb2 encodings of NEON instructions. 
llvm-svn: 118854
 2010-11-11 23:12:55 +00:00
Owen Anderson
0913dac245 Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4]. 
llvm-svn: 118843
 2010-11-11 21:36:43 +00:00
Owen Anderson
7fda1a6efd Flesh out tests for Thumb2 encodings of NEON instructions. 
llvm-svn: 118837
 2010-11-11 21:15:47 +00:00
Owen Anderson
f43f09f6f6 Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure. 
More tests to come.

llvm-svn: 118819
 2010-11-11 19:07:48 +00:00
Owen Anderson
52e3873edc Add support for ARM's specialized vector-compare-against-zero instructions. 
llvm-svn: 118453
 2010-11-08 23:21:22 +00:00
Owen Anderson
add19dd6dd Add codegen and encoding support for the immediate form of vbic. 
llvm-svn: 118291
 2010-11-05 19:27:46 +00:00
Bill Wendling
990c247994 Add encoding for VSTR. 
llvm-svn: 118220
 2010-11-04 00:59:42 +00:00
Owen Anderson
d144bb1ddc Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization. 
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.

llvm-svn: 118204
 2010-11-03 23:15:26 +00:00
Owen Anderson
1a89511e5d Add support for code generation of the one register with immediate form of vorr. 
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.

llvm-svn: 118201
 2010-11-03 22:44:51 +00:00
Owen Anderson
98f9965c89 Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead, 
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.

llvm-svn: 118183
 2010-11-03 18:16:27 +00:00
Bill Wendling
34599f4aa8 The MC code couldn't handle ARM LDR instructions with negative offsets: 
vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.

llvm-svn: 118144
 2010-11-03 01:49:29 +00:00
Bill Wendling
1546322a9c Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work 
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.

llvm-svn: 118094
 2010-11-02 22:31:46 +00:00
Owen Anderson
cdd587157f Provide correct encodings for the remaining vst variants that we currently generate. 
llvm-svn: 118087
 2010-11-02 22:18:18 +00:00
Owen Anderson
46d4ab1a87 Add correct encodings for basic variants for vst3 and vst4. 
llvm-svn: 118082
 2010-11-02 21:47:03 +00:00
Owen Anderson
36d5c04fbd Add correct encodings for the basic variants for vst2. 
llvm-svn: 118068
 2010-11-02 21:16:58 +00:00
Owen Anderson
c9f6909c96 Add correct encodings for the basic form of vst1. 
llvm-svn: 118067
 2010-11-02 21:06:06 +00:00
Owen Anderson
ee1337c01f Add correct encodings for the rest of the vld instructions that we generate. 
llvm-svn: 118053
 2010-11-02 20:40:59 +00:00
Owen Anderson
9d85c89ade Add correct NEON encodings for vld2, vld3, and vld4 basic variants. 
llvm-svn: 117997
 2010-11-02 01:24:55 +00:00
Owen Anderson
6647eb222b Add correct NEON encodings for the "multiple single elements" form of vld. 
llvm-svn: 117984
 2010-11-02 00:05:05 +00:00
Bill Wendling
af717e3c58 Use ARM-style comments. 
llvm-svn: 117955
 2010-11-01 21:16:39 +00:00
Owen Anderson
09920faec7 Use ARM-style comment syntax. 
llvm-svn: 117941
 2010-11-01 18:33:37 +00:00
Owen Anderson
dbba9bcc36 Covert this test to .s form. 
llvm-svn: 117939
 2010-11-01 18:30:39 +00:00
Owen Anderson
38af2df6e5 Convert this test to .s form. 
llvm-svn: 117938
 2010-11-01 18:26:43 +00:00
Owen Anderson
8d4bfde002 Covert this test to .s form. 
llvm-svn: 117937
 2010-11-01 18:13:11 +00:00
Owen Anderson
d5757a8585 Covert this test to .s form. 
llvm-svn: 117935
 2010-11-01 18:03:16 +00:00
Jim Grosbach
76910aa62f Mark ARM subtarget features that are available for the assembler. 
llvm-svn: 117929
 2010-11-01 16:59:54 +00:00
Owen Anderson
ccef9fc4fc Convert this test to .s form. 
llvm-svn: 117900
 2010-11-01 05:23:58 +00:00
Bill Wendling
b68e0d0ee3 Some instructions end with an "ls" prefix, but it doesn't indicate that they are 
conditional. Check for those instructions explicitly.

llvm-svn: 117747
 2010-10-29 23:50:21 +00:00
Owen Anderson
ccbb8e7b65 Convert this test to .s form. 
llvm-svn: 117708
 2010-10-29 20:39:19 +00:00
Owen Anderson
7e3af87961 Convert this test to .s form. 
llvm-svn: 117704
 2010-10-29 20:23:45 +00:00
Owen Anderson
1b3d8432b1 Convert this test to .s form. 
llvm-svn: 117699
 2010-10-29 20:17:07 +00:00
Owen Anderson
fc007fef16 Convert this test to .s form. 
llvm-svn: 117696
 2010-10-29 20:12:34 +00:00
Owen Anderson
2119e59322 Covert this test to .s form. 
llvm-svn: 117694
 2010-10-29 19:56:07 +00:00
Owen Anderson
b75ef99b0c Convert this test to .s form. 
llvm-svn: 117693
 2010-10-29 19:51:11 +00:00
Owen Anderson
9e3265d3da Convert this test to .s form. 
llvm-svn: 117690
 2010-10-29 19:45:32 +00:00
Owen Anderson
f9a6495d0a Convert this test to .s form. 
llvm-svn: 117689
 2010-10-29 19:37:05 +00:00
Owen Anderson
8fb42c665e Convert this test to .s form. 
llvm-svn: 117686
 2010-10-29 19:17:08 +00:00
Owen Anderson
230358caab Convert this test to .s form. 
llvm-svn: 117685
 2010-10-29 19:09:08 +00:00
Owen Anderson
4176d55f79 Covert this test to .s form. 
llvm-svn: 117684
 2010-10-29 19:05:26 +00:00
Owen Anderson
cc7d9dcb52 Convert this test to .s form. 
llvm-svn: 117683
 2010-10-29 18:58:30 +00:00
Owen Anderson
4e1532000b Convert this test to .s form. 
llvm-svn: 117682
 2010-10-29 18:48:59 +00:00
Owen Anderson
a84837747c Convert this file to less fragile .s form. 
llvm-svn: 117681
 2010-10-29 18:41:40 +00:00
Owen Anderson
8e290aafbd Replace this test with the less fragile .s version. Still XFAIL'd, since the ASM parser doesn't parse vabal yet. 
llvm-svn: 117679
 2010-10-29 18:31:26 +00:00
Owen Anderson
840931e8ed Covert this test to a .s file to reduce fragility. 
llvm-svn: 117676
 2010-10-29 18:18:40 +00:00
Owen Anderson
9930e7bcb6 Convert this test to a .s file, so that it's not sensitive to codegen changes. 
llvm-svn: 117633
 2010-10-29 01:01:56 +00:00
Chris Lattner
115cd02d22 add simple support for addrmode5 operands, allowing 
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626
 2010-10-29 00:27:31 +00:00
Chris Lattner
1917294eb5 most simple arm instructions match correctly now, 
it looks like we're not handling [] operands though

llvm-svn: 117607
 2010-10-28 21:31:07 +00:00
Chris Lattner
bd838d16e5 fix the asmmatcher generator to handle targets with no RegisterPrefix 
(like ARM) correctly.  With this change, we can now match "bx lr"
because we recognize lr as a register.

llvm-svn: 117606
 2010-10-28 21:28:42 +00:00
Evan Cheng
72be097417 Disable most of the ARM vfp / NEON MC tests. These are too fragile to be useful. 
I'll work with Jim, Owen, and Bill on an alternative testing strategy until
the assembly parser is available.

llvm-svn: 117530
 2010-10-28 06:46:17 +00:00
Owen Anderson
e75f7c5419 Add correct NEON encodings for vtbl and vtbx. 
llvm-svn: 117513
 2010-10-28 00:18:46 +00:00
Owen Anderson
008116cb71 Add correct NEON encodings for vext, vtrn, vuzp, and vzip. 
llvm-svn: 117512
 2010-10-27 23:56:39 +00:00
Owen Anderson
27049dbce3 Tests for NEON encoding of vrev. 
llvm-svn: 117502
 2010-10-27 22:54:49 +00:00
Owen Anderson
9437a20a72 Provide correct encodings for NEON vcvt, which has its own special immediate encoding 
for specifying fractional bits for fixed point conversions.

llvm-svn: 117501
 2010-10-27 22:49:00 +00:00
Owen Anderson
d28d229ded Provide correct encodings for the get_lane and set_lane variants of vmov. 
llvm-svn: 117495
 2010-10-27 21:28:09 +00:00
Owen Anderson
7c46fcfee4 Provide correct NEON encodings for vdup. 
llvm-svn: 117475
 2010-10-27 19:25:54 +00:00
Owen Anderson
dbed42aff5 Tests for NEON encoding of vmovl, vmovn, vqmovn, and vqmovun. 
llvm-svn: 117469
 2010-10-27 18:17:12 +00:00
Owen Anderson
25d75e80ba Tests for NEON encoding of vcls, vclz, and vcnt. 
llvm-svn: 117466
 2010-10-27 18:05:25 +00:00
Owen Anderson
a5643da004 Tests for NEON encoding of vneg and vqneg. 
llvm-svn: 117463
 2010-10-27 17:57:26 +00:00
Owen Anderson
32da0e6e3f Tests for NEON encoding of vabs and vqabs. 
llvm-svn: 117460
 2010-10-27 17:50:07 +00:00
Owen Anderson
c8757eb137 Add correct NEON encodings for vsli and vsri. 
llvm-svn: 117459
 2010-10-27 17:40:08 +00:00
Owen Anderson
e64b7187a9 Add correct NEON encodings for vsra and vrsra. 
llvm-svn: 117458
 2010-10-27 17:29:29 +00:00
Owen Anderson
1dc05f20e2 Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun. 
llvm-svn: 117411
 2010-10-26 22:50:46 +00:00
Owen Anderson
55c0bad37d Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn. 
llvm-svn: 117402
 2010-10-26 21:58:41 +00:00
Owen Anderson
71deab0da0 Add tests for NEON encoding of vshll. 
llvm-svn: 117399
 2010-10-26 21:21:47 +00:00
Owen Anderson
31c1429a2c Tests for NEON encoding of vshr. 
llvm-svn: 117396
 2010-10-26 21:08:42 +00:00
Owen Anderson
0cecbd810e Provide correct NEON encodings for vshl, register and immediate forms. 
llvm-svn: 117394
 2010-10-26 20:56:57 +00:00
Owen Anderson
ee9f7e6c20 Tests for NEON encoding of vrecpe, vrecps, vrsqrte, and vsqrts. 
llvm-svn: 117385
 2010-10-26 18:43:13 +00:00
Owen Anderson
9e49cae184 Tests for NEON encodings of vpmin and vpmax. 
llvm-svn: 117382
 2010-10-26 18:31:47 +00:00
Owen Anderson
d8e5d26a56 Add correct NEON encoding for vpadal. 
llvm-svn: 117380
 2010-10-26 18:18:03 +00:00
Owen Anderson
1940ad62ca Tests for NEON encoding of vpadd and vpaddl. 
llvm-svn: 117377
 2010-10-26 18:04:51 +00:00
Owen Anderson
b7618a821f Add NEON encodings for vmov and vmvn of immediates. 
llvm-svn: 117374
 2010-10-26 17:40:54 +00:00
Bob Wilson
309484bb46 When the "true" and "false" blocks of a diamond if-conversion are the same, 
do not double-count the duplicate instructions by counting once from the
beginning and again from the end.  Keep track of where the duplicates from
the beginning ended and don't go past that point when counting duplicates
at the end.  Radar 8589805.

This change causes one of the MC/ARM/simple-fp-encoding tests to produce
different (better!) code without the vmovne instruction being tested.
I changed the test to produce vmovne and vmoveq instructions but moving
between register files in the opposite direction.  That's not quite the same
but predicated versions of those instructions weren't being tested before,
so at least the test coverage is not any worse, just different.

llvm-svn: 117333
 2010-10-26 00:02:24 +00:00
Owen Anderson
67684a0bae Tests for NEON encoding of vmax. 
llvm-svn: 117327
 2010-10-25 23:45:34 +00:00
Owen Anderson
10a13e5063 Tests for NEON encoding of vmin. 
llvm-svn: 117326
 2010-10-25 23:35:36 +00:00
Owen Anderson
e5e0dcd665 Add correct encodings for NEON vabal. 
llvm-svn: 117315
 2010-10-25 21:29:04 +00:00
Owen Anderson
3eff0b86a5 Add correct NEON encodings for vaba. 
llvm-svn: 117309
 2010-10-25 20:52:57 +00:00
Owen Anderson
a45478aef9 Tests for NEON encoding of vabdl. 
llvm-svn: 117303
 2010-10-25 20:36:28 +00:00
Owen Anderson
3e03c142fd Add tests for NEON encoding of vabd. 
llvm-svn: 117302
 2010-10-25 20:29:27 +00:00
Owen Anderson
61f5b3f2dc Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment. 
llvm-svn: 117294
 2010-10-25 20:17:22 +00:00
Owen Anderson
072692331e Provide correct NEON encodings for vbsl. 
llvm-svn: 117293
 2010-10-25 20:13:13 +00:00
Owen Anderson
59e85cbd66 Add correct instruction encodings for vbic, vorn, and vmvn. 
llvm-svn: 117282
 2010-10-25 18:43:52 +00:00
Owen Anderson
2824342fac Provide correct NEON encodings for vand, veor, and vorr. 
llvm-svn: 117279
 2010-10-25 18:28:30 +00:00
Owen Anderson
1693a4c5d5 Add tests for NEON encoding of vtst. 
llvm-svn: 117277
 2010-10-25 18:10:34 +00:00
Owen Anderson
ba261b092c Add NEON encoding tests for vcgt and vacgt. 
llvm-svn: 117276
 2010-10-25 18:03:59 +00:00
Owen Anderson
3a5f798790 Add tests for NEON encodings of vcge and vacge. 
llvm-svn: 117274
 2010-10-25 17:49:32 +00:00
Owen Anderson
757022131f Add a warning about our inability to test the encoding of vceq with immediate zero. 
llvm-svn: 117273
 2010-10-25 17:33:02 +00:00
Owen Anderson
8ad139dce6 Add tests for NEON encoding of vceq. 
llvm-svn: 117270
 2010-10-25 17:20:26 +00:00
Owen Anderson
d7968b1d9c Add tests for NEON encoding of vsubhn and vrsubhn. 
llvm-svn: 117269
 2010-10-25 17:12:46 +00:00
Owen Anderson
2710687363 Add tests for NEON encoding of vqsub. 
llvm-svn: 117214
 2010-10-23 18:02:16 +00:00
Owen Anderson
1e091f8c58 Add tests for NEON encoding of vhsub. 
llvm-svn: 117189
 2010-10-22 23:58:22 +00:00
Jim Grosbach
7de028efd2 Add a CMP test. 
llvm-svn: 117187
 2010-10-22 23:48:01 +00:00
Owen Anderson
3416940e43 Add tests for NEON encoding of vsubw. 
llvm-svn: 117186
 2010-10-22 23:46:07 +00:00
Owen Anderson
a9c3c6c610 Add tests for NEON encoding of vsubl. 
llvm-svn: 117183
 2010-10-22 23:36:36 +00:00
Owen Anderson
8bc3d6ec45 Add tests for NEON encoding of vsub. 
llvm-svn: 117177
 2010-10-22 23:21:04 +00:00
Owen Anderson
2d807f4ed0 Add tests for NEON encoding of vqdmlsl. 
llvm-svn: 117173
 2010-10-22 23:08:47 +00:00
Owen Anderson
593d941f2f Add tests for NEON encoding of vmlsl. 
llvm-svn: 117171
 2010-10-22 23:02:27 +00:00
Jim Grosbach
de52e11864 tidy up. 
llvm-svn: 117166
 2010-10-22 22:15:48 +00:00
Jim Grosbach
bba77cca02 ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. 
llvm-svn: 117165
 2010-10-22 22:12:16 +00:00
Owen Anderson
8c38a57413 Add tests for the correct encoding of NEON vmls. 
llvm-svn: 117145
 2010-10-22 20:31:24 +00:00
Owen Anderson
424434414e Add correct NEON encodings for vqdmlal. 
llvm-svn: 117134
 2010-10-22 19:35:48 +00:00
Jim Grosbach
10195e9b73 Add the encoding information for the rest of the ARM mode multiply instructions. 
llvm-svn: 117133
 2010-10-22 19:15:30 +00:00
Owen Anderson
2bbdc62e17 Provide correct encodings for NEON vmlal. 
llvm-svn: 117131
 2010-10-22 19:05:25 +00:00
Owen Anderson
ada2b33321 Provide correct NEON encodings for vmla. 
llvm-svn: 117126
 2010-10-22 18:54:37 +00:00
Jim Grosbach
ca2897a0ca More ARM multiply instuction binary encodings. 
llvm-svn: 117121
 2010-10-22 18:35:16 +00:00
Owen Anderson
399ec622e4 Add testscases for encoding of NEON vdqmull. 
llvm-svn: 117115
 2010-10-22 17:57:37 +00:00
Jim Grosbach
0ae6bf8095 More ARM multiply instruction encoding information. 
llvm-svn: 117108
 2010-10-22 17:16:17 +00:00
Owen Anderson
bba3b2050e Add tests for NEON encoding of vmull. 
llvm-svn: 117077
 2010-10-21 22:19:53 +00:00
Jim Grosbach
7c42142b71 ARM binary encodings for MVN variants. 
llvm-svn: 117076
 2010-10-21 22:19:32 +00:00
Owen Anderson
653fc9304a Add tests for NEON encoding of vqdmulh and vqrdmulh. 
llvm-svn: 117074
 2010-10-21 22:05:33 +00:00
Jim Grosbach
cb41e97b5c ARM Binary encoding information for BFC/BFI instructions. 
llvm-svn: 117072
 2010-10-21 22:03:21 +00:00
Owen Anderson
2c25ce7af1 Add tests for NEON vmul encoding. 
llvm-svn: 117069
 2010-10-21 21:51:58 +00:00
Owen Anderson
b0bddd3282 Rename this test to better reflect its contents. 
llvm-svn: 117067
 2010-10-21 21:40:15 +00:00
Owen Anderson
77c5078d4a Add tests for NEON encodings of vaddhn and vraddhn. 
llvm-svn: 117064
 2010-10-21 20:56:57 +00:00
Owen Anderson
ba6ee305cf Add tests for NEON encodings of vqadd, which was already correctly encoded. 
llvm-svn: 117059
 2010-10-21 20:42:04 +00:00
Owen Anderson
51a6bc3b27 Add correct NEON encodings for vhadd and vrhadd. 
llvm-svn: 117047
 2010-10-21 18:55:04 +00:00
Owen Anderson
dce283c7db Add correct encodings for NEON vaddw.s* and vaddw.u*. 
llvm-svn: 117040
 2010-10-21 18:20:25 +00:00
Owen Anderson
7d90c72edf Provide correct NEON encodings for vaddl.u* and vaddl.s*. 
llvm-svn: 117039
 2010-10-21 18:09:17 +00:00
Bill Wendling
8b2c8a5856 Fix whitespace. 
llvm-svn: 117002
 2010-10-21 06:25:08 +00:00
Andrew Trick
4a3b819c1f putback r116983 and fix simple-fp-encoding.ll tests 
llvm-svn: 116992
 2010-10-21 03:40:16 +00:00
Owen Anderson
a685f8e90a Implement correct encodings for NEON vadd, both integer and floating point. 
llvm-svn: 116981
 2010-10-21 00:48:00 +00:00
Bill Wendling
c7ef66fcf2 Add encoding for moving a value between two ARM core registers and a doublework 
extension register.

llvm-svn: 116970
 2010-10-20 23:37:40 +00:00
Bill Wendling
0f96ff63b3 Add encodings for movement between ARM core registers and single-precision 
registers.

llvm-svn: 116961
 2010-10-20 22:44:54 +00:00
Jim Grosbach
67f94c42d8 ARM mode encoding information for UBFX and SBFX instructions. 
llvm-svn: 116588
 2010-10-15 17:15:16 +00:00
Jim Grosbach
608e4fd221 Simplify test file a bit. 
llvm-svn: 116540
 2010-10-14 23:32:44 +00:00
Jim Grosbach
26842cb893 Add testcase for RRX and ASRS (which effectively tests MOVs, since those 
are just forms of that instruction).

llvm-svn: 116538
 2010-10-14 23:29:18 +00:00
Jim Grosbach
73c78f8790 MOVi16 and MOVT ARM mode encodings. 
llvm-svn: 116498
 2010-10-14 18:54:27 +00:00
Bill Wendling
2c335d364c Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on 
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.

llvm-svn: 116471
 2010-10-14 02:33:26 +00:00
Bill Wendling
33a2ecd5e4 Add encoding for 'fmstat'. 
llvm-svn: 116466
 2010-10-14 01:19:34 +00:00
Bill Wendling
cd41f22ec1 - Add encodings for multiply add/subtract instructions in all their glory. 
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.

llvm-svn: 116464
 2010-10-14 01:02:08 +00:00
Bill Wendling
bf63d6eb63 Add MC encodings for VCVT* instrunctions. 
llvm-svn: 116431
 2010-10-13 20:58:46 +00:00
Jim Grosbach
8f0bea85bf Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. 
llvm-svn: 116421
 2010-10-13 19:56:10 +00:00
Jim Grosbach
9c4a598ef2 Add ARM mode operand encoding information for ADDE/SUBE instructions. 
llvm-svn: 116412
 2010-10-13 18:00:52 +00:00
Bill Wendling
6d8a23c978 Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test 
just yet.

llvm-svn: 116386
 2010-10-13 01:17:33 +00:00
Bill Wendling
ea062d454d Add encodings for VCVT instructions. 
llvm-svn: 116385
 2010-10-13 00:56:35 +00:00
Jim Grosbach
3fe0337063 Add ARM encoding information for comparisons, forced-cc-out arithmetics, and 
arithmetic-with-carry-in instructions.

llvm-svn: 116384
 2010-10-13 00:50:27 +00:00
Bill Wendling
e6c2fdebbd Add VCMPZ and VABS. 
llvm-svn: 116383
 2010-10-13 00:38:07 +00:00
Bill Wendling
fddde4cc72 Refactor VCMP instructions. 
llvm-svn: 116379
 2010-10-13 00:04:29 +00:00
Bill Wendling
47155cfddd Add encodings for VNMUL[SD]. 
llvm-svn: 116375
 2010-10-12 23:47:37 +00:00
Bill Wendling
185b548b07 Add encodings for VDIV and VMUL. 
llvm-svn: 116370
 2010-10-12 23:22:27 +00:00
Jim Grosbach
0038f2eec6 Be nitpicky and line up the comments. 
llvm-svn: 116365
 2010-10-12 23:14:03 +00:00
Bill Wendling
cd3cb8da45 Add encoding for VSUB and VCMP. 
Fear not! I'm going to try a refactoring right now. :)

llvm-svn: 116359
 2010-10-12 22:55:35 +00:00
Bill Wendling
fad2800dbd Don't need to specify calling convention. Add 'readnone' to functions. 
llvm-svn: 116354
 2010-10-12 22:24:10 +00:00
Bill Wendling
33a26354c1 Encoding for VADDD. Plus a test for the VFP instructions. 
llvm-svn: 116348
 2010-10-12 22:08:41 +00:00
Jim Grosbach
10d9bbe0ca Add encoding information for the remainder of the generic arithmetic 
ARM instructions.

llvm-svn: 116313
 2010-10-12 17:11:26 +00:00
Jim Grosbach
29ef87e765 MC machine encoding for simple aritmetic instructions that use a shifted 
register operand.

llvm-svn: 116259
 2010-10-11 23:16:21 +00:00
Jim Grosbach
3075d28c15 Implement a few more binary encoding bits. Still very early stage proof-of- 
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.

This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.

llvm-svn: 116112
 2010-10-08 21:45:55 +00:00
Jim Grosbach
edbbf33203 Add test file for simple ARM binary encodings with MC 
llvm-svn: 116024
 2010-10-08 00:47:59 +00:00
Chris Lattner
3528fce592 move ARM MC tests up one level. 
llvm-svn: 115414
 2010-10-02 18:52:05 +00:00