1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 11:42:57 +01:00
Commit Graph

70503 Commits

Author SHA1 Message Date
Benjamin Kramer
d4ea449e7e ComputeMaskedBits: sub falls through to add, and sub doesn't have the same overflow semantics as add.
Should fix the selfhost failures that started with r127463.

llvm-svn: 127465
2011-03-11 14:46:49 +00:00
Benjamin Kramer
666407939f InstCombine: Fix a thinko where transform an icmp under the assumption that it's a zero comparison when it's not.
Fixes PR9454.

llvm-svn: 127464
2011-03-11 11:37:40 +00:00
Nick Lewycky
cf0e3e88df Teach ComputeMaskedBits about nsw on add. I don't think there's anything we can
do with nuw here, but sub and mul should be given similar treatment.
Fixes PR9343 #15!

llvm-svn: 127463
2011-03-11 09:00:19 +00:00
John Wiegley
e1168a569b Fix use of CompEnd predicate to be standards conforming
The existing CompEnd predicate does not define a strict weak order as required
by the C++03 standard; therefore, its use as a predicate to std::upper_bound
is invalid. For a discussion of this issue, see
http://www.open-std.org/jtc1/sc22/wg21/docs/lwg-defects.html#270

This patch replaces the asymmetrical comparison with an iterator adaptor that
achieves the same effect while being strictly standard-conforming by ensuring
an apples-to-apples comparison.

llvm-svn: 127462
2011-03-11 08:54:34 +00:00
Cameron Zwarich
9ed726c151 Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127459
2011-03-11 04:54:27 +00:00
Jim Grosbach
c7548fce48 Teach TableGen to pre-calculate register enum values when creating the
CodeGenRegister entries. Use this information to more intelligently build
the literal register entires in the DAGISel matcher table. Specifically,
use a single-byte OPC_EmitRegister entry for registers with a value of
less than 256 and OPC_EmitRegister2 entry for registers with a larger value.

rdar://9066491

llvm-svn: 127456
2011-03-11 02:19:02 +00:00
Chris Lattner
2cd24b852f silence a conditional assignment -Wuninitialized warning.
llvm-svn: 127453
2011-03-11 02:12:51 +00:00
Jim Grosbach
6e41ec016b Make the register enum value part of the CodeGenRegister struct.
llvm-svn: 127448
2011-03-11 01:33:54 +00:00
Jim Grosbach
2c9ce71360 Trailing whitespace.
llvm-svn: 127447
2011-03-11 01:27:24 +00:00
Jim Grosbach
9834ed0ef4 Trailing whitespace.
llvm-svn: 127446
2011-03-11 01:19:05 +00:00
Jim Grosbach
9cddc3746d Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos.
llvm-svn: 127445
2011-03-11 01:16:49 +00:00
Jim Grosbach
ed45ac390c Properly pseudo-ize ARM MOVCCi and MOVCCi16.
llvm-svn: 127442
2011-03-11 01:09:28 +00:00
Eric Christopher
46f43c9cce Change the x86 32-bit scheduler to register pressure and fix up the
corresponding testcases back to the previous versions.

Fixes some performance regressions only seen on 32-bit.

llvm-svn: 127441
2011-03-11 01:05:58 +00:00
Evan Cheng
d5d2d4a158 Avoid replacing the value of a directly stored load with the stored value if the load is indexed. rdar://9117613.
llvm-svn: 127440
2011-03-11 00:48:56 +00:00
Jim Grosbach
1986d9ac8f Properly pseudo-ize MOVCCr and MOVCCs.
llvm-svn: 127434
2011-03-10 23:56:09 +00:00
Dan Gohman
051cc738c3 RecursivelyDeleteTriviallyDeadInstructions only needs a
Value, not an Instruction, so casting is not necessary. Also,
it's theoretically possible that the Value is not an
Instruction, since WeakVH follows RAUWs.

llvm-svn: 127427
2011-03-10 20:57:44 +00:00
Rafael Espindola
222ccb2bdd Don't compute the file size if we don't need to.
llvm-svn: 127426
2011-03-10 20:54:07 +00:00
Dan Gohman
bb9c77f5bd Fix reassociate to postpone certain instruction deletions until
after it has finished all of its reassociations, because its
habit of unlinking operands and holding them in a datastructure
while working means that it's not easy to determine when an
instruction is really dead until after all its regular work is
done. rdar://9096268.

llvm-svn: 127424
2011-03-10 19:51:54 +00:00
Jim Grosbach
5891b1323a DMB can just be a pat referencing MCR.
llvm-svn: 127423
2011-03-10 19:27:17 +00:00
Jim Grosbach
4b74ef6ca9 Reorganize a bit. No functional change, just moving patterns up.
llvm-svn: 127422
2011-03-10 19:21:08 +00:00
Jim Grosbach
db549a7f6c Pseudo-instructions are codegenonly by definition.
llvm-svn: 127420
2011-03-10 19:06:39 +00:00
Jim Grosbach
41694b91ad Memory barrier instructions don't need special handling in tblgen anymore.
llvm-svn: 127419
2011-03-10 19:05:48 +00:00
Benjamin Kramer
52a44b9c80 InstCombine: Turn umul_with_overflow into mul nuw if we can prove that it cannot overflow.
This happens a lot in clang-compiled C++ code because it adds overflow checks to operator new[]:
  unsigned *foo(unsigned n) { return new unsigned[n]; }
We can optimize away the overflow check on 64 bit targets because (uint64_t)n*4 cannot overflow.

llvm-svn: 127418
2011-03-10 18:40:14 +00:00
Rafael Espindola
a271db1a12 Add r127409 back now that the windows file was updated.
llvm-svn: 127417
2011-03-10 18:33:29 +00:00
Rafael Espindola
11ae298b4f Try to fix the windows build.
llvm-svn: 127416
2011-03-10 18:30:48 +00:00
Jakob Stoklund Olesen
891bfab351 Revert r127409 which broke all the Windows bots.
llvm-svn: 127413
2011-03-10 18:01:43 +00:00
Justin Holewinski
a26d2f782e PTX: Add preliminary support for floating-point divide and multiply-and-add
llvm-svn: 127410
2011-03-10 16:57:18 +00:00
Rafael Espindola
b7a2d86ef5 Add support for MemoryBuffers that are not null terminated and add
support for creating buffers that cover only a part of a file.

llvm-svn: 127409
2011-03-10 16:10:30 +00:00
Chris Lattner
bf47cbabd9 rip out llvm 2.8 release notes to make room for llvm 2.9 notes.
llvm-svn: 127399
2011-03-10 07:43:44 +00:00
Cameron Zwarich
206503113e Add an option to disable critical edge splitting in PHIElimination.
llvm-svn: 127398
2011-03-10 05:59:17 +00:00
Che-Liang Chiou
fc6c7ba9d5 ptx: add the rest of special registers of ISA version 2.0
llvm-svn: 127397
2011-03-10 04:05:57 +00:00
Jakob Stoklund Olesen
92652a803f Change the Spiller interface to take a LiveRangeEdit reference.
This makes it possible to register delegates and get callbacks when the spiller
edits live ranges.

llvm-svn: 127389
2011-03-10 01:51:42 +00:00
Jakob Stoklund Olesen
70541686bf Make SpillIs an optional pointer. Avoid creating a bunch of temporary SmallVectors.
llvm-svn: 127388
2011-03-10 01:21:58 +00:00
Francois Pichet
348d41b59b Unbreak the CMake build.
llvm-svn: 127383
2011-03-10 00:51:01 +00:00
Stuart Hastings
fd42046d56 Revert 127359; it broke lencod.
llvm-svn: 127382
2011-03-10 00:25:53 +00:00
Devang Patel
73d68195ce Introduce DebugInfoProbe. This is used to monitor how llvm optimizer is treating debugging information.
It generates output that lools like

8 times line number info lost by Scalar Replacement of Aggregates (SSAUp) 
1 times line number info lost by Simplify well-known library calls 
12 times variable info lost by Jump Threading

llvm-svn: 127381
2011-03-10 00:21:25 +00:00
Evan Cheng
a3a7a7e364 Re-commit 127368 and 127371. They are exonerated.
llvm-svn: 127380
2011-03-10 00:16:32 +00:00
Evan Cheng
d7a2008a55 Revert 127368 and 127371 for now.
llvm-svn: 127376
2011-03-09 23:53:17 +00:00
Evan Cheng
c4a9f8a319 Restore the default implementation of getCrossCopyRegClass: no need for cross-regclass copies.
llvm-svn: 127371
2011-03-09 23:15:40 +00:00
Daniel Dunbar
11a8b6c4ff Revert "Re-enable test and hope to silence the buildbots", still broken.
llvm-svn: 127369
2011-03-09 22:48:46 +00:00
Evan Cheng
b717770dfe Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be more
flexible.

If it returns a register class that's different from the input, then that's the
register class used for cross-register class copies.
If it returns a register class that's the same as the input, then no cross-
register class copies are needed (normal copies would do).
If it returns null, then it's not at all possible to copy registers of the
specified register class.

llvm-svn: 127368
2011-03-09 22:47:38 +00:00
Benjamin Kramer
8313cf1cf4 Fix mistyped CHECK lines.
llvm-svn: 127366
2011-03-09 22:07:31 +00:00
Benjamin Kramer
f1c1220d8f Fix a pasto that broke all x86_64-elf targets.
llvm-svn: 127365
2011-03-09 22:07:13 +00:00
Stuart Hastings
6c99b422b1 Tweak test to work on Linux.
llvm-svn: 127364
2011-03-09 21:35:10 +00:00
Stuart Hastings
5c555821bb Disable this test temporarily to reduce BuildBot complaints.
llvm-svn: 127363
2011-03-09 21:33:47 +00:00
Devang Patel
7a4edc6463 Preserve line number information while simplifying libcalls.
llvm-svn: 127362
2011-03-09 21:27:52 +00:00
Stuart Hastings
61f9a3dab2 X86 byval copies no longer always_inline. <rdar://problem/8706628>
llvm-svn: 127359
2011-03-09 21:10:30 +00:00
Bruno Cardoso Lopes
f34376b0e1 Add a testcase for the addc improvements introduced some commits ago. Patch by Akira Hatanaka
llvm-svn: 127358
2011-03-09 21:05:32 +00:00
Bruno Cardoso Lopes
51df3638f8 Re-enable test and hope to silence the buildbots
llvm-svn: 127357
2011-03-09 21:00:16 +00:00
Bruno Cardoso Lopes
64f0169989 try to make o32 cc tests less specific to silence some buildbots. The test isn't enabled yet, this is will be done in a subsequent commit. Patch by Akira Hatanaka.
llvm-svn: 127356
2011-03-09 20:59:05 +00:00