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181225 Commits

Author SHA1 Message Date
Simon Pilgrim
d6fe99fc94 [X86] getTargetConstantBitsFromNode - remove unnecessary getZExtValue() (PR42486)
Don't use APInt::getZExtValue() if you can avoid it - eventually someone will call it with i128 or something that doesn't fit into 64-bits.

In this case it was completely superfluous as we'd moved the rest of the code to always use APInt.

Fixes the <1 x i128> addition bug in PR42486

llvm-svn: 364953
2019-07-02 18:20:38 +00:00
Alexander Timofeev
29ea39e798 [AMDGPU] LCSSA pass added in preISel. Fixing typo in previous commit
llvm-svn: 364952
2019-07-02 18:16:42 +00:00
Alexander Timofeev
cca373d192 [AMDGPU] LCSSA pass added in preISel. Uniform values defined in the divergent loop and used outside
Differential Revision: https://reviews.llvm.org/D63953

Reviewers: rampitec, nhaehnle, arsenm
llvm-svn: 364950
2019-07-02 17:59:44 +00:00
Craig Topper
42300c67a0 [X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
Similar for (V)MOVSD. Ultimately, I'd like to see about folding
scalar_to_vector+load to vzload. Which would select as (V)MOVSSrm
so this is closer to that.

llvm-svn: 364948
2019-07-02 17:51:02 +00:00
Roman Lebedev
ceff4201f1 [NFC][Codegen][X86][AArch64][ARM][PowerPC] Recommit: Add test coverage for "add-of-inc" vs "sub-of-not"
I initially committed it with --check-prefix instead of --check-prefixes
(again, shame on me, and utils/update_*.py not complaining!)
and did not have a moment to understand the failure,
so i reverted it initially in rL64939.

llvm-svn: 364945
2019-07-02 16:48:49 +00:00
Vitaly Buka
435ba65fb9 Fix GN build
llvm-svn: 364942
2019-07-02 16:08:10 +00:00
David Bolvansky
5f972de5c3 [SimplifyLibCalls] powf(x, sitofp(n)) -> powi(x, n)
Summary:
Partially solves https://bugs.llvm.org/show_bug.cgi?id=42190



Reviewers: spatel, nikic, efriedma

Reviewed By: efriedma

Subscribers: efriedma, nikic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63038

llvm-svn: 364940
2019-07-02 15:58:45 +00:00
Roman Lebedev
dc00c29c8d Revert "[NFC][Codegen][X86][AArch64][ARM][PowerPC] Add test coverage for "add-of-inc" vs "sub-of-not""
Some test failures i don't have a moment to investigate.

This reverts commit r364930.

llvm-svn: 364939
2019-07-02 15:54:24 +00:00
Serge Guelton
002a175085 Provide basic Full LTO extension points
Differential Revision: https://reviews.llvm.org/D61738

llvm-svn: 364937
2019-07-02 15:52:39 +00:00
Sam McCall
82429ff8e0 getMainExecutable: handle realpath() failure, falling back to getprogpath().
Summary:
Previously, we'd pass a nullptr to std::string and crash().

This case happens when the binary is deleted while being used (e.g. rebuilding clangd).

Reviewers: kadircet

Subscribers: ilya-biryukov, kristina, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64068

llvm-svn: 364936
2019-07-02 15:42:37 +00:00
Matt Arsenault
5de7688059 AMDGPU: Fix broken test
llvm-svn: 364935
2019-07-02 15:34:40 +00:00
Matt Arsenault
53a677c028 AMDGPU/GlobalISel: Try generated matcher with intrinsics
llvm-svn: 364933
2019-07-02 14:52:16 +00:00
Matt Arsenault
b559c964e7 AMDGPU/GlobalISel: Select mul
llvm-svn: 364932
2019-07-02 14:52:14 +00:00
Matt Arsenault
cdf2a5a6c1 GlobalISel: Define GINodeEquiv for G_UMULH/G_SMULH
llvm-svn: 364931
2019-07-02 14:49:29 +00:00
Roman Lebedev
f4e76ebe9e [NFC][Codegen][X86][AArch64][ARM][PowerPC] Add test coverage for "add-of-inc" vs "sub-of-not"
As it is pointed out in https://reviews.llvm.org/D63992,
before we get to pick canonical variant in middle-end
we should ensure best codegen in backend.

llvm-svn: 364930
2019-07-02 14:48:52 +00:00
Paul Robinson
6421f43f1b Use --defsym instead of sed in a test. NFC
llvm-svn: 364929
2019-07-02 14:47:49 +00:00
Matt Arsenault
25f8690d8f AMDGPU/GlobalISel: Fix G_GEP with mixed SGPR/VGPR operands
The register bank for the destination of the sample argument copy was
wrong. We shouldn't be constraining each source to the result register
bank. Allow constraining the original register to the right size.

llvm-svn: 364928
2019-07-02 14:40:22 +00:00
Matt Arsenault
9db0cb6291 AMDGPU/GlobalISel: Select G_FENCE
Manually select to workaround tablegen emitter emitting checks for
G_CONSTANT.

llvm-svn: 364927
2019-07-02 14:17:38 +00:00
Matt Arsenault
2e9237bd7c GlobalISel: Add G_FENCE
The pattern importer is for some reason emitting checks for G_CONSTANT
for the immediate operands.

llvm-svn: 364926
2019-07-02 14:16:39 +00:00
Simon Pilgrim
95d83c904b [X86][AVX] combineX86ShuffleChain - pull out CombineShuffleWithExtract lambda. NFCI.
Pull out CombineShuffleWithExtract lambda to new combineX86ShuffleChainWithExtract wrapper and refactored it to handle more than 2 shuffle inputs - this will allow combineX86ShufflesRecursively to call this in a future patch.

llvm-svn: 364924
2019-07-02 13:30:04 +00:00
Kristof Umann
09c73382e2 Removed extra ; after function definition
llvm-svn: 364923
2019-07-02 13:25:41 +00:00
Roman Lebedev
cb2c544395 [NFC][TargetLowering] Some preparatory cleanups around 'prepareUREMEqFold()' from D63963
llvm-svn: 364921
2019-07-02 13:21:23 +00:00
Roman Lebedev
cb256ed9f4 [APIntTest] multiplicativeInverse(): clarify test
Clarify that multiplicative inverse exists for all odd numbers,
and does not exist for all even numbers (including 0).

llvm-svn: 364920
2019-07-02 13:21:17 +00:00
Paul Robinson
bdcbceeb8b Fix line endings (NFC)
llvm-svn: 364919
2019-07-02 13:13:36 +00:00
James Henderson
2a01506a1e [docs][llvm-readelf] Delete old llvm-readelf.md
This was accidentally missed when committing r364800.

llvm-svn: 364918
2019-07-02 13:11:34 +00:00
George Rimar
fab1cebcb8 [Object/invalid.test] - Convert Object/corrupt.test to YAML and merge the result into invalid.test
Object/corrupt.test has the same purpose as Object/invalid.test:
it tests the behavior on invalid inputs.

In this patch I converted it to YAML, merged into invalid.test, 
added comments and removed a few precompiled binaries.

Differential revision: https://reviews.llvm.org/D63927

llvm-svn: 364916
2019-07-02 12:58:37 +00:00
Roman Lebedev
41f678a3ed [InstCombine] Shift amount reassociation: fixup constantexpr handling (PR42484)
I was actually wondering if there was some nicer way than m_Value()+cast,
but apparently what i was really "subconsciously" thinking about
was correctness issue.

hasNoUnsignedWrap()/hasNoUnsignedWrap() exist for Instruction,
not for BinaryOperator, so let's just use m_Instruction(),
thus both avoiding a cast, and a crash.

Fixes https://bugs.llvm.org/show_bug.cgi?id=42484,
      https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=15587

llvm-svn: 364915
2019-07-02 12:54:48 +00:00
Kristof Umann
7a17e57dc3 Attempt to fix buildbot failures with MSVC
llvm-svn: 364914
2019-07-02 12:40:29 +00:00
Michal Gorny
981e8e9d50 [llvm] [Support] Clean PrintStackTrace() ptr arithmetic up
Use '%tu' modifier for pointer arithmetic since we are using C++11
already.  Prefer static_cast<> over C-style cast.  Remove unnecessary
conversion of result, and add const qualifier to converted pointers,
to silence the following warning:

  In file included from /home/mgorny/llvm-project/llvm/lib/Support/Signals.cpp:220:0:
  /home/mgorny/llvm-project/llvm/lib/Support/Unix/Signals.inc: In function ‘void llvm::sys::PrintStackTrace(llvm::raw_ostream&)’:
  /home/mgorny/llvm-project/llvm/lib/Support/Unix/Signals.inc:546:53: warning: cast from type ‘const void*’ to type ‘char*’ casts away qualifiers [-Wcast-qual]
                                         (char*)dlinfo.dli_saddr));
                                                       ^~~~~~~~~

Differential Revision: https://reviews.llvm.org/D63888

llvm-svn: 364912
2019-07-02 11:32:03 +00:00
Kristof Umann
7262615ba5 [IDF] Generalize IDFCalculator to be used with Clang's CFG
I'm currently working on a GSoC project that aims to improve the the bug reports
of the analyzer. The main heuristic I plan to use is to explain values that are
a control dependency of the bug location better.

01 bool b = messyComputation();
02 int i = 0;
03 if (b) // control dependency of the bug site, let's explain why we assume val
04        // to be true
05   10 / i; // warn: division by zero

Because of this, I'd like to generalize IDFCalculator so that I could use it for
Clang's CFG: D62883.

In detail:

* Rename IDFCalculator to IDFCalculatorBase, make it take a general CFG node
  type as a template argument rather then strictly BasicBlock (but preserve
  ForwardIDFCalculator and ReverseIDFCalculator)
* Move IDFCalculatorBase from llvm/include/llvm/Analysis to
  llvm/include/llvm/Support (but leave the BasicBlock variants in
  llvm/include/llvm/Analysis)
* clang-format the file since this patch messes up git blame anyways
* Change typedef to using
* Add the new type ChildrenGetterTy, and store an instance of it in
  IDFCalculatorBase. This is important because I'll have to specialize it for
  Clang's CFG to filter out nullpointer successors, similarly to D62507.

Differential Revision: https://reviews.llvm.org/D63389

llvm-svn: 364911
2019-07-02 11:30:12 +00:00
Simon Tatham
b7791e7f2e [ARM] MVE: allow soft-float ABI to pass vector types.
Passing a vector type over the soft-float ABI involves it being split
into four GPRs, so the first thing that has to happen at the start of
the function is to recombine those into a vector register. The ABI
types all vectors as v2f64, so we need to support BUILD_VECTOR for
that type, which I do in this patch by allowing it to be expanded in
terms of INSERT_VECTOR_ELT, and writing an ISel pattern for that in
turn. Similarly, I provide a rule for EXTRACT_VECTOR_ELT so that a
returned vector can be marshalled back into GPRs.

While I'm here, I've also added ISD::UNDEF to the list of operations
we turn back on in `setAllExpand`, because I noticed that otherwise it
gets expanded into a BUILD_VECTOR with explicit zero inputs, leading
to pointless machine instructions to zero out a vector register that's
about to have every lane overwritten of in any case.

Reviewers: dmgreen, ostannard

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63937

llvm-svn: 364910
2019-07-02 11:26:11 +00:00
Simon Tatham
4152cccce8 [ARM] Stop using scalar FP instructions in integer-only MVE mode.
If you compile with `-mattr=+mve` (enabling integer MVE instructions
but not floating-point ones), then the scalar FP //registers// exist
and it's legal to move things in and out of them, load and store them,
but it's not legal to do arithmetic on them.

In D60708, the calls to `addRegisterClass` in ARMISelLowering that
enable use of the scalar FP registers became conditionalised on
`Subtarget->hasFPRegs()` instead of `Subtarget->hasVFP2Base()`, so
that loads, stores and moves of those registers would work. But I
didn't realise that that would also enable all the operations on those
types by default.

Now, if the target doesn't have basic VFP, we follow up those
`addRegisterClass` calls by turning back off all the nontrivial
operations you can perform on f32 and f64. That causes several
knock-on failures, which are fixed by allowing the `VMOVDcc` and
`VMOVScc` instructions to be selected even if all you have is
`HasFPRegs`, and adjusting several checks for 'is this a double in a
single-precision-only world?' to the more general 'is this any FP type
we can't do arithmetic on?'. Between those, the whole of the
`float-ops.ll` and `fp16-instructions.ll` tests can now run in
MVE-without-FP mode and generate correct-looking code.

One odd side effect is that I had to relax the check lines in that
test so that they permit test functions like `add_f` to be generated
as tailcalls to software FP library functions, instead of ordinary
calls. Doing that is entirely legal, but the mystery is why this is
the first RUN line that's needed the relaxation: on the usual kind of
non-FP target, no tailcalls ever seem to be generated. Going by the
llc messages, I think `SoftenFloatResult` must be perturbing the code
generation in some way, but that's as much as I can guess.

Reviewers: dmgreen, ostannard

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63938

llvm-svn: 364909
2019-07-02 11:26:00 +00:00
Nico Weber
09c8d9930c gn build: Merge r364866
llvm-svn: 364908
2019-07-02 11:20:40 +00:00
George Rimar
4c75da8dbd [yaml2obj] - An attempt to fix a ppc64be build bot after r364898
I guess the problem is because of endianess of
the bytes tested by "od" tool. I changed the Content
sequence as it does not actually matter.

llvm-svn: 364907
2019-07-02 11:02:09 +00:00
Simon Pilgrim
516651e650 [X86] resolveTargetShuffleInputsAndMask - add repeated input handling.
We were relying on combineX86ShufflesRecursively to handle this - this patch gets it done earlier which should make it easier for other code to use resolveTargetShuffleInputsAndMask.

llvm-svn: 364906
2019-07-02 10:53:17 +00:00
George Rimar
1f23beae08 [test/Object] - Fix build bot.
Fixed mistype in the test case.

BB: http://lab.llvm.org:8011/builders/lld-x86_64-ubuntu-fast/builds/2720/steps/test-check-all/logs/stdio
llvm-svn: 364905
2019-07-02 10:47:13 +00:00
George Rimar
74eddae7ef [Object/invalid.test] - Convert 3 more sub-tests to YAML
This allows to remove 3 more precompiled binaries from the inputs.

Differential revision: https://reviews.llvm.org/D63880

llvm-svn: 364903
2019-07-02 10:30:06 +00:00
Simon Atanasyan
5b20d62655 [mips] Mark P5600 scheduling model as complete
llvm-svn: 364902
2019-07-02 10:22:14 +00:00
Simon Atanasyan
338b75c7c0 [mips] Add missing schedinfo for FPU load/store/conv instructions
llvm-svn: 364900
2019-07-02 10:22:06 +00:00
Simon Atanasyan
713cc1b1e4 [mips] Map SNOP, NOP to the P5600Nop scheduler resource
llvm-svn: 364899
2019-07-02 10:21:59 +00:00
George Rimar
36adbe81da [yaml2obj] - Allow overriding sh_offset field from the YAML.
Some of our test cases are using objects which
has sections with a broken sh_offset field.

There was no way to set it from YAML until this patch.

Differential revision: https://reviews.llvm.org/D63879

llvm-svn: 364898
2019-07-02 10:20:12 +00:00
Roman Lebedev
6441358c7c [NFC][InstCombine] Revisit tests for "redundant shift input masking" (PR42456)
llvm-svn: 364897
2019-07-02 10:02:25 +00:00
Igor Kudrin
a8593263e5 [DWARF] Simplify dumping of a .debug_addr section.
This patch removes the part which tried to interpret addresses
in that section as offsets and simplifies the remaining code.

Differential Revision: https://reviews.llvm.org/D64020

llvm-svn: 364896
2019-07-02 09:57:28 +00:00
Roman Lebedev
ffd0b141f9 [NFC][InstCombine] Add tests for "redundant shift input masking" (PR42456)
https://bugs.llvm.org/show_bug.cgi?id=42456
https://rise4fun.com/Alive/Vf1p

llvm-svn: 364894
2019-07-02 09:27:34 +00:00
Amara Emerson
207f6805ea [TailDuplicator] Fix copy instruction emitting into the wrong block.
The code for duplicating instructions could sometimes try to emit copies
intended to deal with unconstrainable register classes to the tail block of the
original instruction, rather than before the newly cloned instruction in the
predecessor block.

This was exposed by GlobalISel on arm64.

Differential Revision: https://reviews.llvm.org/D64049

llvm-svn: 364888
2019-07-02 06:04:46 +00:00
Craig Topper
1c92b44903 [X86] Add PreprocessISelDAG support for turning ISD::FP_TO_SINT/UINT into X86ISD::CVTTP2SI/CVTTP2UI and to reduce the number of isel patterns.
llvm-svn: 364887
2019-07-02 05:53:37 +00:00
QingShan Zhang
da451ad14d [PowerPC] Implement the areMemAccessesTriviallyDisjoint hook
After implemented this hook, we will model the memory dependency in the scheduling dependency graph more precise,
and will have more opportunity to reorder the load/stores, as they didn't have the dependency at some condition

Differential Revision: https://reviews.llvm.org/D63804

llvm-svn: 364886
2019-07-02 03:28:52 +00:00
Zi Xuan Wu
88b4c7ca50 [DAGCombiner] Exploiting more about the transformation of TransformFPLoadStorePair function
For a given floating point load / store pair, if the load value isn't used by any other operations, 
then consider transforming the pair to integer load / store operations if the target deems the transformation profitable.

And we can exploiting much more when there are other operation nodes with chain operand between the load/store pair 
so long as we keep the chain ordering original. We only replace the register used to load/store from float to integer.

I only add testcase in ARM because the TLI.isDesirableToTransformToIntegerOp hook is only enabled in ARM target.

Differential Revision: https://reviews.llvm.org/D60601

llvm-svn: 364883
2019-07-02 02:54:52 +00:00
Jordan Rupprecht
7a712701a0 Revert Recommit [PowerPC] Update P9 vector costs for insert/extract element
This reverts r364557 (git commit 9f7f5858fe46b8e706e87a83e2fd0a2678be619e)

This crashes as reported on the commit thread. Repro instructions TBD.

llvm-svn: 364876
2019-07-01 23:29:46 +00:00
Keno Fischer
3ac3a2c421 [cmake] With utils disabled, don't build tblgen in cross mode
Summary:
In cross mode, we build a separate NATIVE tblgen that runs on the
host and is used during the build. Separately, we have a flag that
disables building all executables in utils/. Of course generally,
this doesn't turn off tblgen, since we need that during the build.
In cross mode, however, that tblegen is useless since we never
actually use it. Furthermore, it can be actively problematic if the
cross toolchain doesn't like building executables for whatever reason.
And even if building executables works fine, we can at least save
compile time by omitting it from the target build. There's two changes
needed to make this happen:
- Stop creating a dependency from the native tool to the target tool.
  No such dependency is required for a correct build, so I'm not entirely
  sure why it was there in the first place.
- If utils were disabled on the CMake command line and we're in cross mode,
  respect that by excluding it from the install target (using EXCLUDE_FROM_ALL).

Reviewers: smeenai
Differential Revision: https://reviews.llvm.org/D64032

llvm-svn: 364872
2019-07-01 23:15:07 +00:00