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Author SHA1 Message Date
Chris Lattner
8cdbb1fe84 Improve code for passing constant longs as arguments to function calls. 
For example, on this instruction:

        call void %test(long 1234)

Instead of this:
        mov %EAX, 1234
        mov %ECX, 0
        mov DWORD PTR [%ESP], %EAX
        mov DWORD PTR [%ESP + 4], %ECX
        call test

We now emit this:
        mov DWORD PTR [%ESP], 1234
        mov DWORD PTR [%ESP + 4], 0
        call test

llvm-svn: 12686
 2004-04-06 03:23:00 +00:00
Chris Lattner
2738d6d4a4 Emit more efficient 64-bit operations when the RHS is a constant, and one 
of the words of the constant is zeros.  For example:
  Y = and long X, 1234

now generates:
  Yl = and Xl, 1234
  Yh = 0

instead of:
  Yl = and Xl, 1234
  Yh = and Xh, 0

llvm-svn: 12685
 2004-04-06 03:15:53 +00:00
Chris Lattner
bdbedf9523 Fix typeo 
llvm-svn: 12684
 2004-04-06 02:13:25 +00:00
Chris Lattner
606639ed1a Add support for simple immediate handling to long instruction selection. 
This allows us to handle code like 'add long %X, 123456789012' more efficiently.

llvm-svn: 12683
 2004-04-06 02:11:49 +00:00
Chris Lattner
e84f12a165 The sbb instructions really ARE sbb's, not adc's 
llvm-svn: 12682
 2004-04-06 02:02:11 +00:00
Chris Lattner
0808f5daa5 Implement negation of longs efficiently. For this testcase: 
long %test(long %X) {
        %Y = sub long 0, %X
        ret long %Y
}

We used to generate:

test:
        sub %ESP, 4
        mov DWORD PTR [%ESP], %ESI
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %ESI, DWORD PTR [%ESP + 12]
        mov %EAX, 0
        mov %EDX, 0
        sub %EAX, %ECX
        sbb %EDX, %ESI
        mov %ESI, DWORD PTR [%ESP]
        add %ESP, 4
        ret

Now we generate:

test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        neg %EAX
        adc %EDX, 0
        neg %EDX
        ret

llvm-svn: 12681
 2004-04-06 01:48:06 +00:00
Chris Lattner
56dcdcf638 Minor tweak to avoid an extra reg-reg copy that the register allocator has to eliminate 
llvm-svn: 12680
 2004-04-06 01:25:33 +00:00
Chris Lattner
42cf317fca Two changes: 
* In promote32, if we can just promote a constant value, do so instead of
    promoting a constant dynamically.
  * In visitReturn inst, actually USE the promote32 argument that takes a
    Value*

The end result of this is that we now generate this:

test:
        mov %EAX, 0
        ret

instead of...

test:
        mov %AX, 0
        movzx %EAX, %AX
        ret

for:

ushort %test() {
        ret ushort 0
}

llvm-svn: 12679
 2004-04-06 01:21:00 +00:00
Chris Lattner
9236135e8f Support getelementptr instructions which use uint's to index into structure 
types and can have arbitrary 32- and 64-bit integer types indexing into
sequential types.

llvm-svn: 12653
 2004-04-05 01:30:19 +00:00
Chris Lattner
c69fd63e82 In the perhaps not-to-distant future, we might support gep instructions that 
have non-long indices for sequential types.  In order to avoid trying to figure
out how the v9 backend works, we'll just hack it in the preselection pass.

llvm-svn: 12647
 2004-04-04 20:44:05 +00:00
Brian Gaeke
dec12ea71d Add support for many of the MRegisterInfo callbacks. 
Eliminating call-frame pseudo instrs and frame indices are still stubs.
Flesh out the emitPrologue method based on better ABI knowledge.

llvm-svn: 12632
 2004-04-02 20:53:37 +00:00
Brian Gaeke
b2d36cced3 Add load, store, and NOP instructions. 
Fix up comments.

llvm-svn: 12631
 2004-04-02 20:53:37 +00:00
Brian Gaeke
741518f9f6 Add support for printing pc-relative displacements of functions (as used in 
the CALL instruction).

llvm-svn: 12630
 2004-04-02 20:53:35 +00:00
Brian Gaeke
10ab592570 Add support for call instructions (0-ary only for now). 
llvm-svn: 12629
 2004-04-02 20:53:33 +00:00
Alkis Evlogimenos
27ed33c309 Clean up code a bit. 
llvm-svn: 12615
 2004-04-02 18:11:32 +00:00
Brian Gaeke
73afcebba1 Only strip symbols if emitting bytecode to the assembly file. 
Move lowerselect pass to come after preselection.  Move machine
code construction and stack slots pass to come right before instruction
selection. This is to help fix perlbmk.

Update comments.

Make the sequence of passes in addPassesToJITCompile look more like
the sequence of passes in addPassesToEmitAssembly, including support
for -print-machineinstrs.

llvm-svn: 12614
 2004-04-02 17:52:40 +00:00
Brian Gaeke
3fb4f87195 Add support for constant select expressions. Clarify the assertion failure msg. 
llvm-svn: 12613
 2004-04-02 17:52:29 +00:00
Alkis Evlogimenos
85e007a6dc Fix type in comments 
llvm-svn: 12611
 2004-04-02 16:02:50 +00:00
Alkis Evlogimenos
84ee10f9e1 Fix type in instruction builder instantiation 
llvm-svn: 12610
 2004-04-02 15:51:03 +00:00
Alkis Evlogimenos
20b074682c Add more ADC and SBB variants 
llvm-svn: 12607
 2004-04-02 07:11:10 +00:00
Chris Lattner
ef90bac3e3 Add support for select constant expressions to the CBE, fixing SIOD 
llvm-svn: 12589
 2004-04-01 05:28:26 +00:00
Chris Lattner
b6e4e5a95e Simplify code by using the more powerful BuildMI forms. 
Implement a small optimization.  In test/Regression/CodeGen/X86/select.ll,
we now generate this for foldSel3:

foldSel3:
        mov %AL, BYTE PTR [%ESP + 4]
        fld DWORD PTR [%ESP + 8]
        fld DWORD PTR [%ESP + 12]
        mov %EAX, DWORD PTR [%ESP + 16]
        mov %ECX, DWORD PTR [%ESP + 20]
        cmp %EAX, %ECX
        fxch %ST(1)
        fcmovae %ST(0), %ST(1)
***     fstp %ST(1)
        ret

Instead of:

foldSel3:
        mov %AL, BYTE PTR [%ESP + 4]
        fld DWORD PTR [%ESP + 8]
        fld DWORD PTR [%ESP + 12]
        mov %EAX, DWORD PTR [%ESP + 16]
        mov %ECX, DWORD PTR [%ESP + 20]
        cmp %EAX, %ECX
        fxch %ST(1)
        fcmovae %ST(0), %ST(1)
***     fxch %ST(1)
***     fstp %ST(0)
        ret

In practice, this only effects code size: performance should be basically
unaffected.

llvm-svn: 12588
 2004-04-01 04:06:09 +00:00
Chris Lattner
78027ca4ff Wrap at 80 cols 
llvm-svn: 12587
 2004-04-01 04:03:27 +00:00
Chris Lattner
2e0755a058 Generate slightly smaller code, "test R, R" instead of "cmp R, 0" 
llvm-svn: 12579
 2004-03-31 22:22:36 +00:00
Chris Lattner
97e8b80649 The X86 backend no longer needs the select lowering pass. 
llvm-svn: 12578
 2004-03-31 22:03:46 +00:00
Chris Lattner
e5d60adc20 Codegen FP select instructions into X86 conditional moves. Annoyingly enough 
the X86 does not support a full set of fp cmove instructions, so we can't always
fold the condition into the select.  :(  Yuck.

llvm-svn: 12577
 2004-03-31 22:03:35 +00:00
Chris Lattner
d50df93168 Add support for floating point conditional move instructions 
llvm-svn: 12576
 2004-03-31 22:02:36 +00:00
Chris Lattner
4d543b4201 Add support for FP cmoves 
llvm-svn: 12575
 2004-03-31 22:02:21 +00:00
Chris Lattner
e4fa3010db Add FP conditional move instructions, which annoyingly have special properties 
that require the asmwriter to be extended (printing implicit uses before the
explicit operands)

llvm-svn: 12574
 2004-03-31 22:02:13 +00:00
Chris Lattner
bfe4dd0f90 MBB::remove should not modify the iterator passed in 
llvm-svn: 12572
 2004-03-31 21:59:59 +00:00
Brian Gaeke
98c323dedd Factor out getStaticStackSize from InsertPrologCode(), so that I can more 
easily steal it for a separate use in the reoptimizer.

llvm-svn: 12568
 2004-03-31 20:58:37 +00:00
Chris Lattner
f477746a61 Fold comparisons into select instructions, making much better code and 
using our broad selection of movcc instructions.  :)

llvm-svn: 12560
 2004-03-30 22:39:09 +00:00
Chris Lattner
6c1dd729d3 Implement spill code folding for all of the conditional move instructions 
llvm-svn: 12554
 2004-03-30 21:29:47 +00:00
Chris Lattner
ff016bd6fe Add direct support for integer select instructions, though we still don't support 
folding compares into the select yet.

llvm-svn: 12553
 2004-03-30 21:22:00 +00:00
Chris Lattner
57968a98df Fix some serious bugs in the cmov descriptions, which didn't cause a problem because 
we never generated them

Make indentation a bit more consistent

llvm-svn: 12549
 2004-03-30 20:18:02 +00:00
Chris Lattner
95942c021a Fix a fairly major performance problem. If a PHI node had a constant as 
an incoming value from a block, the selector would evaluate the constant
at the TOP of the block instead of at the end of the block.  This made the
live range for the constant span the entire block, increasing register
pressure needlessly.

llvm-svn: 12542
 2004-03-30 19:10:12 +00:00
Chris Lattner
87479998f2 Add the select lowering pass to get initial support for select instructions 
llvm-svn: 12541
 2004-03-30 18:41:59 +00:00
Brian Gaeke
610cfaa7fd Don't warn about a null live range if the Value is a ConstantIntegral. 
Otherwise, if you're in debugging mode, you get warnings for (apparently)
every immediate constant in the function during reg. allocation.

llvm-svn: 12538
 2004-03-29 21:58:41 +00:00
Chris Lattner
4e7ea3671c Fix PR299: [Sparc] Code generator asserts on alloc of zero size type 
llvm-svn: 12504
 2004-03-19 04:21:43 +00:00
Chris Lattner
b8f179cb9b Malloc doesn't kill a load. This patch need not go into 1.2 though. 
llvm-svn: 12500
 2004-03-18 17:01:26 +00:00
Chris Lattner
ef7c1e9f7f Fix a really nasty bug that was breaking ijpeg in LLC mode. We were incorrectly 
folding load instructions into other instructions across free instruction
boundaries.  Perhaps this will also fix the other strange failures?

llvm-svn: 12494
 2004-03-18 06:29:54 +00:00
Brian Gaeke
c1c4cfd741 The .type directive on Solaris uses the # character instead of @. 
llvm-svn: 12454
 2004-03-16 22:52:04 +00:00
Brian Gaeke
f97393aebf Fix bug in zero-extending of shorts. 
llvm-svn: 12453
 2004-03-16 22:45:42 +00:00
Brian Gaeke
26deccbffb Add UMULrr and SMULrr instructions. 
llvm-svn: 12452
 2004-03-16 22:37:13 +00:00
Brian Gaeke
fd02eeae64 Use ! for comment char; it works in both Solaris as and GAS. 
llvm-svn: 12451
 2004-03-16 22:37:12 +00:00
Brian Gaeke
199ba20b20 Make getClass more robust by adding cLong. 
Add handling for Mul instruction.

llvm-svn: 12450
 2004-03-16 22:37:11 +00:00
Alkis Evlogimenos
6ac147a7fb Add LAHF instruction 
llvm-svn: 12424
 2004-03-15 17:20:14 +00:00
Alkis Evlogimenos
2b94b048a9 Another API change to MRegisterInfo::foldMemoryOperand. Instead of a 
MachineBasicBlock::iterator take a MachineInstr*.

llvm-svn: 12392
 2004-03-14 20:14:27 +00:00
Alkis Evlogimenos
ff9482b664 Change MRegisterInfo::foldMemoryOperand to return the folded 
instruction to make the API more flexible.

llvm-svn: 12386
 2004-03-14 07:19:51 +00:00
Chris Lattner
b45245327e It helps if I save the file. :) 
llvm-svn: 12357
 2004-03-13 00:24:52 +00:00
Chris Lattner
f7bc6fd913 Rename the intrinsic enum values for llvm.va_* from Intrinsic::va_* to 
Intrinsic::va*.  This avoid conflicting with macros in the stdlib.h file.

llvm-svn: 12356
 2004-03-13 00:24:00 +00:00
Brian Gaeke
5bc633f691 Make -print-machineinstrs show us the code both before and after reg. alloc. 
llvm-svn: 12344
 2004-03-12 21:19:08 +00:00
Alkis Evlogimenos
da990ad8a4 Add support for a wider range of CMOV instructions. 
llvm-svn: 12336
 2004-03-12 17:59:56 +00:00
Chris Lattner
e536e15ce1 ADd support for select instructions 
llvm-svn: 12316
 2004-03-12 05:52:14 +00:00
Misha Brukman
fe8263c956 Move implementations of functions here, which avoids #including <cstdlib> in the 
header file and all those who #include it.

llvm-svn: 12297
 2004-03-11 23:52:43 +00:00
Brian Gaeke
ede938b425 Get rid of the abort in PhyRegAlloc::finishSavingState(). 
Make an explicit call to it from runOnFunction() if we know we're supposed to
write into the global. This is lame (esp. the const_cast), but it solves
the problem.

llvm-svn: 12291
 2004-03-11 19:46:30 +00:00
Brian Gaeke
e6916ff3b4 Give pass a name 
llvm-svn: 12290
 2004-03-11 19:23:15 +00:00
Misha Brukman
992e44e3c5 Fix compilation on Sparc: assert(0) => abort() 
llvm-svn: 12289
 2004-03-11 19:08:24 +00:00
Brian Gaeke
b3f9f99ff2 In PhyRegAlloc::saveState(), dump Arguments' saved-state, and try to 
make the output more compact.

Divorce state-saving from the doFinalization method; for some reason it's not
getting called when I want it to, at Reoptimizer time. Put the guts in
PhyRegAlloc::finishSavingState(). Put an abort() in it so that I can be really
really sure that it's getting called.

Update comments.

llvm-svn: 12286
 2004-03-11 06:45:52 +00:00
Brian Gaeke
bb3d010689 Remove ghostly directory from the build 
llvm-svn: 12285
 2004-03-11 04:42:41 +00:00
Brian Gaeke
a3ed4044b0 Move all the SaveState options and stuff inton one spot at the top of the file. 
De-constify SaveStateToModule; we have to set both it and SaveRegAllocState
explicitly in the reoptimizer.
Make SaveRegAllocState an 'external location' option.

llvm-svn: 12278
 2004-03-10 22:21:03 +00:00
Brian Gaeke
8af4555830 Only call verifySavedState if SaveRegAllocState is set AND debugging flag is on. 
llvm-svn: 12277
 2004-03-10 22:01:59 +00:00
Alkis Evlogimenos
a13672fd71 Check if printing of implicit uses is required for all types of shift 
instructions.

llvm-svn: 12258
 2004-03-09 06:10:15 +00:00
Brian Gaeke
de0239b2a6 Hmm, who left this sitting around in my tree 
llvm-svn: 12255
 2004-03-09 04:49:13 +00:00
Alkis Evlogimenos
7c0224327e Differentiate between extended precision floats (80-bit) and double precision floats (64-bit) 
llvm-svn: 12254
 2004-03-09 03:37:54 +00:00
Alkis Evlogimenos
f86d2df13d Use newly added API to emit bytes for instructions that gas misassembles 
llvm-svn: 12253
 2004-03-09 03:35:34 +00:00
Alkis Evlogimenos
085957be0b Add emitInstruction() API so that we can get the bytes of a simple instruction 
llvm-svn: 12252
 2004-03-09 03:34:53 +00:00
Alkis Evlogimenos
813daf05c3 Constify things a bit 
llvm-svn: 12251
 2004-03-09 03:30:12 +00:00
Brian Gaeke
57269b0c32 Change PhyRegAlloc::saveStateForValue()'s arg type to deal with 
AllocInfo.Instruction becoming an int.

llvm-svn: 12247
 2004-03-08 23:22:03 +00:00
Brian Gaeke
ed741b87c2 Save argument list alloc state by recording it as the operands of Instruction 
#-1. Other minor changes to deal with AllocInfo.Instruction becoming an int.

llvm-svn: 12246
 2004-03-08 23:22:02 +00:00
Brian Gaeke
b9b20ad428 Make AllocInfo's Instruction an int, so that we can overload it for arguments. 
(Instruction #-1's operands = argument list).

llvm-svn: 12245
 2004-03-08 23:22:01 +00:00
Chris Lattner
a7180252e6 Avoid allocating special registers a bit more robustly 
llvm-svn: 12207
 2004-03-08 03:48:07 +00:00
Chris Lattner
a55628694a Implement folding explicit load instructions into binary operations. For a 
testcase like this:

int %test(int* %P, int %A) {
        %Pv = load int* %P
        %B = add int %A, %Pv
        ret int %B
}

We now generate:
test:
        mov %ECX, DWORD PTR [%ESP + 4]
        mov %EAX, DWORD PTR [%ESP + 8]
        add %EAX, DWORD PTR [%ECX]
        ret

Instead of:
test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EAX, DWORD PTR [%EAX]
        add %EAX, %ECX
        ret

... saving one instruction, and often a register.  Note that there are a lot
of other instructions that could use this, but they aren't handled.  I'm not
really interested in adding them, but mul/div and all of the FP instructions
could be supported as well if someone wanted to add them.

llvm-svn: 12204
 2004-03-08 01:58:35 +00:00
Chris Lattner
9a9b1c4822 Rearrange and refactor some code. No functionality changes. 
llvm-svn: 12203
 2004-03-08 01:18:36 +00:00
Alkis Evlogimenos
65649a50e9 Add memory operand version of conditional move. 
llvm-svn: 12190
 2004-03-07 03:19:11 +00:00
Brian Gaeke
4bb4ec2388 Support return values of basic integer types. 
Emit RETL instruction to return instead of funny JMPL.
Fix indentation.

llvm-svn: 12186
 2004-03-06 05:32:28 +00:00
Brian Gaeke
855518207c Sort stanzas into Sparc V8 book page number order. 
Add RET, RETL.  Rename SAVE, RESTORE & JMPL for consistency.

llvm-svn: 12185
 2004-03-06 05:32:13 +00:00
Brian Gaeke
813f0d8512 Hack it so we do not try to allocate values to G0. 
llvm-svn: 12184
 2004-03-06 05:31:32 +00:00
Brian Gaeke
a265c3c4df Make prolog align stack properly. Make epilog not touch any registers. 
llvm-svn: 12183
 2004-03-06 05:31:21 +00:00
Brian Gaeke
b4258231ca Emit register names in lowercase, as required by the assembler. 
llvm-svn: 12182
 2004-03-06 05:30:21 +00:00
Brian Gaeke
13f3e2f254 Teach getRegClassForType where to find FP registers 
llvm-svn: 12180
 2004-03-06 03:54:13 +00:00
Brian Gaeke
689af03601 Asm output is looking a lot better; not correct for all operands yet though. 
llvm-svn: 12143
 2004-03-05 08:39:09 +00:00
Brian Gaeke
a24ac9bf8b Support -print-machineinstrs 
llvm-svn: 12124
 2004-03-04 19:22:16 +00:00
Brian Gaeke
0b913593ae make -print-machineinstrs work for both SparcV9 and X86 
llvm-svn: 12122
 2004-03-04 19:16:23 +00:00
Alkis Evlogimenos
e8ebdcc780 Add assertion for scale verification. 
llvm-svn: 12120
 2004-03-04 18:05:02 +00:00
Brian Gaeke
9c6c572f24 Asm printer support, based on x86 - only prints mnemonics for now 
llvm-svn: 12113
 2004-03-04 06:00:41 +00:00
Brian Gaeke
f8440c5a60 Double-FP pseudo-registers. 
llvm-svn: 12112
 2004-03-04 05:15:03 +00:00
Brian Gaeke
b2f869ee43 Subtract instructions; minor cleanups 
llvm-svn: 12111
 2004-03-04 04:37:45 +00:00
Brian Gaeke
0d71671bcf Floating point regs 
llvm-svn: 12110
 2004-03-04 04:37:22 +00:00
Brian Gaeke
9ebecfdfe0 Simple copyConstantToReg support, SETHIi and ORri 
llvm-svn: 12107
 2004-03-04 00:56:25 +00:00
Brian Gaeke
324c928e36 Support add - note, still missing important copyConstantToRegister stuff 
llvm-svn: 12106
 2004-03-03 23:03:14 +00:00
Chris Lattner
6978f97701 SPECIFY a target data to initialize the CBE target with. Until now we have 
been using the default target data layout object to lower malloc instructions,
causing us to allocate more memory than we needed!  This could improve the
performance of the CBE generated code substantially!

llvm-svn: 12088
 2004-03-03 02:14:15 +00:00
Chris Lattner
8f80c299f2 Add a new constructor 
llvm-svn: 12087
 2004-03-03 02:12:47 +00:00
Misha Brukman
491ff34abf Doxygenify some comments. 
llvm-svn: 12064
 2004-03-01 23:53:11 +00:00
Chris Lattner
4d192a2674 Add this back, as its absence introduces assertions, and it seems to work now 
that Instructions are annotable again

llvm-svn: 12045
 2004-03-01 15:28:27 +00:00
Tanya Lattner
b22016f21b fix bug in previous checkin 
llvm-svn: 12044
 2004-03-01 15:05:17 +00:00
Brian Gaeke
b78f8498f0 TargetCacheInfo has been removed; its only uses were to propagate a constant 
(16) into certain areas of the SPARC V9 back-end. I'm fairly sure the US IIIi's
dcache has 32-byte lines, so I'm not sure where the 16 came from. However, in
the interest of not breaking things any more than they already are, I'm going
to leave the constant alone.

llvm-svn: 12043
 2004-03-01 06:43:29 +00:00
Chris Lattner
8c1d67b55f Handle passing constant integers to functions much more efficiently. Instead 
of generating this code:

        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        call Y

we now generate:
        mov DWORD PTR [%ESP], 4
        mov DWORD PTR [%ESP + 4], 123
        call Y

Which hurts the eyes less.  :)

Considering that register pressure around call sites is already high (with all
of the callee clobber registers n stuff), this may help a lot.

llvm-svn: 12028
 2004-03-01 02:42:43 +00:00
Chris Lattner
c686a9ab37 Fix a minor code-quality issue. When passing 8 and 16-bit integer constants 
to function calls, we would emit dead code, like this:

int Y(int, short, double);
int X() {
  Y(4, 123, 4);
}

--- Old
X:
        sub %ESP, 20
        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
***     mov %AX, 123
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        fld QWORD PTR [.CPIX_0]
        fstp QWORD PTR [%ESP + 8]
        call Y
        mov %EAX, 0
        # IMPLICIT_USE %EAX %ESP
        add %ESP, 20
        ret

Now we emit:
X:
        sub %ESP, 20
        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        fld QWORD PTR [.CPIX_0]
        fstp QWORD PTR [%ESP + 8]
        call Y
        mov %EAX, 0
        # IMPLICIT_USE %EAX %ESP
        add %ESP, 20
        ret

Next up, eliminate the mov AX and movsx entirely!

llvm-svn: 12026
 2004-03-01 02:34:08 +00:00
Chris Lattner
4c7ed6793e Remove public header. It's been moved to lib/Target/SparcV9 
llvm-svn: 12004
 2004-02-29 19:13:20 +00:00
Chris Lattner
fe38629411 Move the private MachineInstrAnnot.h into a private directory. 
llvm-svn: 12003
 2004-02-29 19:12:51 +00:00
Alkis Evlogimenos
e186d8eb2f Add instruction name description. 
llvm-svn: 11998
 2004-02-29 18:44:03 +00:00
Alkis Evlogimenos
8d8f872b3d Use correct template for SHLD and SHRD instructions so that the memory 
operand size is correctly specified.

llvm-svn: 11997
 2004-02-29 09:19:40 +00:00
Alkis Evlogimenos
10f4523e9a Improve allocation order: 
1) For 8-bit registers try to use first the ones that are parts of the
   same register (AL then AH). This way we only alias 2 16/32-bit
   registers after allocating 4 8-bit variables.

2) Move EBX as the last register to allocate. This will cause less
   spills to happen since we will have 8-bit registers available up to
   register excaustion (assuming we use the allocation order). It
   would be nice if we could push all of the 8-bit aliased registers
   towards the end but we much prefer to keep callee saved register to
   the end to avoid saving them on entry and exit of the function.

For example this gives a slight reduction of spills with linear scan
on 164.gzip.

Before:

11221 asm-printer           - Number of machine instrs printed
  975 spiller               - Number of loads added
  675 spiller               - Number of stores added
  398 spiller               - Number of register spills

After:

11182 asm-printer           - Number of machine instrs printed
  952 spiller               - Number of loads added
  652 spiller               - Number of stores added
  386 spiller               - Number of register spills

llvm-svn: 11996
 2004-02-29 09:17:01 +00:00
Alkis Evlogimenos
7ecfe0a839 A big X86 instruction rename. The instructions are renamed to make 
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory

llvm-svn: 11995
 2004-02-29 08:50:03 +00:00
Brian Gaeke
8303cb575e Remove dead member variables of SparcV9SchedInfo and TargetSchedInfo 
llvm-svn: 11994
 2004-02-29 08:40:03 +00:00
Chris Lattner
a7db4ff17a Eliminate the X86-specific BMI functions, using BuildMI instead. 
Replace uses of addZImm with addImm.

llvm-svn: 11992
 2004-02-29 07:22:16 +00:00
Chris Lattner
e8e0bafbba Fix a miscompilation of 197.parser that occurs when you have single basic 
block loops.

llvm-svn: 11990
 2004-02-29 07:10:16 +00:00
Chris Lattner
c2977ac665 Adjust to change in TII ctor arguments 
llvm-svn: 11987
 2004-02-29 06:31:44 +00:00
Chris Lattner
b5f0e162c7 Eliminate the distinction between "real" and "unreal" instructions 
llvm-svn: 11986
 2004-02-29 06:31:16 +00:00
Chris Lattner
cfc8f02250 These two virtual methods are never called. 
llvm-svn: 11984
 2004-02-29 05:59:33 +00:00
Chris Lattner
dd752eec34 Remove a TON of flags that noone cares about 
llvm-svn: 11983
 2004-02-29 05:58:30 +00:00
Chris Lattner
d80ff1bdc0 Noone calls these virtual methods 
llvm-svn: 11982
 2004-02-29 05:58:16 +00:00
Chris Lattner
dded7ad224 This is the only file in the system that uses this enum. eliminate it. 
llvm-svn: 11981
 2004-02-29 05:57:59 +00:00
Chris Lattner
7cb71a20ca Implement initial prolog/epilog code insertion methods. 
llvm-svn: 11979
 2004-02-29 05:18:30 +00:00
Alkis Evlogimenos
0f96b44e0e Use correct template for ADC instruction with memory operands. 
llvm-svn: 11974
 2004-02-29 02:18:17 +00:00
Chris Lattner
800f720e7b Add an instruction selector capable of selecting 'ret void' 
llvm-svn: 11973
 2004-02-29 00:27:00 +00:00
Alkis Evlogimenos
6815402082 SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them 
to denote this fact.

llvm-svn: 11972
 2004-02-28 23:46:44 +00:00
Alkis Evlogimenos
e8dac99a43 Floating point loads/stores act on memory operands. Rename them to 
denote this fact.

llvm-svn: 11971
 2004-02-28 23:42:35 +00:00
Alkis Evlogimenos
1d71a15be9 Rename instruction templates to be easier to the human eye to 
parse. The name is now I (operand size)*. For example:

Im32 -> instruction with 32-bit memory operands.

Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
          operands.

llvm-svn: 11970
 2004-02-28 23:09:03 +00:00
Alkis Evlogimenos
6038a89025 Uncomment instructions that take both an immediate and a memory 
operand but their sizes differ.

llvm-svn: 11969
 2004-02-28 22:06:59 +00:00
Alkis Evlogimenos
f208a0fd81 Each instruction now has both an ImmType and a MemType. This describes 
the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).

llvm-svn: 11967
 2004-02-28 22:02:05 +00:00
Chris Lattner
3583890ab7 Change this so that LLC actually tries to run the code generator, though it will 
immediately abort due to lack of an instruction selector. :)

llvm-svn: 11963
 2004-02-28 20:21:45 +00:00
Chris Lattner
529a354ea4 SparcV8 now builds. 
llvm-svn: 11960
 2004-02-28 19:54:00 +00:00
Chris Lattner
5effdb67b7 fine grainify namespacification 
llvm-svn: 11959
 2004-02-28 19:53:18 +00:00
Chris Lattner
3852b0c3b8 Finegrainify namespacification 
llvm-svn: 11958
 2004-02-28 19:52:49 +00:00
Chris Lattner
88268605ec Tab completion is our friend. 
llvm-svn: 11957
 2004-02-28 19:45:39 +00:00
Chris Lattner
013aa47975 Clean up rules 
llvm-svn: 11956
 2004-02-28 19:43:40 +00:00
Chris Lattner
d2bb7e91b0 Bring this directory into "it actually compiles" land 
llvm-svn: 11955
 2004-02-28 19:37:18 +00:00
Chris Lattner
3f70429d28 Fix multiple inclusion problem 
llvm-svn: 11954
 2004-02-28 19:31:32 +00:00
Alkis Evlogimenos
977dbaadf7 Do not generate instructions with mismatched memory/immediate sized 
operands. The X86 backend doesn't handle them properly right now.

llvm-svn: 11944
 2004-02-28 06:01:43 +00:00
Alkis Evlogimenos
84f00e93f7 Further comment updates. 
llvm-svn: 11933
 2004-02-28 03:20:31 +00:00
Alkis Evlogimenos
edbe362160 Update comments. 
llvm-svn: 11932
 2004-02-28 03:12:31 +00:00
Alkis Evlogimenos
0f91ce52a0 My previous commit broke the jit. The shift instructions always take 
an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.

A bug still exists:

def SHLDmri32  : I2A8 <"shld", 0xA4, MRMDestMem>, TB;           // [mem32] <<= [mem32],R32 imm8

The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.

llvm-svn: 11931
 2004-02-28 02:56:26 +00:00
Brian Gaeke
6afa0813d2 Turn off the SparcV9MachineCodeDestructionPass for now, because it's buggy 
llvm-svn: 11930
 2004-02-27 21:15:40 +00:00
Brian Gaeke
0e74ff91a0 Correct DestroyMachineFunction's getPassName 
llvm-svn: 11929
 2004-02-27 21:01:14 +00:00
Alkis Evlogimenos
ace6d81654 Fix argument size for SHL, SHR, SAR, SHLD and SHRD families of 
instructions.

llvm-svn: 11923
 2004-02-27 19:46:30 +00:00
Alkis Evlogimenos
839c70f45d Fix encoding of ADD and SUB family of instructions. Also rearrange 
them so that they are consistent with AND, XOR, etc...

llvm-svn: 11922
 2004-02-27 18:57:00 +00:00
Alkis Evlogimenos
56d357aa23 Rename MRMS[0-7]{r,m} to MRM[0-7]{r,m}. 
llvm-svn: 11921
 2004-02-27 18:55:12 +00:00
Alkis Evlogimenos
5ac109957f Add memory operand folding support for the SETcc family of 
instructions.

llvm-svn: 11907
 2004-02-27 16:13:37 +00:00
Alkis Evlogimenos
0742b93bb9 Add memory operand folding support for SHLD and SHRD instructions. 
llvm-svn: 11905
 2004-02-27 15:03:18 +00:00
Alkis Evlogimenos
b1f67f6741 Add memory operand folding support for SHL, SHR and SAR, SHLD instructions. 
llvm-svn: 11903
 2004-02-27 09:28:43 +00:00
Alkis Evlogimenos
cf49d13ed2 Rename SHL, SHR, SAR, SHLD and SHLR instructions to make them 
consistent with the rest and also pepare for the addition of their
memory operand variants.

llvm-svn: 11902
 2004-02-27 06:57:05 +00:00
John Criswell
0b01bff060 Fixes for PR258 and PR259. 
Functions with linkonce linkage are declared with weak linkage.
Global floating point constants used to represent unprintable values
(such as NaN and infinity) are declared static so that they don't interfere
with other CBE generated translation units.

llvm-svn: 11884
 2004-02-26 22:20:58 +00:00
Alkis Evlogimenos
b15631fcfa Uncomment assertions that register# != 0 on calls to 
MRegisterInfo::is{Physical,Virtual}Register. Apply appropriate fixes
to relevant files.

llvm-svn: 11882
 2004-02-26 22:00:20 +00:00
Chris Lattner
4aff6ec077 Use a map instead of annotations 
llvm-svn: 11875
 2004-02-26 08:02:17 +00:00
Chris Lattner
6a3796eaf9 Fix some warnings, some of which were spurious, and some of which were real 
bugs.  Thanks Brian!

llvm-svn: 11859
 2004-02-26 01:20:02 +00:00
Misha Brukman
3d1720cdb9 Instructions to call and return from functions. 
llvm-svn: 11858
 2004-02-26 00:37:12 +00:00
Misha Brukman
6a13621948 SparcV8 regs are really 32-bit, not 64! Thanks, Chris. 
llvm-svn: 11835
 2004-02-25 21:03:02 +00:00
Misha Brukman
f12c1e5a55 Clean up the tablegen descriptions for SparcV8. 
llvm-svn: 11834
 2004-02-25 21:02:21 +00:00