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22 Commits

Author SHA1 Message Date
Peter Collingbourne
a067ba4392 Target: Remove unused patterns and transforms. NFC. 
llvm-svn: 283515
 2016-10-07 00:30:49 +00:00
Matt Arsenault
d3892e17d5 AMDGPU: Select mulhi 24-bit instructions 
llvm-svn: 279902
 2016-08-27 01:32:27 +00:00
Jan Vesely
44baa3114f AMDGPU/R600: Convert buffer id to VTX_READ input 
Use patterns instead of multiple instructions
Add buffer id to asm string

https://reviews.llvm.org/D22650

llvm-svn: 278749
 2016-08-15 21:38:30 +00:00
Matt Arsenault
6e4504e0db AMDGPU: Fix TargetPrefix for remaining r600 intrinsics 
llvm-svn: 275619
 2016-07-15 21:27:08 +00:00
Matt Arsenault
3bfc10ac74 AMDGPU: Remove legacy rsq.clamped intrinsic 
Mesa still has a use of llvm.AMDGPU.rsq.f64 remaining.

Also fix mismatch with non-IEEE rsq selecting to IEEE rsq.

llvm-svn: 275617
 2016-07-15 21:26:52 +00:00
Matt Arsenault
ce4eceea10 AMDGPU/R600: Delete/rename intrinsics no longer used by mesa 
Use the replacement pass to update the tests, and delete old names.

llvm-svn: 275375
 2016-07-14 05:47:17 +00:00
Matt Arsenault
a42057703b AMDGPU/R600: Remove intrinsics with no tests and no users 
Mesa removed this path, so nothing is using these anymore.

llvm-svn: 275372
 2016-07-14 05:23:23 +00:00
Jan Vesely
ba1aea29ff AMDGPU/R600: Add implicitarg.ptr intrinsic 
Differential Revision: http://reviews.llvm.org/D21622

llvm-svn: 275024
 2016-07-10 21:20:29 +00:00
Tom Stellard
63fc45cc8d AMDGPU/R600: Add PatFrags for selecting the correct vtx id for loads 
This moves of the r600 logic out of isGlobalLoad() and into the
TableGen files.

Differential Revision: http://reviews.llvm.org/D21710

llvm-svn: 274527
 2016-07-05 00:12:51 +00:00
Jan Vesely
c03890ec2f AMDGPU/R600: Add indentation to VTX and TEX fetch asm strings 
These are printed as part of Fetch clauses.

Differential Revision: http://reviews.llvm.org/D21730

llvm-svn: 274517
 2016-07-04 19:45:00 +00:00
Matt Arsenault
8603948f83 AMDGPU: Cleanup subtarget handling. 
Split AMDGPUSubtarget into amdgcn/r600 specific subclasses.
This removes most of the static_casting of the basic codegen
classes everywhere, and tries to restrict the features
visible on the wrong target.

llvm-svn: 273652
 2016-06-24 06:30:11 +00:00
Matt Arsenault
66eec46266 AMDGPU: Fix verifier errors in SILowerControlFlow 
The main sin this was committing was using terminator
instructions in the middle of the block, and then
not updating the block successors / predecessors.
Split the blocks up to avoid this and introduce new
pseudo instructions for branches taken with exec masking.

Also use a pseudo instead of emitting s_endpgm and erasing
it in the special case of a non-void return.

llvm-svn: 273467
 2016-06-22 20:15:28 +00:00
Jan Vesely
8960f3da2c AMDGPU/R600: Implement memory loads from constant AS 
Reviewers: tstellard

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D19792

llvm-svn: 269479
 2016-05-13 20:39:29 +00:00
Matt Arsenault
4ff4c396c1 AMDGPU: Rename intrinsic to better match instruction name 
Also fixes missing f32 test.

llvm-svn: 260780
 2016-02-13 01:03:00 +00:00
Matt Arsenault
b119805900 AMDGPU: Remove 24-bit intrinsics 
The known bit matching code seems to work reasonably well,
so these shouldn't really be needed.

llvm-svn: 259180
 2016-01-29 10:05:16 +00:00
Matt Arsenault
fe8ee22547 AMDGPU: Remove more unused intrinsics 
Replace tests with lrp with basic IR expansion

llvm-svn: 258612
 2016-01-23 05:42:38 +00:00
Matt Arsenault
351925633e AMDGPU: Remove random TGSI intrinsic 
I don't think this was ever used.

llvm-svn: 258514
 2016-01-22 18:42:44 +00:00
Matt Arsenault
21c6e6f537 AMDGPU: Remove AMDGPU.fract intrinsic 
Mesa doesn't use this, and this is pattern matched already
from fsub x, (ffloor x)

llvm-svn: 258513
 2016-01-22 18:42:38 +00:00
Bruce Mitchener
9ad7a63fa9 Fix typos. 
Summary: This fixes a variety of typos in docs, code and headers.

Subscribers: jholewinski, sanjoy, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D12626

llvm-svn: 247495
 2015-09-12 01:17:08 +00:00
Tom Stellard
3f1708598e R600 -> AMDGPU rename 
llvm-svn: 239657
 2015-06-13 03:28:10 +00:00
Tom Stellard
39f7e52397 Revert "AMDGPU: Add core backend files for R600/SI codegen v6" 
This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea.

llvm-svn: 160303
 2012-07-16 18:19:53 +00:00
Tom Stellard
9f326179fc AMDGPU: Add core backend files for R600/SI codegen v6 
llvm-svn: 160270
 2012-07-16 14:17:08 +00:00