RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-26 14:33:02 +02:00
Code Issues Projects Releases Wiki Activity
66,160 Commits 4 Branches 5 Tags 704 MiB
ddd67f8e88
Commit Graph

66160 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Jim Grosbach
ddd67f8e88 Formatting. 
llvm-svn: 117453
 2010-10-27 16:30:18 +00:00
Rafael Espindola
58a0ea80a4 Symbols defined as the difference of other two end up in the ABS section. 
llvm-svn: 117451
 2010-10-27 16:04:30 +00:00
Rafael Espindola
23d05a8675 Add support for the .symver directive. This is really ugly, but most of it is 
contained in the ELF object writer.

llvm-svn: 117448
 2010-10-27 15:18:17 +00:00
Rafael Espindola
f5b4013598 Move more logic to isInSymtab and simplify. 
llvm-svn: 117447
 2010-10-27 14:44:52 +00:00
Mikhail Glushenkov
df4eb2e516 80-col violation. 
llvm-svn: 117443
 2010-10-27 09:09:10 +00:00
Mikhail Glushenkov
5eeaebe9b8 Remove try/catch(...) from Win32/Signals.inc. 
catch(...) is used in Win32/Signals.inc for catching Win32 structured
exceptions, but according to [1], this is wrong.

We can't simply change try/catch to __try/__finally, since this syntax is not
supported by MinGW. We can use __try/__finally on MSVC and __try1/__except1
macros on MinGW [2], but I think that that solution obfuscates the code too
much.

The use of try/catch(...) in Signals.inc makes it impossible to link
MinGW-compiled libSystem with llvm-gcc compiled executables. I propose that we
just remove try/catch(...) from Signals.inc, since the meaning of the code won't
change.

[1] http://members.cox.net/doug_web/eh.htm
[2] http://article.gmane.org/gmane.comp.compilers.llvm.cvs/81315

llvm-svn: 117442
 2010-10-27 09:09:04 +00:00
Mikhail Glushenkov
64c0814208 It is confusing to call a random-access iterator 'InputIterator'. 
llvm-svn: 117441
 2010-10-27 07:39:54 +00:00
Mikhail Glushenkov
a52646c12e Trailing whitespace. 
llvm-svn: 117440
 2010-10-27 07:39:48 +00:00
Kevin Enderby
74a2614673 Yet another tweak to X86 instructions to add ud2a as an alias to ud2 
(still to add ud2b).

llvm-svn: 117435
 2010-10-27 03:01:02 +00:00
Kevin Enderby
d22f3b9de7 Another tweak to X86 instructions to add the missing flex instruction (without 
the wait prefix).

llvm-svn: 117434
 2010-10-27 02:53:04 +00:00
Kevin Enderby
e812b356cc Tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

llvm-svn: 117433
 2010-10-27 02:32:19 +00:00
Jim Grosbach
5ccda16fe2 LDRi12 machine instructions handle negative offset operands normally (simple 
integer values), not with the addrmode2 encoding.

llvm-svn: 117429
 2010-10-27 01:19:41 +00:00
Bill Wendling
bead915338 Random cleanups and format changes. 
llvm-svn: 117428
 2010-10-27 01:07:41 +00:00
Kevin Enderby
d5235bb45c Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc 
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

llvm-svn: 117427
 2010-10-27 00:59:28 +00:00
Jakob Stoklund Olesen
66180b2c06 Handle critical loop predecessors by making both inside and outside registers 
live out.

This doesn't prevent us from inserting a loop preheader later on, if that is
better.

llvm-svn: 117424
 2010-10-27 00:39:07 +00:00
Jakob Stoklund Olesen
514eb703b8 Compute critical loop predecessors in the same way as critical loop exits. 
Critical edges going into a loop are not as bad as critical exits. We can handle
them by splitting the critical edge, or by having both inside and outside
registers live out of the predecessor.

llvm-svn: 117423
 2010-10-27 00:39:05 +00:00
Jakob Stoklund Olesen
4701c56446 Physical registers trivially have multiple connected components all the time. 
Only virtuals should be requires to be connected.

llvm-svn: 117422
 2010-10-27 00:39:01 +00:00
Jim Grosbach
6453c7cdf9 One more spot where the new arm mode LDR instruction representation 
doesn't need the additional addrmode2 register operand. Missed it the first
time around.

llvm-svn: 117421
 2010-10-27 00:38:16 +00:00
Wesley Peck
854507453a Adding disassembler to the MicroBlaze backend. 
llvm-svn: 117420
 2010-10-27 00:23:01 +00:00
Jim Grosbach
4d4caf1384 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

llvm-svn: 117419
 2010-10-27 00:19:44 +00:00
Jim Grosbach
625e128d29 Since I parameterized this bit, I should probably actually use said parameter. 
llvm-svn: 117418
 2010-10-26 23:58:04 +00:00
Dan Gohman
3200547546 Enable clang autocompletion by default. 
llvm-svn: 117415
 2010-10-26 23:24:54 +00:00
Dale Johannesen
e7f07349e4 Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches 
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet).  No functional change except
for dump output.

llvm-svn: 117413
 2010-10-26 23:11:10 +00:00
Andrew Trick
6363e80ded Remove the vector of live vregs. I thought we would need to track 
them, but hopefully we won't. And this is not the right data structure
to do it anyway.

llvm-svn: 117412
 2010-10-26 22:58:24 +00:00
Owen Anderson
1dc05f20e2 Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun. 
llvm-svn: 117411
 2010-10-26 22:50:46 +00:00
Jim Grosbach
30f6744f05 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Jakob Stoklund Olesen
bb4b26c42b After splitting, compute connected components of all new registers, not just for 
the remainder register.

Example:

bb0:
  x = 1
bb1:
  use(x)
  ...
  x = 2
  jump bb1

When x is isolated in bb1, the inner part breaks into two components, x1 and x2:

bb0:
  x0 = 1
bb1:
  x1 = x0
  use(x1)
  ...
  x2 = 2
  x0 = x2
  jump bb1

llvm-svn: 117408
 2010-10-26 22:36:09 +00:00
Jakob Stoklund Olesen
3bf3211458 Verify that live intervals are connected. If there are multiple connected 
components, each should get its own virtual register.

llvm-svn: 117407
 2010-10-26 22:36:07 +00:00
Jakob Stoklund Olesen
fa777d622d Call RenumberValues for all new registers created during splitting. This is 
necessary to get correct hasPHIKill flags.

llvm-svn: 117406
 2010-10-26 22:36:05 +00:00
Jakob Stoklund Olesen
0007e9a345 Preserve PHIDef bits in cloned values during splitting. 
llvm-svn: 117405
 2010-10-26 22:36:02 +00:00
Devang Patel
7796146304 Assign source ordering to nodes created for StoreInst. 
llvm-svn: 117404
 2010-10-26 22:14:52 +00:00
Owen Anderson
55c0bad37d Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn. 
llvm-svn: 117402
 2010-10-26 21:58:41 +00:00
Jim Grosbach
afc1e913c0 FileCheck'ize 
llvm-svn: 117401
 2010-10-26 21:26:47 +00:00
Owen Anderson
71deab0da0 Add tests for NEON encoding of vshll. 
llvm-svn: 117399
 2010-10-26 21:21:47 +00:00
Owen Anderson
570a4cdc45 Simplify classes for shift instructions, which are never commutable. 
llvm-svn: 117398
 2010-10-26 21:13:59 +00:00
Owen Anderson
31c1429a2c Tests for NEON encoding of vshr. 
llvm-svn: 117396
 2010-10-26 21:08:42 +00:00
Owen Anderson
0cecbd810e Provide correct NEON encodings for vshl, register and immediate forms. 
llvm-svn: 117394
 2010-10-26 20:56:57 +00:00
Jakob Stoklund Olesen
3a4c0c13eb Teach MachineBasicBlock::print() to annotate instructions and blocks with 
SlotIndexes when available.

llvm-svn: 117392
 2010-10-26 20:21:46 +00:00
Jakob Stoklund Olesen
195132633a Remmeber to print full live interval on verification error. 
llvm-svn: 117391
 2010-10-26 20:21:43 +00:00
Rafael Espindola
50d3c29c30 Add support for .ident. 
llvm-svn: 117389
 2010-10-26 19:35:47 +00:00
Jim Grosbach
04cd5e5841 Grammar. 
llvm-svn: 117388
 2010-10-26 19:34:41 +00:00
Jim Grosbach
db5b1d93c2 Nuke extraneous comment. It's applicable elsewhere, but not in this func. 
llvm-svn: 117387
 2010-10-26 19:22:23 +00:00
Owen Anderson
ee9f7e6c20 Tests for NEON encoding of vrecpe, vrecps, vrsqrte, and vsqrts. 
llvm-svn: 117385
 2010-10-26 18:43:13 +00:00
Andrew Trick
06fb7ed472 Jakob's review of the basic register allocator. 
llvm-svn: 117384
 2010-10-26 18:34:01 +00:00
Owen Anderson
9e49cae184 Tests for NEON encodings of vpmin and vpmax. 
llvm-svn: 117382
 2010-10-26 18:31:47 +00:00
Owen Anderson
d8e5d26a56 Add correct NEON encoding for vpadal. 
llvm-svn: 117380
 2010-10-26 18:18:03 +00:00
Rafael Espindola
adaf2ea5c6 handle X86::EH_RETURN64 and X86::EH_RETURN. 
llvm-svn: 117378
 2010-10-26 18:09:55 +00:00
Owen Anderson
1940ad62ca Tests for NEON encoding of vpadd and vpaddl. 
llvm-svn: 117377
 2010-10-26 18:04:51 +00:00
Devang Patel
e544bb3842 s/beginScope/beginInstruction/g 
s/endScope/endInstruction/g

llvm-svn: 117376
 2010-10-26 17:49:02 +00:00
Owen Anderson
b7618a821f Add NEON encodings for vmov and vmvn of immediates. 
llvm-svn: 117374
 2010-10-26 17:40:54 +00:00