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4296 Commits

Author SHA1 Message Date
Bill Wendling
fca05e3a5c Add a -no-implicit-float flag. This acts like -soft-float, but may generate 
floating point instructions that are explicitly specified by the user.

llvm-svn: 66719
 2009-03-11 22:30:01 +00:00
Duncan Sands
b27c523449 It makes no sense to have a ODR version of common 
linkage, so remove it.

llvm-svn: 66690
 2009-03-11 20:14:15 +00:00
Mon P Wang
287e422039 For yonah, fix a vector shuffle case for v16i8 where we didn't properly clear some bits. 
llvm-svn: 66684
 2009-03-11 18:47:57 +00:00
Mon P Wang
2867737ad2 Fixed a v8i16 shuffle case that should generate a pshufb instead of a pshuflw/hw. 
llvm-svn: 66645
 2009-03-11 06:35:11 +00:00
Chris Lattner
eb9327f335 formatting change, reduce indentation. No functionality change. 
llvm-svn: 66642
 2009-03-11 05:48:52 +00:00
Dan Gohman
e15d8f03c3 Add more information to the EFLAGS note. 
llvm-svn: 66515
 2009-03-10 00:26:23 +00:00
Dan Gohman
995c3dd344 Add a note about EFLAGS optimization. 
llvm-svn: 66508
 2009-03-09 23:47:02 +00:00
Chris Lattner
b89dbcd448 do not export all the X86FastISel symbols, ever. 
llvm-svn: 66382
 2009-03-08 18:44:31 +00:00
Chris Lattner
3342ba06d4 add a note. 
llvm-svn: 66360
 2009-03-08 03:04:26 +00:00
Chris Lattner
8ace06fdda add a note. 
llvm-svn: 66359
 2009-03-08 01:54:43 +00:00
Duncan Sands
5ab54d488f Introduce new linkage types linkonce_odr, weak_odr, common_odr 
and extern_weak_odr.  These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global.  In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time.   This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function.  If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body.  The
code generators on the other hand map weak and weak_odr linkage
to the same thing.

llvm-svn: 66339
 2009-03-07 15:45:40 +00:00
Dan Gohman
b9c32f1aca Arithmetic instructions don't set EFLAGS bits OF and CF bits 
the same say the "test" instruction does in overflow cases,
so eliminating the test is only safe when those bits aren't
needed, as is the case for COND_E and COND_NE, or if it
can be proven that no overflow will occur. For now, just
restrict the optimization to COND_E and COND_NE and don't
do any overflow analysis.

llvm-svn: 66318
 2009-03-07 01:58:32 +00:00
Dan Gohman
f9599e6c5f Don't use plain INC32 and DEC32 on x86-64; it needs 
INC64_32r and INC64_16r, because these instructions are encoded
differently on x86-64. This fixes JIT regressions on x86-64 in
kimwitu++ and others.

llvm-svn: 66207
 2009-03-05 21:32:23 +00:00
Dan Gohman
1e9db7c1a1 When creating X86ISD::INC and X86ISD::DEC nodes, only add one operand. 
The extra operand didn't appear to cause any trouble, but it was
erroneous regardless.

llvm-svn: 66206
 2009-03-05 21:29:28 +00:00
Dan Gohman
f6f684b206 Fix the "test" optimization to recognize "dec" as an add of 
negative one, as subtracts of immediates are canonicalized
to adds.

llvm-svn: 66180
 2009-03-05 19:32:48 +00:00
Dan Gohman
31fb085c2e Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. 
llvm-svn: 66058
 2009-03-04 19:44:21 +00:00
Dan Gohman
f41e54c5af Correct this comment. 
llvm-svn: 66057
 2009-03-04 19:24:25 +00:00
Dan Gohman
04453ca36c When using MachineInstr operand indices on SDNodes, the number 
of MachineInstr def operands must be subtracted out. This bug
was uncovered by the recent x86 EFLAGS optimization. Before
that, the only instructions that ever needed unfolding were
things like CMP32rm, where NumDefs is zero.

llvm-svn: 66056
 2009-03-04 19:23:38 +00:00
Evan Cheng
7d9019d0f3 Fix PR3666: isel calls to constant addresses. 
llvm-svn: 66024
 2009-03-04 06:48:53 +00:00
Dan Gohman
6831e2c2a6 Revert r66004 for now; it's causing a variety of test failures. 
llvm-svn: 66008
 2009-03-04 03:54:19 +00:00
Dan Gohman
c6c669cc1e Teach the x86 backend to eliminate "test" instructions by using the EFLAGS 
result from add, sub, inc, and dec instructions in simple cases.

llvm-svn: 66004
 2009-03-04 02:33:24 +00:00
Evan Cheng
db402a7a49 Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. 
llvm-svn: 65996
 2009-03-04 01:41:49 +00:00
Dan Gohman
3c6c7754b2 Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC 
instructions. These aren't used yet.

llvm-svn: 65965
 2009-03-03 19:53:46 +00:00
Dan Gohman
51d4e8db6a Fix a bunch of Doxygen syntax issues. Escape special characters, 
and put @file directives on their own comment line.

llvm-svn: 65920
 2009-03-03 02:55:14 +00:00
Mon P Wang
0258a27c5a Added another darwin subtarget 
llvm-svn: 65662
 2009-02-28 00:25:30 +00:00
Rafael Espindola
880e63bf01 Refactor TLS code and add some tests. The tests and expected results are: 
pic |  declaration | linkage  | visibility |

!pic |  declaration | external | default    | tls1.ll     tls2.ll     | local exec
 pic |  declaration | external | default    | tls1-pic.ll tls2-pic.ll | general dynamic
!pic | !declaration | external | default    | tls3.ll     tls4.ll     | initial exec
 pic | !declaration | external | default    | tls3-pic.ll tls4-pic.ll | general dynamic

!pic |  declaration | external | hidden     | tls7.ll     tls8.ll     | local exec
 pic |  declaration | external | hidden     | X                       | local dynamic
!pic | !declaration | external | hidden     | tls9.ll     tls10.ll    | local exec
 pic | !declaration | external | hidden     | X                       | local dynamic

!pic |  declaration | internal | default    | tls5.ll     tls6.ll     | local exec
 pic |  declaration | internal | default    | X                       | local dynamic

The ones marked with an X have not been implemented since local dynamic is not implemented.

llvm-svn: 65632
 2009-02-27 13:37:18 +00:00
Evan Cheng
4014a9a5b8 ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified. 
llvm-svn: 65499
 2009-02-26 03:12:02 +00:00
Evan Cheng
ec34226c2b Revert BuildVectorSDNode related patches: 65426, 65427, and 65296. 
llvm-svn: 65482
 2009-02-25 22:49:59 +00:00
Bill Wendling
9d4eb136da Overhaul my earlier submission due to feedback. It's a large patch, but most of 
them are generic changes.

- Use the "fast" flag that's already being passed into the asm printers instead
  of shoving it into the DwarfWriter.

- Instead of calling "MI->getParent()->getParent()" for every MI, set the
  machine function when calling "runOnMachineFunction" in the asm printers.

llvm-svn: 65379
 2009-02-24 08:30:20 +00:00
Dan Gohman
3766eeea36 Fast-isel can't do TLS yet, so it should fall back to SDISel 
if it sees TLS addresses.

llvm-svn: 65341
 2009-02-23 22:03:08 +00:00
Evan Cheng
dd139e795c Only v1i16 (i.e. _m64) is returned via RAX / RDX. 
llvm-svn: 65313
 2009-02-23 09:03:22 +00:00
Nate Begeman
e0093d2501 Generate better code for v8i16 shuffles on SSE2 
Generate better code for v16i8 shuffles on SSE2 (avoids stack)
Generate pshufb for v8i16 and v16i8 shuffles on SSSE3 where it is fewer uops.
Document the shuffle matching logic and add some FIXMEs for later further
  cleanups.
New tests that test the above.

Examples:

New:
_shuf2:
	pextrw	$7, %xmm0, %eax
	punpcklqdq	%xmm1, %xmm0
	pshuflw	$128, %xmm0, %xmm0
	pinsrw	$2, %eax, %xmm0

Old:
_shuf2:
	pextrw	$2, %xmm0, %eax
	pextrw	$7, %xmm0, %ecx
	pinsrw	$2, %ecx, %xmm0
	pinsrw	$3, %eax, %xmm0
	movd	%xmm1, %eax
	pinsrw	$4, %eax, %xmm0
	ret

=========

New:
_shuf4:
	punpcklqdq	%xmm1, %xmm0
	pshufb	LCPI1_0, %xmm0

Old:
_shuf4:
	pextrw	$3, %xmm0, %eax
	movsd	%xmm1, %xmm0
	pextrw	$3, %xmm1, %ecx
	pinsrw	$4, %ecx, %xmm0
	pinsrw	$5, %eax, %xmm0

========

New:
_shuf1:
	pushl	%ebx
	pushl	%edi
	pushl	%esi
	pextrw	$1, %xmm0, %eax
	rolw	$8, %ax
	movd	%xmm0, %ecx
	rolw	$8, %cx
	pextrw	$5, %xmm0, %edx
	pextrw	$4, %xmm0, %esi
	pextrw	$3, %xmm0, %edi
	pextrw	$2, %xmm0, %ebx
	movaps	%xmm0, %xmm1
	pinsrw	$0, %ecx, %xmm1
	pinsrw	$1, %eax, %xmm1
	rolw	$8, %bx
	pinsrw	$2, %ebx, %xmm1
	rolw	$8, %di
	pinsrw	$3, %edi, %xmm1
	rolw	$8, %si
	pinsrw	$4, %esi, %xmm1
	rolw	$8, %dx
	pinsrw	$5, %edx, %xmm1
	pextrw	$7, %xmm0, %eax
	rolw	$8, %ax
	movaps	%xmm1, %xmm0
	pinsrw	$7, %eax, %xmm0
	popl	%esi
	popl	%edi
	popl	%ebx
	ret

Old:
_shuf1:
	subl	$252, %esp
	movaps	%xmm0, (%esp)
	movaps	%xmm0, 16(%esp)
	movaps	%xmm0, 32(%esp)
	movaps	%xmm0, 48(%esp)
	movaps	%xmm0, 64(%esp)
	movaps	%xmm0, 80(%esp)
	movaps	%xmm0, 96(%esp)
	movaps	%xmm0, 224(%esp)
	movaps	%xmm0, 208(%esp)
	movaps	%xmm0, 192(%esp)
	movaps	%xmm0, 176(%esp)
	movaps	%xmm0, 160(%esp)
	movaps	%xmm0, 144(%esp)
	movaps	%xmm0, 128(%esp)
	movaps	%xmm0, 112(%esp)
	movzbl	14(%esp), %eax
	movd	%eax, %xmm1
	movzbl	22(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	42(%esp), %eax
	movd	%eax, %xmm1
	movzbl	50(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm1, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	77(%esp), %eax
	movd	%eax, %xmm1
	movzbl	84(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	104(%esp), %eax
	movd	%eax, %xmm1
	punpcklbw	%xmm1, %xmm0
	punpcklbw	%xmm2, %xmm0
	movaps	%xmm0, %xmm1
	punpcklbw	%xmm3, %xmm1
	movzbl	127(%esp), %eax
	movd	%eax, %xmm0
	movzbl	135(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	155(%esp), %eax
	movd	%eax, %xmm0
	movzbl	163(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm0, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	188(%esp), %eax
	movd	%eax, %xmm0
	movzbl	197(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	217(%esp), %eax
	movd	%eax, %xmm4
	movzbl	225(%esp), %eax
	movd	%eax, %xmm0
	punpcklbw	%xmm4, %xmm0
	punpcklbw	%xmm2, %xmm0
	punpcklbw	%xmm3, %xmm0
	punpcklbw	%xmm1, %xmm0
	addl	$252, %esp
	ret

llvm-svn: 65311
 2009-02-23 08:49:38 +00:00
Scott Michel
3f8637305f Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR 
instruction. The class also consolidates the code for detecting constant
splats that's shared across PowerPC and the CellSPU backends (and might be
useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for
generating new BUILD_VECTOR nodes.

llvm-svn: 65296
 2009-02-22 23:36:09 +00:00
Evan Cheng
3ea8bd42f3 Add a note. 
llvm-svn: 65275
 2009-02-22 08:13:45 +00:00
Evan Cheng
4385f393f7 Be bug compatible with gcc by returning MMX values in RAX. 
llvm-svn: 65274
 2009-02-22 08:05:12 +00:00
Evan Cheng
9d9688ec15 Do not consider MMX_MOVD64rr a move instructions. The source register is in GR32, the destination is VR64. They are not compatible. 
llvm-svn: 65273
 2009-02-22 08:04:23 +00:00
Anton Korobeynikov
5df82e3e25 Drop bunch of half-working stuff in the ext_weak linkage support. 
Now we're using one gross, but quite robust hack :) (previous ones
did not work, for example, when ext_weak symbol was used deep inside
constant expression in the initializer).

The proper fix of this problem will require some quite huge asmprinter
changes and that's why was postponed. This fixes PR3629 by the way :)

llvm-svn: 65230
 2009-02-21 11:53:32 +00:00
Bill Wendling
bfc216c45a Make sure this doesn't access .end() too. 
llvm-svn: 65213
 2009-02-21 01:11:36 +00:00
Bill Wendling
96430050a5 Make sure we don't dereference the .end() of the container. 
llvm-svn: 65211
 2009-02-21 01:07:26 +00:00
Bill Wendling
66c3ffa2de Propagate more debug loc infos. This also includes some code cleaning. 
llvm-svn: 65207
 2009-02-21 00:43:56 +00:00
Bill Wendling
09289bc433 We need to propagate the debug location information even when dealing with the 
prologue/epilogue.

llvm-svn: 65206
 2009-02-21 00:32:08 +00:00
Evan Cheng
c40c3e28f7 Support return of MMX values in 64-bit mode. 
llvm-svn: 65152
 2009-02-20 20:43:02 +00:00
Bill Wendling
306b992133 Put code that generates debug labels into TableGen so that it can be used by 
everyone.

llvm-svn: 64978
 2009-02-18 23:12:06 +00:00
Nate Begeman
5e78e558ff Add support to the JIT for true non-lazy operation. When a call to a function 
that has not been JIT'd yet, the callee is put on a list of pending functions
to JIT.  The call is directed through a stub, which is updated with the address
of the function after it has been JIT'd.  A new interface for allocating and
updating empty stubs is provided.

Add support for removing the ModuleProvider the JIT was created with, which
would otherwise invalidate the JIT's PassManager, which is initialized with the
ModuleProvider's Module.

Add support under a new ExecutionEngine flag for emitting the infomration 
necessary to update Function and GlobalVariable stubs after JITing them, by
recording the address of the stub and the name of the GlobalValue.  This allows
code to be copied from one address space to another, where libraries may live
at different virtual addresses, and have the stubs updated with their new
correct target addresses.

llvm-svn: 64906
 2009-02-18 08:31:02 +00:00
Dan Gohman
9c258bd2ec Factor out the code to add a MachineOperand to a MachineInstrBuilder. 
llvm-svn: 64891
 2009-02-18 05:45:50 +00:00
Evan Cheng
bd63a1f40d GV with null value initializer shouldn't go to BSS if it's meant for a mergeable strings section. Currently it only checks for Darwin. Someone else please check if it should apply to other targets as well. 
llvm-svn: 64877
 2009-02-18 02:19:52 +00:00
Scott Michel
4c5fa6c982 Remove trailing whitespace to reduce later commit patch noise. 
(Note: Eventually, commits like this will be handled via a pre-commit hook that
 does this automagically, as well as expand tabs to spaces and look for 80-col
 violations.)

llvm-svn: 64827
 2009-02-17 22:15:04 +00:00
Chris Lattner
3b67310686 add a horrible note 
llvm-svn: 64719
 2009-02-17 01:16:14 +00:00
Bill Wendling
266c8bc98f --- Merging (from foreign repository) r64714 into '.': 
U    include/llvm/CodeGen/DebugLoc.h
U    lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp

Enable debug location generation at -Os. This goes with the reapplication of the
r63639 patch.

llvm-svn: 64715
 2009-02-17 01:04:54 +00:00
Dan Gohman
856736a187 MachineLICM now handles these cases. 
llvm-svn: 64620
 2009-02-15 23:24:52 +00:00
Dan Gohman
684359ea96 The x86-64 red zone is now being used. 
llvm-svn: 64535
 2009-02-14 03:30:05 +00:00
Evan Cheng
9041a71923 Teach x86 target -soft-float. 
llvm-svn: 64496
 2009-02-13 22:36:38 +00:00
Dale Johannesen
560b03bbcd Remove non-DebugLoc versions of BuildMI from X86. 
There were some that might even matter in X86FastISel.

llvm-svn: 64437
 2009-02-13 02:33:27 +00:00
Bill Wendling
40e4b271af Revert this. It was breaking stuff. 
llvm-svn: 64428
 2009-02-13 02:16:35 +00:00
Bill Wendling
83b6edd760 Turn off the old way of handling debug information in the code generator. Use 
the new way, where all of the information is passed on SDNodes and machine
instructions.

llvm-svn: 64427
 2009-02-13 02:01:04 +00:00
Dale Johannesen
5a21722625 Eliminate a couple of non-DebugLoc BuildMI variants. 
Modify callers.

llvm-svn: 64409
 2009-02-12 23:08:38 +00:00
Dale Johannesen
47321cf01f Arrange to print constants that match "n" and "i" constraints 
in inline asm as signed (what gcc does).  Add partial support
for x86-specific "e" and "Z" constraints, with appropriate
signedness for printing.

llvm-svn: 64400
 2009-02-12 20:58:09 +00:00
Chris Lattner
1174b80823 fix the X86 backend to just drop llvm.declare nodes for VLAs instead of 
leaving them in the DAG and then getting selection errors.  This is a 
fix for PR3538.

llvm-svn: 64382
 2009-02-12 17:33:11 +00:00
Bill Wendling
49baa5465c Propagate DebugLoc info for spiller call-backs. 
llvm-svn: 64329
 2009-02-11 21:51:19 +00:00
Dan Gohman
2decb4495d Don't try to set an EFLAGS operand to dead if no instruction was created. 
This fixes a bug introduced by r61215.

llvm-svn: 64316
 2009-02-11 19:50:24 +00:00
Evan Cheng
cdb35e3f0f Handle llvm.x86.sse2.maskmov.dqu in 64-bit. 
llvm-svn: 64240
 2009-02-10 22:06:28 +00:00
Evan Cheng
a1b9cf3143 80 col violations. 
llvm-svn: 64237
 2009-02-10 21:39:44 +00:00
Evan Cheng
3b84024598 Implement FpSET_ST1_*. 
llvm-svn: 64186
 2009-02-09 23:32:07 +00:00
Dan Gohman
548d7c9145 Use doxygen comment syntax. 
llvm-svn: 64150
 2009-02-09 18:12:09 +00:00
Evan Cheng
9dc1507838 Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty 
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.

llvm-svn: 64124
 2009-02-09 07:14:22 +00:00
Chris Lattner
a50a554333 add a note. 
llvm-svn: 64093
 2009-02-08 20:44:19 +00:00
Dale Johannesen
b22cb23f6f Use getDebugLoc forwarder instead of getNode()->getDebugLoc. 
No functional change.

llvm-svn: 64026
 2009-02-07 19:59:05 +00:00
Dan Gohman
4105a38248 Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing 
ScheduleDAG's TLI member to use const.

llvm-svn: 64018
 2009-02-07 16:15:20 +00:00
Dale Johannesen
a259483aae Get rid of the last non-DebugLoc versions of getNode! 
Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base.  There's no
sensible way to associate debug info with these.  I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands. 
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.

llvm-svn: 63992
 2009-02-07 00:55:49 +00:00
Dan Gohman
8437b9efa1 Refactor some repeated logic into a separate function. 
llvm-svn: 63989
 2009-02-07 00:43:41 +00:00
Dan Gohman
8aeae15ebd Make a comment a doxygen comment. 
llvm-svn: 63988
 2009-02-07 00:42:54 +00:00
Dale Johannesen
1580ab6b7f Remove more non-DebugLoc getNode variants. Use 
getCALLSEQ_{END,START} to permit passing no DebugLoc
there.  UNDEF doesn't logically have DebugLoc; add
getUNDEF to encapsulate this.

llvm-svn: 63978
 2009-02-06 23:05:02 +00:00
Dale Johannesen
c405486235 Remove more non-DebugLoc versions of getNode. 
llvm-svn: 63969
 2009-02-06 21:50:26 +00:00
Bill Wendling
2c7f47d1d4 Record debug location information in the Dwarf writer. 
A simple test program shows that debugging works. :-)

llvm-svn: 63968
 2009-02-06 21:45:08 +00:00
Dan Gohman
a2f300f26d Use .size and .type on ELF systems; this helps tools that map 
addresses to symbols.

llvm-svn: 63962
 2009-02-06 21:15:52 +00:00
Evan Cheng
e00df1d39c Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo. 
llvm-svn: 63938
 2009-02-06 17:43:24 +00:00
Evan Cheng
381b2df5ff Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook. 
llvm-svn: 63936
 2009-02-06 17:17:30 +00:00
Dale Johannesen
e95c76b65e Get rid of one more non-DebugLoc getNode and 
its corresponding getTargetNode.  Lots of
caller changes.

llvm-svn: 63904
 2009-02-06 01:31:28 +00:00
Evan Cheng
87def37f67 A few more isAsCheapAsAMove. 
llvm-svn: 63852
 2009-02-05 08:42:55 +00:00
Dale Johannesen
15a801f11d Remove non-DebugLoc versions of getLoad and getStore. 
Adjust the many callers of those versions.

llvm-svn: 63767
 2009-02-04 20:06:27 +00:00
Chris Lattner
feb6b56242 Bill implemented this. 
llvm-svn: 63752
 2009-02-04 19:09:07 +00:00
Chris Lattner
eae4653469 add a note, this is why we're faster at SciMark-MonteCarlo with 
SSE disabled.

llvm-svn: 63751
 2009-02-04 19:08:01 +00:00
Dan Gohman
1cd89d625c Minor code cleanups; no functionality change. 
llvm-svn: 63740
 2009-02-04 17:28:58 +00:00
Mon P Wang
430525dc4f Fixes a case where we generate an incorrect mask for pshfhw in the presence 
of undefs and incorrectly determining if we have punpckldq.

llvm-svn: 63702
 2009-02-04 01:16:59 +00:00
Dale Johannesen
fa244d6e2d Patch up omissions in DebugLoc propagation. 
llvm-svn: 63693
 2009-02-04 00:33:20 +00:00
Dale Johannesen
f9b2746030 Need this file too. 
llvm-svn: 63674
 2009-02-03 22:26:34 +00:00
Dale Johannesen
b7f2857776 Add some DL propagation to places that didn't 
have it yet.  More coming.

llvm-svn: 63673
 2009-02-03 22:26:09 +00:00
Dale Johannesen
45009f127b DebugLoc propgation 
llvm-svn: 63664
 2009-02-03 21:48:12 +00:00
Dale Johannesen
358418bb3d DebugLoc propagation. done with file. 
llvm-svn: 63656
 2009-02-03 20:21:25 +00:00
Dale Johannesen
6c8c315519 DebugLoc propagation. 2/3 through file. 
llvm-svn: 63650
 2009-02-03 19:33:06 +00:00
Dan Gohman
7d19e6cd6d Tevert part of the x86 subtarget logic changes: when -march=x86-64 
is given, override the subtarget settings and enable 64-bit support.
This restores the earlier behavior, and fixes regressions on
Non-64-bit-capable x86-32 hosts.

This isn't necessarily the best approach, but the most obvious
alternative is to require -mcpu=x86-64 or -mattr=+64bit to be used
with -march=x86-64 when the host doesn't have 64-bit support. This
makes things little more consistent, but it's less convenient, and
it has the practical drawback of requiring lots of test changes, so
I opted for the above approach for now.

llvm-svn: 63642
 2009-02-03 18:53:21 +00:00
Bill Wendling
5b177df8e9 Create DebugLoc information in FastISel. Several temporary methods were 
created. Specifically, those BuildMIs which use
"DebugLoc::getUnknownLoc()". I'll remove them soon.

llvm-svn: 63584
 2009-02-03 00:55:04 +00:00
Dan Gohman
2170150035 Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has 
SSE2, however it's possible to disable SSE2, and the subtarget support
code thinks that if 64-bit implies SSE2 and SSE2 is disabled then
64-bit should also be disabled. Instead, just mark all the 64-bit
subtargets as explicitly supporting SSE2.

Also, move the code that makes -march=x86-64 enable 64-bit support by
default to only apply when there is no explicit subtarget. If you
need to specify a subtarget and you want 64-bit code, you'll need to
select a subtarget that supports 64-bit code.

llvm-svn: 63575
 2009-02-03 00:04:43 +00:00
Torok Edwin
2bc41a36ba Only force SSE level if it is not correct. 
Add an assert to check HasX86_64 status.

llvm-svn: 63552
 2009-02-02 21:57:34 +00:00
Torok Edwin
c1017185a5 remove #if 0 code on Bill's request. 
llvm-svn: 63542
 2009-02-02 20:23:02 +00:00
Evan Cheng
16c8f917fb ADD / SUB / SMUL / UMUL with overflow second result top bits must be zero. 
llvm-svn: 63509
 2009-02-02 09:15:04 +00:00
Evan Cheng
e8dfbb5884 Add comment. 
llvm-svn: 63506
 2009-02-02 08:19:07 +00:00
Evan Cheng
483bbd1643 Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow. 
llvm-svn: 63505
 2009-02-02 08:07:36 +00:00
Torok Edwin
b4c9a6097f Implement -mno-sse: if SSE is disabled on x86-64, don't store XMM on stack for 
var-args, and don't allow FP return values

llvm-svn: 63495
 2009-02-01 18:15:56 +00:00
Duncan Sands
cac6cf74f9 Fix PR3453 and probably a bunch of other potential 
crashes or wrong code with codegen of large integers:
eliminate the legacy getIntegerVTBitMask and
getIntegerVTSignBit methods, which returned their
value as a uint64_t, so couldn't handle huge types.

llvm-svn: 63494
 2009-02-01 18:06:53 +00:00
Dale Johannesen
39738b1ff8 Make LowerCallTo and LowerArguments take a DebugLoc 
argument.  Adjust all callers and overloaded versions.

llvm-svn: 63444
 2009-01-30 23:10:59 +00:00
Bill Wendling
67737da99b Get rid of the non-DebugLoc-ified getNOT() method. 
llvm-svn: 63442
 2009-01-30 23:03:19 +00:00
Mon P Wang
5db99442e4 When PerformBuildVectorCombine, avoid creating a X86ISD::VZEXT_LOAD of 
an illegal type.

llvm-svn: 63380
 2009-01-30 07:07:40 +00:00
Dan Gohman
9d120d6d8f Make x86's BT instruction matching more thorough, and add some 
dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.

llvm-svn: 63266
 2009-01-29 01:59:02 +00:00
Mon P Wang
8abb07a527 Fixed lowering of v816 shuffles. 
llvm-svn: 63252
 2009-01-28 23:11:14 +00:00
Duncan Sands
aee16d4916 Rename getAnalysisToUpdate to getAnalysisIfAvailable. 
llvm-svn: 63198
 2009-01-28 13:14:17 +00:00
Evan Cheng
2a965124b7 The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement. 
llvm-svn: 63195
 2009-01-28 08:35:02 +00:00
Mon P Wang
e1c886f775 Add shuffle splat pattern for x86 sse shifts. 
llvm-svn: 63193
 2009-01-28 08:12:05 +00:00
Dan Gohman
c017343459 Reformat the allocation-order arrays to a more conventional style. 
llvm-svn: 63121
 2009-01-27 19:25:38 +00:00
Dan Gohman
7d80f8688e Simplify findNonImmUse; return the result using the return value 
instead of via a by-reference argument. No functionality change.

llvm-svn: 63118
 2009-01-27 19:04:30 +00:00
Evan Cheng
a05436f739 Implement multiple with overflow by 2 with an add instruction. 
llvm-svn: 63090
 2009-01-27 03:30:42 +00:00
Dan Gohman
2e0343e321 Eliminate unnecessary operands-list traversals. 
llvm-svn: 63088
 2009-01-27 02:37:43 +00:00
Dan Gohman
4ad174b236 Fix the Red Zone calculation for functions with frame pointers. 
Don't use the Red Zone when dynamic stack realignment is needed.
This could be implemented, but most x86-64 ABIs don't require
dynamic stack realignment so it isn't urgent.

llvm-svn: 63074
 2009-01-27 00:40:06 +00:00
Dan Gohman
3a51d8e847 Implement Red Zone utilization on x86-64. This is currently 
disabled by default; I'll enable it when I hook it up with
the llvm-gcc flag which controls it.

llvm-svn: 63056
 2009-01-26 22:22:31 +00:00
Evan Cheng
ec03e0cd3b Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start. 
llvm-svn: 63022
 2009-01-26 18:43:34 +00:00
Dan Gohman
4abaebae0c Take the next steps in making SDUse more consistent with LLVM Use, and 
tidy up SDUse and related code.
 - Replace the operator= member functions with a set method, like
   LLVM Use has, and variants setInitial and setNode, which take
   care up updating use lists, like LLVM Use's does. This simplifies
   code that calls these functions.
 - getSDValue() is renamed to get(), as in LLVM Use, though most
   places can either use the implicit conversion to SDValue or the
   convenience functions instead.
 - Fix some more node vs. value terminology issues.

Also, eliminate the one remaining use of SDOperandPtr, and
SDOperandPtr itself.

llvm-svn: 62995
 2009-01-26 04:35:06 +00:00
Nate Begeman
d2f708eca5 De-identifying per sabre review 
llvm-svn: 62988
 2009-01-26 03:15:31 +00:00
Nate Begeman
92efc4f0ce Map address space 256 to gs; similar mappings could be supported for the 
other x86 segments.  address space 0 is stack/default, 1-255 are reserved for
client use.

llvm-svn: 62980
 2009-01-26 01:24:32 +00:00
Nate Begeman
81d70f3f54 Support pattern matching various x86 sse shifts. 
llvm-svn: 62979
 2009-01-26 00:52:55 +00:00
Torok Edwin
6f715ebe85 should have removed the + when manually applying a patch! 
llvm-svn: 62973
 2009-01-25 20:29:34 +00:00
Torok Edwin
3f54410405 revert this patch for now, because Codegen does still want to generate SSE code, 
for example in the case of va-args. XFAIL associated tests.

llvm-svn: 62972
 2009-01-25 20:21:24 +00:00
Torok Edwin
49b1d3e3cc If user explicitly asks not to use SSE, don't force it. This fixes LLVM part of PR3402. 
llvm-svn: 62967
 2009-01-25 17:58:56 +00:00
Nate Begeman
48f3fe9199 Fix an indent and a typo. 
llvm-svn: 62940
 2009-01-24 22:12:48 +00:00
Chris Lattner
97b6f6a674 hopefully address PR3379 by making the P modifier work in x86 inline asm. 
llvm-svn: 62887
 2009-01-23 22:33:40 +00:00
Bob Wilson
186046e657 Add SelectionDAG::getNOT method to construct bitwise NOT operations, 
corresponding to the "not" and "vnot" PatFrags.  Use the new method
in some places where it seems appropriate.

llvm-svn: 62768
 2009-01-22 17:39:32 +00:00
Evan Cheng
c971801ae1 Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. 
llvm-svn: 62762
 2009-01-22 09:10:11 +00:00
Dan Gohman
29b575c6cd Recognize inline asm for bswap on x86-64 GLIBC. This allows it 
to be supported in the JIT.

llvm-svn: 62730
 2009-01-21 23:40:54 +00:00
Evan Cheng
43d680b0d8 Also favors NOT64r. 
llvm-svn: 62710
 2009-01-21 19:45:31 +00:00
Dan Gohman
704f0d5879 Fix a recent regression. ClrOpcode is not set for i8; for i8, if 
we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.

llvm-svn: 62691
 2009-01-21 14:50:16 +00:00
Evan Cheng
0ed6a9d7e0 Favors generating "not" over "xor -1". For example. 
unsigned test(unsigned a) {
  return ~a;
}
llvm used to generate:
movl    $4294967295, %eax
xorl    4(%esp), %eax

Now it generates:
movl      4(%esp), %eax
notl      %eax

It's 3 bytes shorter.

llvm-svn: 62661
 2009-01-21 02:09:05 +00:00
Evan Cheng
b3c82db63d Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. 
llvm-svn: 62600
 2009-01-20 19:12:24 +00:00
Evan Cheng
06cfade044 DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it. 
llvm-svn: 62519
 2009-01-19 19:06:11 +00:00
Evan Cheng
a14fd26a8b Minor tweak to LowerUINT_TO_FP_i32. Bias (after scalar_to_vector) has two uses so we should make it the second source operand of ISD::OR so 2-address pass won't have to be smart about commuting. 
%reg1024<def> = MOVSDrm %reg0, 1, %reg0, <cp#0>, Mem:LD(8,8) [ConstantPool + 0]
%reg1025<def> = MOVSD2PDrr %reg1024
%reg1026<def> = MOVDI2PDIrm <fi#-1>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack-1 + 0]
%reg1027<def> = ORPSrr %reg1025<kill>, %reg1026<kill>
%reg1028<def> = MOVPD2SDrr %reg1027<kill>
%reg1029<def> = SUBSDrr %reg1028<kill>, %reg1024<kill>
%reg1030<def> = CVTSD2SSrr %reg1029<kill>
MOVSSmr <fi#0>, 1, %reg0, 0, %reg1030<kill>, Mem:ST(4,4) [FixedStack0 + 0]
%reg1031<def> = LD_Fp32m80 <fi#0>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack0 + 0]
RET %reg1031<kill>, %ST0<imp-use,kill>

The reason 2-addr pass isn't smart enough to commute the ORPSrr is because it can't look pass the MOVSD2PDrr instruction.

llvm-svn: 62505
 2009-01-19 08:19:57 +00:00
Evan Cheng
53e83a2eb9 Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 
optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself.

llvm-svn: 62504
 2009-01-19 08:08:22 +00:00
Bill Wendling
ce30a8cab9 Extend thi 
llvm-svn: 62415
 2009-01-17 07:40:19 +00:00
Evan Cheng
182d9c4c9f Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode. 
llvm-svn: 62413
 2009-01-17 07:09:27 +00:00
Bill Wendling
ddd55bdfec Temporarily revert my last change. It is causing a bootstrap failure. 
llvm-svn: 62405
 2009-01-17 04:23:51 +00:00
Bill Wendling
d18c38c0f2 Implement a special algorithm for converting uint_to_fp for i32 values on 
X86. This code:

void f() {
  uint32_t x;
  float y = (float)x;
}

used to be:

     movl     %eax, -8(%ebp)
     movl     [2^52 double], -4(%ebp)
     movsd    -8(%ebp), %xmm0
     subsd    [2^52 double], %xmm0
     cvtsd2ss %xmm0, %xmm0

Is now:

   movsd        [2^52 double], %xmm0
   movsd        %xmm0, %xmm1
   movd         %ecx, %xmm2
   orps         %xmm2, %xmm1
   subsd        %xmm0, %xmm1
   cvtsd2ss     %xmm1, %xmm0

This is faster on X86. Note that there's an extra load of %xmm0 into %xmm1. That
will be fixed in a later coalescer fix.

llvm-svn: 62404
 2009-01-17 03:56:04 +00:00
Bill Wendling
c9e856fbfd Add support for non-zero __builtin_return_address values on X86. 
llvm-svn: 62338
 2009-01-16 19:25:27 +00:00
Mon P Wang
4cfe965df2 Expand insert/extract of a <4 x i32> with a variable index. 
llvm-svn: 62281
 2009-01-15 21:10:20 +00:00
Rafael Espindola
0aba6c9435 Add the private linkage. 
llvm-svn: 62279
 2009-01-15 20:18:42 +00:00
Dan Gohman
6fcee67989 Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph 
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.

To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.

llvm-svn: 62275
 2009-01-15 19:20:50 +00:00
Dan Gohman
0b06dcbf4b Add load-folding table entries for BT*ri8 instructions. 
llvm-svn: 62267
 2009-01-15 17:57:09 +00:00
Dan Gohman
37d7b5be33 Make getWidenVectorType const. 
llvm-svn: 62265
 2009-01-15 17:34:08 +00:00
Dan Gohman
6f5847ccfc BT appears to be available on all >= i386 chips. 
llvm-svn: 62196
 2009-01-13 23:27:15 +00:00
Dan Gohman
9c2ee40c1c Don't use a BT instruction if the AND has multiple uses. 
llvm-svn: 62195
 2009-01-13 23:25:30 +00:00
Dan Gohman
8c835f6285 Disable the register+memory forms of the bt instructions for now. Thanks 
to Eli for pointing out that these forms don't ignore the high bits of
their index operands, and as such are not immediately suitable for use
by isel.

llvm-svn: 62194
 2009-01-13 23:23:30 +00:00
Dan Gohman
15e69a394a Add bt instructions that take immediate operands. 
llvm-svn: 62180
 2009-01-13 20:33:23 +00:00
Dan Gohman
e84cfeac5f Fix a few more JIT encoding issues in the BT instructions. 
llvm-svn: 62179
 2009-01-13 20:32:45 +00:00
Devang Patel
eed0505ed8 Use DebugInfo interface to lower dbg_* intrinsics. 
llvm-svn: 62127
 2009-01-13 00:35:13 +00:00
Duncan Sands
bcdbfb63dc Rename getABITypeSize to getTypePaddedSize, as 
suggested by Chris.

llvm-svn: 62099
 2009-01-12 20:38:59 +00:00
Evan Cheng
ce292ad389 80 col violation. 
llvm-svn: 62024
 2009-01-10 03:33:22 +00:00
Misha Brukman
71c7e40966 Removed trailing whitespace from Makefiles. 
llvm-svn: 61991
 2009-01-09 16:44:42 +00:00
Dan Gohman
a487b137a8 Add load-folding table entries for MOVDQA. 
llvm-svn: 61972
 2009-01-09 02:40:34 +00:00
Dan Gohman
0e86745357 Whitespace and other minor adjustments to make SSE instructions have 
the same formatting as their corresponding SSE2 instructions, for
consistency.

llvm-svn: 61971
 2009-01-09 02:27:34 +00:00
Devang Patel
747d4b38ad Convert DwarfWriter into a pass. 
Now Users request DwarfWriter through getAnalysisUsage() instead of creating an instance of DwarfWriter object directly.

llvm-svn: 61955
 2009-01-08 23:40:34 +00:00
Dan Gohman
ca4475dd7b Add patterns to match conditional moves with loads folded 
into their left operand, rather than their right. Do this
by commuting the operands and inverting the condition.

llvm-svn: 61842
 2009-01-07 01:00:24 +00:00
Dan Gohman
ab00fbad9d Add load-folding table entries for cmovno too. 
llvm-svn: 61841
 2009-01-07 00:44:53 +00:00
Dan Gohman
e78fdaec67 Define instructions for cmovo and cmovno. 
llvm-svn: 61836
 2009-01-07 00:35:10 +00:00
Dan Gohman
2682e8745c X86_COND_C and X86_COND_NC are alternate mnemonics for 
X86_COND_B and X86_COND_AE, respectively.

llvm-svn: 61835
 2009-01-07 00:15:08 +00:00
Dan Gohman
e033f7c41e Revert r42653 and forward-port the code that lets INC64_32r be 
converted to LEA64_32r in x86's convertToThreeAddress. This
replaces code like this:
   movl  %esi, %edi
   inc   %edi
with this:
   lea   1(%rsi), %edi
which appears to be beneficial.

llvm-svn: 61830
 2009-01-06 23:34:46 +00:00
Bill Wendling
891f9abdbb Revert r61415 and r61484. Duncan was correct that these weren't needed. 
llvm-svn: 61765
 2009-01-05 22:53:45 +00:00
Dan Gohman
8271066844 Tidy up #includes, deleting a bunch of unnecessary #includes. 
llvm-svn: 61715
 2009-01-05 17:59:02 +00:00
Devang Patel
689e130117 squash warnings. 
llvm-svn: 61707
 2009-01-05 17:31:22 +00:00
Evan Cheng
d2ffa1f122 Atom and Core i7 do not have same model number after all. 
llvm-svn: 61686
 2009-01-05 08:45:01 +00:00
Evan Cheng
540a7a5e9b Add Intel processors core i7 and atom. 
llvm-svn: 61603
 2009-01-03 04:24:44 +00:00
Evan Cheng
c477e19c19 Fix PR3210: Detect more Intel processors. Patch by Torok Edwin. 
llvm-svn: 61602
 2009-01-03 04:04:46 +00:00
Evan Cheng
c52f942d67 Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. 
llvm-svn: 61557
 2009-01-02 05:35:45 +00:00
Evan Cheng
f460ec040c Fix x86 CPU id detection to identify Penryn (and future processors). 
llvm-svn: 61556
 2009-01-02 05:29:20 +00:00
Evan Cheng
57115c1887 Use movaps / movd to extract vector element 0 even with sse4.1. It's still cheaper than pextrw especially if the value is in memory. 
llvm-svn: 61555
 2009-01-02 05:29:08 +00:00
Duncan Sands
190d6bc636 Fix PR3274: when promoting the condition of a BRCOND node, 
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType.  In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).

llvm-svn: 61542
 2009-01-01 15:52:00 +00:00
Bill Wendling
067c48f7a6 Linux wants the FDE initial location and address range to be forced to 32-bit. 
Darwin doesn't. Make this optional for platforms.

llvm-svn: 61484
 2008-12-29 22:12:11 +00:00
Chris Lattner
fde038935b Add a simple pattern for matching 'bt'. 
llvm-svn: 61426
 2008-12-25 05:34:37 +00:00
Chris Lattner
062ed6e3dd Fix some JIT encodings. 
llvm-svn: 61425
 2008-12-25 01:32:49 +00:00
Chris Lattner
f34b843728 BT memory operands load from their address operand. 
llvm-svn: 61424
 2008-12-25 01:27:10 +00:00
Chris Lattner
e9229dc899 translateX86CC can never fail. Simplify it based on this. 
llvm-svn: 61423
 2008-12-24 23:53:05 +00:00
Bill Wendling
044248aad1 Darwin likes for the EH frame to be non-local. 
llvm-svn: 61420
 2008-12-24 08:05:17 +00:00
Bill Wendling
6add893a14 GCC doesn't emit DW_EH_PE_sdata4 for the FDE encoding on Darwin. I'm not sure 
about other platforms.

llvm-svn: 61415
 2008-12-24 05:25:49 +00:00
Dan Gohman
7ff343fe6c Fix a compiler-abort on a testcase where the stack-pointer is added to 
a symbolic constant. This is unlikely to be intentional, but it
shouldn't crash the compiler.

llvm-svn: 61408
 2008-12-24 00:27:51 +00:00
Chris Lattner
ca08c532f7 indentation 
llvm-svn: 61407
 2008-12-24 00:11:37 +00:00
Chris Lattner
c20dd60a21 simplify some control flow and reduce indentation, no functionality change. 
llvm-svn: 61404
 2008-12-23 23:42:27 +00:00
Dan Gohman
1ba93ac6be Add instruction patterns and encodings for the x86 bt instructions. 
llvm-svn: 61400
 2008-12-23 22:45:23 +00:00
Devang Patel
d4aebdfa3f Silence unused variable warnings. 
llvm-svn: 61392
 2008-12-23 21:56:28 +00:00
Dan Gohman
a0f1fc06c4 Clean up the atomic opcodes in SelectionDAG. 
This removes all the _8, _16, _32, and _64 opcodes and replaces each
group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode
is now used to carry the size information. In tablegen, the size-specific
opcodes are replaced by size-independent opcodes that utilize the
ability to compose them with predicates.

This shrinks the per-opcode tables and makes the code that handles
atomics much more concise.

llvm-svn: 61389
 2008-12-23 21:37:04 +00:00
Mon P Wang
7b9b2770bb Fixed code generation for v8i16 and v16i8 splats on X86. 
Fixed lowering of v8i16 shuffles for v8i16 when we fall back to extract/insert.

llvm-svn: 61365
 2008-12-23 04:03:27 +00:00
Dan Gohman
faf474af38 Make the fuse-failed debug output human-readable. 
llvm-svn: 61356
 2008-12-23 00:19:20 +00:00
Dan Gohman
c9f244842c Fix fast-isel to not emit invalid assembly when presented with a 
constant shift count that doesn't fit in the shift instruction's
immediate field. This fixes PR3242.

llvm-svn: 61281
 2008-12-20 17:19:40 +00:00
Dan Gohman
22b7b328a4 Move the patterns which have i8 immediates before the patterns 
that have i32 immediates so that they get selected first. This
currently only matters in the JIT, as assemblers will
automatically use the smallest encoding.

llvm-svn: 61250
 2008-12-19 18:25:21 +00:00
Chris Lattner
27c3b1df00 Fix some release-assert warnings 
llvm-svn: 61244
 2008-12-19 17:03:38 +00:00
Rafael Espindola
7593f0004f Fix bug 3202. 
The EH_frame and .eh symbols are now private, except for darwin9 and earlier.
The patch also fixes the definition of PrivateGlobalPrefix on pcc linux.

llvm-svn: 61242
 2008-12-19 10:55:56 +00:00
Dan Gohman
1c74326cea When emitting instructions that define EFLAGS and the EFLAGS value isn't 
used, mark the defs as dead.

llvm-svn: 61215
 2008-12-18 22:03:42 +00:00
Dan Gohman
54790143b2 When setting up the frame pointer, add it as a live-in register to all 
non-entry blocks, so that it doesn't appear use-before-def anywhere.

llvm-svn: 61214
 2008-12-18 22:01:52 +00:00
Mon P Wang
9f8945c5b9 Fixed x86 code generation of multiple for v2i64. It was incorrect for SSE4.1. 
llvm-svn: 61211
 2008-12-18 21:42:19 +00:00
Dan Gohman
fb30c38893 Mark the x86 fp stack registers as "reserved". This tells LiveVariables 
and the RegisterScavenger not to expect traditional liveness 
techniques are applicable to these registers, since we don't fully
modify the effects of push and pop after stackification.

llvm-svn: 61179
 2008-12-18 01:05:09 +00:00
Dan Gohman
c3e24d559b Add initial support for back-scheduling address computations, 
especially in the case of addresses computed from loop induction
variables.

llvm-svn: 61075
 2008-12-16 03:35:01 +00:00
Bill Wendling
13e4a3d0b0 - Use patterns instead of creating completely new instruction matching patterns, 
which are identical to the original patterns.

- Change the multiply with overflow so that we distinguish between signed and
  unsigned multiplication. Currently, unsigned multiplication with overflow
  isn't working!

llvm-svn: 60963
 2008-12-12 21:15:41 +00:00
Mon P Wang
53d0c96c6f Added support for SELECT v8i8 v4i16 for X86 (MMX) 
Added support for TRUNC v8i16 to v8i8 for X86 (MMX)

llvm-svn: 60916
 2008-12-12 01:25:51 +00:00
Bill Wendling
5d026e47c1 Redo the arithmetic with overflow architecture. I was changing the semantics of 
ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace
the intrinsic with an ISD::SADDO node. Then custom lower that into an
X86ISD::ADD node with a associated SETCC that checks the correct condition code
(overflow or carry). Then that gets lowered into the correct X86::ADDOvf
instruction.

Similar for SUB and MUL instructions.

llvm-svn: 60915
 2008-12-12 00:56:36 +00:00
Evan Cheng
487c9ff802 Some code clean up. 
llvm-svn: 60850
 2008-12-10 21:49:05 +00:00
Bill Wendling
417d88be16 Only perform SETO/SETC to JO/JC conversion if extractvalue is coming from an arithmetic with overflow instruction. 
llvm-svn: 60844
 2008-12-10 19:44:24 +00:00
Evan Cheng
caa31a82fc Fix MachineCodeEmitter to use uintptr_t instead of intptr_t. This avoids some overflow issues. Patch by Thomas Jablin. 
llvm-svn: 60828
 2008-12-10 02:32:19 +00:00
Bill Wendling
d33b6dfd4f Whitespace changes. 
llvm-svn: 60826
 2008-12-10 02:01:32 +00:00
Bill Wendling
1c1dacdd42 Implement fast-isel conversion of a branch instruction that's branching on an 
overflow/carry from the "arithmetic with overflow" intrinsics. It searches the
machine basic block from bottom to top to find the SETO/SETC instruction that is
its conditional. If an instruction modifies EFLAGS before it reaches the
SETO/SETC instruction, then it defaults to the normal instruction emission.

llvm-svn: 60807
 2008-12-09 23:19:12 +00:00
Bill Wendling
4c8fb3a0cc Add sub/mul overflow intrinsics. This currently doesn't have a 
target-independent way of determining overflow on multiplication. It's very
tricky. Patch by Zoltan Varga!

llvm-svn: 60800
 2008-12-09 22:08:41 +00:00
Bill Wendling
d034543c7e Correct my English. 
llvm-svn: 60753
 2008-12-09 07:55:31 +00:00
Bill Wendling
7250a29def Add initial support for fast-isel of the [SU]ADDO intrinsics. It isn't 
complete. For instance, it lowers the common case into this less-than-optimal
code:

        addl    %ecx, %eax
        seto    %cl
        testb   %cl, %cl
        jne     LBB1_2  ## overflow

instead of:

        addl    %ecx, %eax
        jo      LBB1_2  ## overflow

That will come in a future commit.

llvm-svn: 60737
 2008-12-09 02:42:50 +00:00
Dan Gohman
9e5cc22129 Fix a couple of mistaken switch case fall-throughs. Thanks to Bill 
for spotting these!

llvm-svn: 60728
 2008-12-08 23:50:06 +00:00
Evan Cheng
3bb2ad8a0a Re-apply 60689 now my head is screwed on right. 
llvm-svn: 60711
 2008-12-08 19:29:03 +00:00
Dan Gohman
5bca97fc4f Revert 60689. It caused many regressions on Darwin targets. 
llvm-svn: 60705
 2008-12-08 17:38:02 +00:00
Dan Gohman
14d4094968 Factor out the code for sign-extending/truncating gep indices 
and use it in x86 address mode folding. Also, make
getRegForValue return 0 for illegal types even if it has a
ValueMap for them, because Argument values are put in the
ValueMap. This fixes PR3181.

llvm-svn: 60696
 2008-12-08 07:57:47 +00:00
Evan Cheng
d668dd83c0 Perform cheap checks first. 
llvm-svn: 60689
 2008-12-08 06:52:43 +00:00
Nick Lewycky
e277f75880 Fix typo, psuedo -> pseudo. 
llvm-svn: 60651
 2008-12-07 03:49:52 +00:00
Chris Lattner
00104cf8f8 add a note 
llvm-svn: 60632
 2008-12-06 22:49:05 +00:00
Dale Johannesen
c6404f98b2 Forgot a file. 
llvm-svn: 60609
 2008-12-05 21:55:35 +00:00
Dale Johannesen
f5a072c388 Make LoopStrengthReduce smarter about hoisting things out of 
loops when they can be subsumed into addressing modes.

Change X86 addressing mode check to realize that
some PIC references need an extra register.
(I believe this is correct for Linux, if not, I'm sure
someone will tell me.)

llvm-svn: 60608
 2008-12-05 21:47:27 +00:00
Evan Cheng
03ef7cf749 Reason #3 from 60595 doesn't hold true. If we can fold a PIC load from constpool into a use, the rewrite happens at time of spill (not in VirtRegMap). Later on, if the GlobalBaseReg is spilled, the spiller can see the use uses GlobalBaseReg and do the right thing. 
llvm-svn: 60596
 2008-12-05 17:41:31 +00:00
Evan Cheng
144447bfa0 Effectively undo 60461 in PIC mode which simply transform V_SET0 / V_SETALLONES into a load from constpool in order to fold into restores. This is not safe to do when PIC base is being used for a number of reasons: 
1. GlobalBaseReg may have been spilled.
2. It may not be live at the use.
3. Spiller doesn't know this is happening so it won't prevent GlobalBaseReg from being spilled later (That by itself is a nasty hack. It's needed because we don't insert the reload until later).

llvm-svn: 60595
 2008-12-05 17:23:48 +00:00
Evan Cheng
1b795803dd Re-did 60519. It turns out Darwin's handling of hidden visibility symbols are a bit more complicate than I expected. Both declarations and weak definitions still need a stub indirection. However, the stubs are in data section and they contain the addresses of the actual symbols. 
llvm-svn: 60571
 2008-12-05 01:06:39 +00:00
Bill Wendling
a0466523bd Temporarily revert r60519. It was causing a bootstrap failure: 
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -DHAVE_CONFIG_H -I. -I../../../llvm-gcc.src/libgomp -I. -I../../../llvm-gcc.src/libgomp/config/posix -I../../../llvm-gcc.src/libgomp -Wall -pthread -Werror -O2 -g -O2 -MT barrier.lo -MD -MP -MF .deps/barrier.Tpo -c ../../../llvm-gcc.src/libgomp/barrier.c  -fno-common -DPIC -o .libs/barrier.o
checking for sys/file.h... /var/folders/zG/zGE-ZJOGFiGjv0B5cs5oYE+++TM/-Tmp-//cc34Jg5P.s:13:non-relocatable subtraction expression, "_gomp_tls_key" minus "L1$pb"
/var/folders/zG/zGE-ZJOGFiGjv0B5cs5oYE+++TM/-Tmp-//cc34Jg5P.s:13:symbol: "_gomp_tls_key" can't be undefined in a subtraction expression
make[4]: *** [barrier.lo] Error 1
make[4]: *** Waiting for unfinished jobs....
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -DHAVE_CONFIG_H -I. -I../../../llvm-gcc.src/libgomp -I. -I../../../llvm-gcc.src/libgomp/config/posix -I../../../llvm-gcc.src/libgomp -Wall -pthread -Werror -O2 -g -O2 -MT alloc.lo -MD -MP -MF .deps/alloc.Tpo -c ../../../llvm-gcc.src/libgomp/alloc.c -o alloc.o >/dev/null 2>&1
yes
checking for sys/param.h... make[3]: *** [all-recursive] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libgomp] Error 2
make[1]: *** Waiting for unfinished jobs....

llvm-svn: 60527
 2008-12-04 04:07:00 +00:00
Evan Cheng
d4b7459179 Visibility hidden GVs do not require extra load of symbol address from the GOT or non-lazy-ptr. 
llvm-svn: 60519
 2008-12-04 01:56:50 +00:00
Evan Cheng
05ded29738 Use mmx (punpckldq VR64, (mmx_v_set0)) to clear high 32-bits of a VR64 register. 
llvm-svn: 60499
 2008-12-03 19:38:05 +00:00
Dan Gohman
74529a2226 Split foldMemoryOperand into public non-virtual and protected virtual 
parts, and add target-independent code to add/preserve
MachineMemOperands.

llvm-svn: 60488
 2008-12-03 18:43:12 +00:00
Dan Gohman
5dad0993a9 Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. 
llvm-svn: 60487
 2008-12-03 18:15:48 +00:00
Dan Gohman
fc05cdda64 Extend X86's addFrameReference to add a MachineMemOperand for 
the frame reference. This will help post-RA scheduling determine
that spills to distinct stack slots are independent.

llvm-svn: 60486
 2008-12-03 18:11:40 +00:00
Rafael Espindola
0c800cf35e Fix bug 3140. 
Print a single parameter .file directive if we have an ELF target.

llvm-svn: 60480
 2008-12-03 11:01:37 +00:00
Evan Cheng
440e75e1d5 Refactor code. No functionality change. 
llvm-svn: 60478
 2008-12-03 08:38:43 +00:00
Bill Wendling
d2208d570b CC should only be a ConstantSDNode at this point. Just use 'cast' instead of 'dyn_cast'. 
llvm-svn: 60477
 2008-12-03 08:32:02 +00:00
Dan Gohman
ac6561793c Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's 
foldMemoryOperand how to "fold" them, by converting them into constant-pool
loads. When they aren't folded, they use xorps/cmpeqd, but for example when
register pressure is high, they may now be folded as memory operands, which
reduces register pressure.

Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will
remat it instead of copying zeros around (V_SETALLONES was already marked).

llvm-svn: 60461
 2008-12-03 05:21:24 +00:00
Dan Gohman
86b0a220af Fix this comment to reflect that it applies to types other 
than just i32.

llvm-svn: 60455
 2008-12-03 01:39:44 +00:00
Dan Gohman
dcd4896f12 Fix byval arguments in the fastcc calling convention. The fastcc convention 
delegates to the regular x86-32 convention which handles byval, but only
after it handles a few cases, and it's necessary to handle byval before
handling those cases. This fixes PR3122 (and rdar://6400815), llvm-gcc
miscompiling LLVM.

llvm-svn: 60453
 2008-12-03 01:28:04 +00:00
Bill Wendling
580f12ae30 Second stab at target-dependent lowering of everyone's favorite nodes: [SU]ADDO 
- LowerXADDO lowers [SU]ADDO into an ADD with an implicit EFLAGS define. The
  EFLAGS are fed into a SETCC node which has the conditional COND_O or COND_C,
  depending on the type of ADDO requested.

- LowerBRCOND now recognizes if it's coming from a SETCC node with COND_O or
  COND_C set.

llvm-svn: 60388
 2008-12-02 01:06:39 +00:00
Bill Wendling
039240b301 Reapply r60382. This time, don't mark "ADC" nodes with "implicit EFLAGS". 
llvm-svn: 60385
 2008-12-02 00:07:05 +00:00
Bill Wendling
16840cba04 Temporarily revert r60382. It caused CodeGen/X86/i2k.ll and others to fail. 
llvm-svn: 60383
 2008-12-01 23:44:08 +00:00
Bill Wendling
628848b540 - Have "ADD" instructions return an implicit EFLAGS. 
- Add support for seto, setno, setc, and setnc instructions.

llvm-svn: 60382
 2008-12-01 23:30:42 +00:00
Duncan Sands
5de8739964 There are no longer any places that require a 
MERGE_VALUES node with only one operand, so get
rid of special code that only existed to handle
that possibility.

llvm-svn: 60349
 2008-12-01 11:41:29 +00:00
Duncan Sands
1fae2ea219 Change the interface to the type legalization method 
ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.

llvm-svn: 60348
 2008-12-01 11:39:25 +00:00
Eli Friedman
3b8efd50d7 A couple small cleanups, plus a new potential optimization. 
llvm-svn: 60286
 2008-11-30 07:52:27 +00:00
Duncan Sands
7fd4ea5847 Fix build with gcc-4.4: it doesn't like PICStyle 
being both a namespace and a variable name.

llvm-svn: 60208
 2008-11-28 09:29:37 +00:00
Bill Wendling
4a6eedb51d Comment out code that isn't entirely correct. 
llvm-svn: 60156
 2008-11-27 07:18:35 +00:00
Evan Cheng
f18016728c On x86 favors folding short immediate into some arithmetic operations (e.g. add, and, xor, etc.) because materializing an immediate in a register is expensive in turns of code size. 
e.g.
movl 4(%esp), %eax
addl $4, %eax

is 2 bytes shorter than

movl $4, %eax
addl 4(%esp), %eax

llvm-svn: 60139
 2008-11-27 00:49:46 +00:00
Bill Wendling
c60a07dbf2 Generate something sensible for an [SU]ADDO op when the overflow/carry flag is 
the conditional for the BRCOND statement. For instance, it will generate:

    addl %eax, %ecx
    jo LOF

instead of

    addl %eax, %ecx
    ; About 10 instructions to compare the signs of LHS, RHS, and sum.
    jl LOF

llvm-svn: 60123
 2008-11-26 22:37:40 +00:00
Dan Gohman
6a589b31f7 Fish kill flag annotations in PUSH instructions. 
llvm-svn: 60095
 2008-11-26 06:39:12 +00:00
Bill Wendling
0560ba7668 - Make lowering of "add with overflow" customizable by back-ends. 
- Mark "add with overflow" as having a custom lowering for X86. Give it a null
  lowering representation for now.

llvm-svn: 59971
 2008-11-24 19:21:46 +00:00
Evan Cheng
a19ef59d6c Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files. 
llvm-svn: 59953
 2008-11-24 07:34:46 +00:00
Mon P Wang
c9ba9d066e Added missing description for -disable-mmx option. 
llvm-svn: 59929
 2008-11-24 02:10:43 +00:00
Duncan Sands
f9ea1124c9 Rename SetCCResultContents to BooleanContents. In 
practice these booleans are mostly produced by SetCC,
however the concept is more general.

llvm-svn: 59911
 2008-11-23 15:47:28 +00:00
Mon P Wang
0f887d148c Added -disable-mmx using a patch from Preston Gurd. 
llvm-svn: 59901
 2008-11-23 04:37:22 +00:00
Anton Korobeynikov
ba74a11c9b Make a convenient helper for printing offsets. 
llvm-svn: 59872
 2008-11-22 16:15:34 +00:00
Mon P Wang
76b86c996e Allow XMM2 and XMM3 to be used for non ABI compliant code. 
llvm-svn: 59720
 2008-11-20 07:48:19 +00:00
Evan Cheng
b434100baa Eliminate a compile time warning. 
llvm-svn: 59677
 2008-11-19 23:21:11 +00:00