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7779 Commits

Author SHA1 Message Date
Owen Anderson
aba398a5ce Add a flag for indirect branch instructions. 
Target maintainers: please check that the instructions for your target are correctly marked.

llvm-svn: 44012
 2007-11-12 07:39:39 +00:00
Anton Korobeynikov
a4eb4336d2 Clarify the meaning of '-2' register number 
llvm-svn: 43998
 2007-11-11 19:53:50 +00:00
Anton Korobeynikov
8e8473c783 Use TableGen to emit information for dwarf register numbers. 
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,

llvm-svn: 43997
 2007-11-11 19:50:10 +00:00
Dale Johannesen
2e9b020e89 Add CCAssignToStackABISizeAlign for convenience in 
dealing with types whose size & alignment are
different on different subtargets.  Use it for x86 f80.

llvm-svn: 43988
 2007-11-10 22:07:15 +00:00
Arnold Schwaighofer
64ad6fa1fa Update tailcall code to include inline attribute operand for memcpy. 
llvm-svn: 43978
 2007-11-10 10:48:01 +00:00
Evan Cheng
946afd2f6c Unbreak x86-64 jumptable. 
llvm-svn: 43955
 2007-11-09 19:11:23 +00:00
Anton Korobeynikov
dcc6077439 Silence a warning 
llvm-svn: 43954
 2007-11-09 19:06:14 +00:00
Dale Johannesen
eca19e7eca Revert previous rewrite per chris's comments. 
llvm-svn: 43950
 2007-11-09 18:07:11 +00:00
Evan Cheng
7d8deec92f Much improved pic jumptable codegen: 
Then:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        imull   $4, %ecx, %ecx
        leal    LJTI1_0-"L1$pb"(%eax), %edx
        addl    LJTI1_0-"L1$pb"(%ecx,%eax), %edx
        jmpl    *%edx

        .align  2
        .set L1_0_set_3,LBB1_3-LJTI1_0
        .set L1_0_set_2,LBB1_2-LJTI1_0
        .set L1_0_set_5,LBB1_5-LJTI1_0
        .set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2

Now:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        addl    LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
        jmpl    *%eax

		.align  2
		.set L1_0_set_3,LBB1_3-"L1$pb"
		.set L1_0_set_2,LBB1_2-"L1$pb"
		.set L1_0_set_5,LBB1_5-"L1$pb"
		.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2

llvm-svn: 43924
 2007-11-09 01:32:10 +00:00
Dale Johannesen
8a9ec1582b Rewrite Dwarf number handling per review comments. 
llvm-svn: 43918
 2007-11-09 00:47:10 +00:00
Lauro Ramos Venancio
d8f2190c19 [ARM] Implement __builtin_thread_pointer. 
llvm-svn: 43892
 2007-11-08 17:20:05 +00:00
Dale Johannesen
b11aca8a92 Complete conditionalization of Dwarf reg numbers. 
Would somebody not on Darwin please make sure this
doesn't break anything.  Exception handling failures
would be the most likely symptom.

llvm-svn: 43844
 2007-11-07 21:48:35 +00:00
Dale Johannesen
a863789700 Interchange Dwarf numbers of ESP and EBP on x86 Darwin. 
Much improvement in exception handling.

llvm-svn: 43794
 2007-11-07 00:25:05 +00:00
Bruno Cardoso Lopes
77e5c419ec Better processor definition 
llvm-svn: 43749
 2007-11-06 03:15:20 +00:00
Rafael Espindola
ec025c3042 Move the LowerMEMCPY and LowerMEMCPYCall to a common place. 
Thanks for the suggestions Bill :-)

llvm-svn: 43742
 2007-11-05 23:12:20 +00:00
Lauro Ramos Venancio
f5081ba980 [ARM] Fix code generation for: 
static __thread struct {
    int a;
    int b;
} teste = {0, 0};

llvm-svn: 43722
 2007-11-05 18:33:37 +00:00
Evan Cheng
c49995c027 Use movups to spill / restore SSE registers on targets where stacks alignment is 
less than 16. This is a temporary solution until dynamic stack alignment is
implemented.

llvm-svn: 43703
 2007-11-05 07:30:01 +00:00
Bruno Cardoso Lopes
569b5512b0 Added support for PIC code with "explicit relocations" *only*. 
Removed all macro code for PIC (goodbye "la").
Support tested with shootout bench.

llvm-svn: 43697
 2007-11-05 03:02:32 +00:00
Duncan Sands
d1bdbd010b Eliminate the remaining uses of getTypeSize. This 
should only effect x86 when using long double.  Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment).  This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.

llvm-svn: 43688
 2007-11-05 00:04:43 +00:00
Chris Lattner
8fac63c8b5 Fix PR1761 by not printing (rip) suffix when in -static mode. 
Evan, please review this.

llvm-svn: 43680
 2007-11-04 19:23:28 +00:00
Nick Lewycky
36047b0b5b Fix crash before main on ppc/linux with static constructors. PR1771 
llvm-svn: 43676
 2007-11-04 17:32:10 +00:00
Chris Lattner
67cd357fb8 Fix PR1763 by allowing the 'q' constraint to work with 64-bit 
regs on x86-64.

llvm-svn: 43669
 2007-11-04 06:51:12 +00:00
Evan Cheng
bf8e7c6644 Unbreak tailcall opt. 
llvm-svn: 43646
 2007-11-02 17:45:40 +00:00
Chris Lattner
679e22d547 add a note 
llvm-svn: 43642
 2007-11-02 17:04:20 +00:00
Evan Cheng
b50cc64eb0 Missing a getNumOperands check. 
llvm-svn: 43630
 2007-11-02 01:26:22 +00:00
Duncan Sands
eb464e976f Executive summary: getTypeSize -> getTypeStoreSize / getABITypeSize. 
The meaning of getTypeSize was not clear - clarifying it is important
now that we have x86 long double and arbitrary precision integers.
The issue with long double is that it requires 80 bits, and this is
not a multiple of its alignment.  This gives a primitive type for
which getTypeSize differed from getABITypeSize.  For arbitrary precision
integers it is even worse: there is the minimum number of bits needed to
hold the type (eg: 36 for an i36), the maximum number of bits that will
be overwriten when storing the type (40 bits for i36) and the ABI size
(i.e. the storage size rounded up to a multiple of the alignment; 64 bits
for i36).

This patch removes getTypeSize (not really - it is still there but
deprecated to allow for a gradual transition).  Instead there is:

(1) getTypeSizeInBits - a number of bits that suffices to hold all
values of the type.  For a primitive type, this is the minimum number
of bits.  For an i36 this is 36 bits.  For x86 long double it is 80.
This corresponds to gcc's TYPE_PRECISION.

(2) getTypeStoreSizeInBits - the maximum number of bits that is
written when storing the type (or read when reading it).  For an
i36 this is 40 bits, for an x86 long double it is 80 bits.  This
is the size alias analysis is interested in (getTypeStoreSize
returns the number of bytes).  There doesn't seem to be anything
corresponding to this in gcc.

(3) getABITypeSizeInBits - this is getTypeStoreSizeInBits rounded
up to a multiple of the alignment.  For an i36 this is 64, for an
x86 long double this is 96 or 128 depending on the OS.  This is the
spacing between consecutive elements when you form an array out of
this type (getABITypeSize returns the number of bytes).  This is
TYPE_SIZE in gcc.

Since successive elements in a SequentialType (arrays, pointers
and vectors) need to be aligned, the spacing between them will be
given by getABITypeSize.  This means that the size of an array
is the length times the getABITypeSize.  It also means that GEP
computations need to use getABITypeSize when computing offsets.
Furthermore, if an alloca allocates several elements at once then
these too need to be aligned, so the size of the alloca has to be
the number of elements multiplied by getABITypeSize.  Logically
speaking this doesn't have to be the case when allocating just
one element, but it is simpler to also use getABITypeSize in this
case.  So alloca's and mallocs should use getABITypeSize.  Finally,
since gcc's only notion of size is that given by getABITypeSize, if
you want to output assembler etc the same as gcc then getABITypeSize
is the size you want.

Since a store will overwrite no more than getTypeStoreSize bytes,
and a read will read no more than that many bytes, this is the
notion of size appropriate for alias analysis calculations.

In this patch I have corrected all type size uses except some of
those in ScalarReplAggregates, lib/Codegen, lib/Target (the hard
cases).  I will get around to auditing these too at some point,
but I could do with some help.

Finally, I made one change which I think wise but others might
consider pointless and suboptimal: in an unpacked struct the
amount of space allocated for a field is now given by the ABI
size rather than getTypeStoreSize.  I did this because every
other place that reserves memory for a type (eg: alloca) now
uses getABITypeSize, and I didn't want to make an exception
for unpacked structs, i.e. I did it to make things more uniform.
This only effects structs containing long doubles and arbitrary
precision integers.  If someone wants to pack these types more
tightly they can always use a packed struct.

llvm-svn: 43620
 2007-11-01 20:53:16 +00:00
Bill Wendling
df2eaa8a55 Silence, accersed warning 
llvm-svn: 43609
 2007-11-01 08:51:44 +00:00
Rafael Espindola
27a8907a7c Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold 
and by restructuring the X86 version.

New I just have to move this to a common place :-)

llvm-svn: 43554
 2007-10-31 14:39:58 +00:00
Rafael Espindola
fae98471a9 Make ARM an X86 memcpy expansion more similar to each other. 
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.

This should not change generated code.

llvm-svn: 43552
 2007-10-31 11:52:06 +00:00
Dale Johannesen
9bc04ae496 Make i64=expand_vector_elt(v2i64) work in 32-bit mode. 
llvm-svn: 43535
 2007-10-31 00:32:36 +00:00
Dale Johannesen
7167117945 Add missing SSE builtins: CVTPD2PI, CVTPS2PI, 
CVTTPD2PI, CVTTPS2PI, CVTPI2PD, CVTPI2PS.

llvm-svn: 43523
 2007-10-30 22:15:38 +00:00
Duncan Sands
f6837e8634 Fix for visibility warnings generated by gcc-4.2. 
llvm-svn: 43500
 2007-10-30 13:14:37 +00:00
Dale Johannesen
461a0c47f8 Add missing MMX PSUBQ. 
llvm-svn: 43488
 2007-10-30 01:18:38 +00:00
Evan Cheng
5fe81cf64e Enable more fold (sext (load x)) -> (sext (truncate (sextload x))) 
transformation. Previously, it's restricted by ensuring the number of load uses
is one. Now the restriction is loosened up by allowing setcc uses to be
"extended" (e.g. setcc x, c, eq -> setcc sext(x), sext(c), eq).

llvm-svn: 43465
 2007-10-29 19:58:20 +00:00
Evan Cheng
1113931fd8 Avoid doing something dumb like rewriting using a 64-bit iv in 32-bit mode. 
llvm-svn: 43446
 2007-10-29 07:57:50 +00:00
Chris Lattner
be8379fac5 add a note. 
llvm-svn: 43444
 2007-10-29 06:19:48 +00:00
Chris Lattner
1503362624 Add support for the x86-64 'q' regigster modifier, and add support for the 
b/h/w/k/q inline asm memory modifiers, which are just ignored.  This fixes
PR1748 and CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll

llvm-svn: 43430
 2007-10-29 03:09:07 +00:00
Chris Lattner
7e3a8a7604 Fix PR1749 and InstCombine/2007-10-28-EmptyField.ll by handling 
zero-length fields better.

llvm-svn: 43427
 2007-10-29 02:40:02 +00:00
Evan Cheng
053178440a New entry. 
llvm-svn: 43420
 2007-10-28 04:01:09 +00:00
Anton Korobeynikov
0d3f43480e Fix off-by-one stack offset computations (dwarf information) for callee-saved 
registers in case, when FP pointer was eliminated. This should fixes misc. random
EH-related crahses, when stuff is compiled with -fomit-frame-pointer.
Thanks Duncan for nailing this bug!

llvm-svn: 43381
 2007-10-26 09:13:24 +00:00
Eric Christopher
82c77dd85b clo/clz aren't supported on mips I. Keep them around for when we'll 
want them later (mips32/64).

llvm-svn: 43380
 2007-10-26 04:00:13 +00:00
Evan Cheng
53696b7e9f Loosen up iv reuse to allow reuse of the same stride but a larger type when truncating from the larger type to smaller type is free. 
e.g.
Turns this loop:
LBB1_1: # entry.bb_crit_edge
        xorl    %ecx, %ecx
        xorw    %dx, %dx
        movw    %dx, %si
LBB1_2: # bb
        movl    L_X$non_lazy_ptr, %edi
        movw    %si, (%edi)
        movl    L_Y$non_lazy_ptr, %edi
        movw    %dx, (%edi)
		addw    $4, %dx
		incw    %si
		incl    %ecx
		cmpl    %eax, %ecx
		jne     LBB1_2  # bb
	
into

LBB1_1: # entry.bb_crit_edge
        xorl    %ecx, %ecx
        xorw    %dx, %dx
LBB1_2: # bb
        movl    L_X$non_lazy_ptr, %esi
        movw    %cx, (%esi)
        movl    L_Y$non_lazy_ptr, %esi
        movw    %dx, (%esi)
        addw    $4, %dx
		incl    %ecx
        cmpl    %eax, %ecx
        jne     LBB1_2  # bb

llvm-svn: 43375
 2007-10-26 01:56:11 +00:00
Dale Johannesen
0774a9c549 Support non-POSIX hosts by removing use of strncasecmp. 
llvm-svn: 43364
 2007-10-25 21:54:43 +00:00
Dale Johannesen
94241a8d3a Disable a couple more things for ppcf128. 
llvm-svn: 43267
 2007-10-23 23:20:14 +00:00
Evan Cheng
0590c75f18 Temporary solution: added a different set of BCTRL_Macho / BCTRL_ELF with right callee-saved defs set for ppc64. 
llvm-svn: 43248
 2007-10-23 06:42:42 +00:00
Evan Cheng
252d9ddb4d Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4. 
llvm-svn: 43234
 2007-10-22 22:11:27 +00:00
Dan Gohman
76e104c8ad Fix the folding of multiplication into addresses on x86, which was broken 
by the recent {U,S}MUL_LOHI changes.

llvm-svn: 43230
 2007-10-22 20:22:24 +00:00
Evan Cheng
85eb733eff Use ptr type in the immediate field of a BxA instruction so we don't end up selecting 32-bit call instruction for ppc64. 
llvm-svn: 43228
 2007-10-22 19:46:19 +00:00
Evan Cheng
ddeab10144 Fix an unfolding bug. 
llvm-svn: 43212
 2007-10-22 03:03:20 +00:00
Dale Johannesen
2edd0fb69d Allow for copysign having f80 second argument. 
Fixes 5550319.

llvm-svn: 43205
 2007-10-21 01:07:44 +00:00
Evan Cheng
b56784f9ea Resolve unfold tables ambiguity. 
llvm-svn: 43194
 2007-10-19 23:50:58 +00:00
Evan Cheng
ded6550885 Local spiller optimization: 
Turn a store folding instruction into a load folding instruction. e.g.
     xorl  %edi, %eax
     movl  %eax, -32(%ebp)
     movl  -36(%ebp), %eax
     orl   %eax, -32(%ebp)
=>
     xorl  %edi, %eax
     orl   -36(%ebp), %eax
     mov   %eax, -32(%ebp)
This enables the unfolding optimization for a subsequent instruction which will
also eliminate the newly introduced store instruction.

llvm-svn: 43192
 2007-10-19 21:23:22 +00:00
Rafael Espindola
c751cbdb02 split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend. 
llvm-svn: 43176
 2007-10-19 14:35:17 +00:00
Rafael Espindola
d8d4372845 Add support for byval function whose argument is not 32 bit aligned. 
To do this it is necessary to add a "always inline" argument to the
memcpy node. For completeness I have also added this node to memmove
and memset.  I have also added getMem* functions, because the extra
argument makes it cumbersome to use getNode and because I get confused
by it :-)

llvm-svn: 43172
 2007-10-19 10:41:11 +00:00
Chris Lattner
4354f2db6a comment fixes 
llvm-svn: 43168
 2007-10-19 04:08:28 +00:00
Chris Lattner
57e2fa4ba0 Add an easy microoptimization I noticed. 
llvm-svn: 43164
 2007-10-19 03:29:26 +00:00
Dale Johannesen
b23b0bfa8f More ppcf128 issues (maybe the last)? 
llvm-svn: 43160
 2007-10-19 00:59:18 +00:00
Evan Cheng
0449186690 - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding. 
- Fix some copy+paste bugs.

llvm-svn: 43153
 2007-10-18 22:40:57 +00:00
Evan Cheng
c852780685 Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface. 
llvm-svn: 43150
 2007-10-18 21:29:24 +00:00
Christopher Lamb
7f21e45b06 Fix a misnamed parameter. 
llvm-svn: 43145
 2007-10-18 19:29:45 +00:00
Christopher Lamb
a26b82ea94 Fix a typo 
llvm-svn: 43144
 2007-10-18 19:28:55 +00:00
Gordon Henriksen
3b309c68d1 Work around downrev gccs which do not inherit visibility of the 
Registry<>::iterator member class.

llvm-svn: 43122
 2007-10-18 11:53:05 +00:00
Chris Lattner
374b185092 legalizing the ret operation on f64 shouldn't introduce a new 
i64 bit convert needlessly.

llvm-svn: 43116
 2007-10-18 06:17:07 +00:00
Gordon Henriksen
a6050b38d2 Switching TargetMachineRegistry to use the new generic Registry. 
llvm-svn: 43094
 2007-10-17 21:28:48 +00:00
Chris Lattner
3a19e981f5 Change fp to sint legalization on x86-32 to do 2 x i32 
loads instead of 1 x i64 loads.  This doesn't change any functionality yet.

llvm-svn: 43068
 2007-10-17 06:17:29 +00:00
Chris Lattner
ba2d55a564 fix some funny indentation, add comments. 
llvm-svn: 43066
 2007-10-17 06:02:13 +00:00
Dale Johannesen
63411d36bf Check for invalid cc's in f80 select. 
llvm-svn: 43033
 2007-10-16 18:09:08 +00:00
Chris Lattner
45d9c7aa07 Fix a bug handling frame references in ppc inline asm when the frame offset 
doesn't fit into 16 bits.

llvm-svn: 43032
 2007-10-16 18:00:18 +00:00
Arnold Schwaighofer
f0d4d73bf6 Correction to tail call optimization code. The new return address 
was stored to the acutal stack slot before the parameters were
lowered to their stack slot. This could cause arguments to be
overwritten by the return address if the called function had less
parameters than the caller function. The update should remove the
last failing test case of llc-beta: SPASS.

llvm-svn: 43027
 2007-10-16 09:05:00 +00:00
Chris Lattner
c641c8c6ec Change LowerFP_TO_SINT to create the specific code it needs instead of 
unconditionally creating an i64 bitcast.  With the future legalizer
design, operation legalization can't introduce new nodes with illegal
types.

This fixes the rest of olden on ppc32.

llvm-svn: 43005
 2007-10-15 20:14:52 +00:00
Evan Cheng
f5bcd3d737 LowerFP_TO_SINT must not create a stack object if it's not needed. 
llvm-svn: 43004
 2007-10-15 20:11:21 +00:00
Dale Johannesen
28beae4a4f Handle PPC long double in CBackend. 
llvm-svn: 42972
 2007-10-15 01:05:37 +00:00
Evan Cheng
90645f30db Unbreak x86-64. 
llvm-svn: 42962
 2007-10-14 10:09:39 +00:00
Evan Cheng
33df6a6bed Revert 42908 for now. 
llvm-svn: 42960
 2007-10-14 05:57:21 +00:00
Dale Johannesen
6c89945eb8 Fix type mismatch error in PPC Altivec (only causes 
a problem when asserts are on).  From vecLib.

llvm-svn: 42959
 2007-10-14 01:58:32 +00:00
Duncan Sands
bf31a19c62 Clarify that fastcc has a problem with nested function 
trampolines, rather than with nested functions themselves.

llvm-svn: 42955
 2007-10-13 07:38:37 +00:00
Evan Cheng
2e2d6358bc Change unfoldMemoryOperand(). User is now responsible for passing in the 
register used by the unfolded instructions. User can also specify whether to
unfold the load, the store, or both.

llvm-svn: 42946
 2007-10-13 02:35:06 +00:00
Arnold Schwaighofer
50d2c33530 Correcting the corrections. Bad bad baaad emacs! 
llvm-svn: 42935
 2007-10-12 21:53:12 +00:00
Arnold Schwaighofer
6bcd9e7ec2 Corrected many typing errors. And removed 'nest' parameter handling 
for fastcc from X86CallingConv.td.  This means that nested functions
are not supported for calling convention 'fastcc'.

llvm-svn: 42934
 2007-10-12 21:30:57 +00:00
Duncan Sands
d781ed9d21 Due to the new tail call optimization, trampolines can no 
longer be created for fastcc functions.

llvm-svn: 42925
 2007-10-12 19:37:31 +00:00
Evan Cheng
c36fdf163a Update. 
llvm-svn: 42922
 2007-10-12 18:22:55 +00:00
Dan Gohman
a75e4a62e6 Change the names used for internal labels to use the current 
function symbol name instead of a codegen-assigned function
number.

Thanks Evan! :-)

llvm-svn: 42908
 2007-10-12 14:53:36 +00:00
Dan Gohman
ad3e823efa Mark vector ctpop, cttz, and ctlz as Expand on x86. 
llvm-svn: 42905
 2007-10-12 14:09:42 +00:00
Dan Gohman
171fb68ae0 Mark vector pow, ctpop, cttz, and ctlz as Expand on PowerPC. 
llvm-svn: 42904
 2007-10-12 14:08:57 +00:00
Evan Cheng
c7b7a3cb74 Fold load / store into MOV32to32_ and MOV16to16_. 
llvm-svn: 42895
 2007-10-12 08:38:01 +00:00
Evan Cheng
f1ead16fd5 Flag MOV32to32_ with EXTRACT_SUBREG. They should not be scheduled apart. 
llvm-svn: 42894
 2007-10-12 07:55:53 +00:00
Dan Gohman
edc841fb53 Set ISD::FPOW to Expand. 
llvm-svn: 42881
 2007-10-11 23:21:31 +00:00
Dale Johannesen
9486be1cf2 Add missing argument to PALIGNR 
llvm-svn: 42874
 2007-10-11 20:58:37 +00:00
Arnold Schwaighofer
d47210011e Added tail call optimization to the x86 back end. It can be 
enabled by passing -tailcallopt to llc.  The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
  elf/pic enabled + callee is in module + callee has
  visibility protected or hidden

llvm-svn: 42870
 2007-10-11 19:40:01 +00:00
Chris Lattner
88dcf28e45 Fix CodeGen/Generic/BasicInstrs.llx on sparc by marking divrem 
illegal.  Thanks to gabor for pointing this out!

llvm-svn: 42832
 2007-10-10 18:10:57 +00:00
Dale Johannesen
76458ddf1e Next PPC long double bits: ppcf128->i32 conversion. 
Surprisingly complicated.
Adds getTargetNode for 2 outputs, no inputs (missing).

llvm-svn: 42822
 2007-10-10 01:01:31 +00:00
Dan Gohman
6c3e0cdd36 LowerIntegerDivOrRem no longer exists. 
llvm-svn: 42787
 2007-10-09 15:45:13 +00:00
Dan Gohman
cc317de0f5 Fix grammar in a comment. 
llvm-svn: 42786
 2007-10-09 15:44:37 +00:00
Dan Gohman
9546d48e97 This is done. 
llvm-svn: 42785
 2007-10-09 15:42:21 +00:00
Evan Cheng
c00dbfc5bc Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte. 
llvm-svn: 42783
 2007-10-09 07:14:53 +00:00
Bruno Cardoso Lopes
257d5a5127 Position Independent Code (PIC) support [3] 
llvm-svn: 42780
 2007-10-09 03:15:11 +00:00
Bruno Cardoso Lopes
627ba10946 Position Independent Code (PIC) support [2] 
- Added a function to hold the stack location 
  where GP must be stored during LowerCALL
- AsmPrinter now emits directives based on
  relocation type
- PIC_ set to default relocation type (same as GCC)

llvm-svn: 42779
 2007-10-09 03:01:19 +00:00
Bruno Cardoso Lopes
3a48664e98 Position Independent Code (PIC) support [1] 
- Modified instruction format to handle pseudo instructions
- Added LoadAddr SDNode to load symbols.

llvm-svn: 42778
 2007-10-09 02:55:31 +00:00
Evan Cheng
90aa032f98 Bug fix. X86 was emitting redundant setcc and test instructions before a conditional move. 
llvm-svn: 42774
 2007-10-08 22:16:29 +00:00
Dan Gohman
6df332f0cb Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to 
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.

llvm-svn: 42762
 2007-10-08 18:33:35 +00:00
Evan Cheng
090bfbebd1 Allow x86 compare to be commutable by default. 
llvm-svn: 42761
 2007-10-08 18:27:46 +00:00
Dan Gohman
ae3b47b06f When we start enabling SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM in 
target-indepenent lowering, don't use them on PowerPC.

llvm-svn: 42755
 2007-10-08 17:28:24 +00:00
Dan Gohman
d7c8b98426 Simplify getIntPtrType, allowing it to work for arbitrary pointer sizes. 
llvm-svn: 42751
 2007-10-08 15:16:25 +00:00
Chris Lattner
fcccf4b6c4 disable this entirely: it is causing use of invalidated iterators and infinite looping. 
llvm-svn: 42739
 2007-10-07 22:00:31 +00:00
Chris Lattner
39dbb82db2 Fix many regressions on x86 by avoiding dereferencing the end iterator. 
llvm-svn: 42738
 2007-10-07 21:53:12 +00:00
Anton Korobeynikov
54ecd77023 Oops, I really wanted to commit this part also :) 
llvm-svn: 42700
 2007-10-06 16:39:43 +00:00
Anton Korobeynikov
34fefcf678 Move merge code into new helper function. 
llvm-svn: 42699
 2007-10-06 16:17:49 +00:00
Evan Cheng
dc95020e30 Added DAG xforms. e.g. 
(vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 
(vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
Remove x86 specific patterns.

llvm-svn: 42677
 2007-10-06 02:46:29 +00:00
Dale Johannesen
9b7ac95116 Next powerpc long double bits. Comparisons work, 
although not well, and shortening FP converts.

llvm-svn: 42672
 2007-10-06 01:24:11 +00:00
Evan Cheng
9af50ee6ef Commute x86 cmove instructions by swapping the operands and change the condition 
to its inverse.
Testing this as llcbeta

llvm-svn: 42661
 2007-10-05 23:13:21 +00:00
Evan Cheng
e0e36e4a0e This is done. 
llvm-svn: 42656
 2007-10-05 22:34:59 +00:00
Evan Cheng
dc467c6323 Enable convertToThreeAddress for X86 by default. 
llvm-svn: 42655
 2007-10-05 22:31:10 +00:00
Evan Cheng
2b3122e56e INC64_32r -> LEA64_32r is better than INC64_32r -> LEA32r, but it still can 
cause performance degradation.

llvm-svn: 42653
 2007-10-05 21:55:32 +00:00
Evan Cheng
688f34a273 In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. 
leal 1(%ecx), %edi, which requires 67H prefix.

llvm-svn: 42647
 2007-10-05 20:34:26 +00:00
Dale Johannesen
c7b51b678d First round of ppc long double. call/return and 
basic arithmetic works.
Rename RTLIB long double functions to distinguish
different flavors of long double; the lib functions
have different names, alas.

llvm-svn: 42644
 2007-10-05 20:04:43 +00:00
Evan Cheng
b069dd6a25 Add support to convert more 64-bit instructions to 3-address instructions. 
llvm-svn: 42642
 2007-10-05 18:20:36 +00:00
Evan Cheng
f658191412 ADC and SBB uses EFLAGS. 
llvm-svn: 42640
 2007-10-05 17:59:57 +00:00
Dan Gohman
821635b63f Change a few more spaces to tabs in assembly output. 
llvm-svn: 42638
 2007-10-05 15:58:41 +00:00
Dan Gohman
950f96e456 Change a space to a tab in the assembly output of a .globl directive 
for consistency.

llvm-svn: 42637
 2007-10-05 15:54:58 +00:00
Evan Cheng
4e46ad06fe Testing convertToThreeeAddress as X86 llcbeta. 
llvm-svn: 42630
 2007-10-05 08:04:01 +00:00
Evan Cheng
6e5205d379 Added storeRegToAddr, loadRegFromAddr, and unfoldMemoryOperand's. 
llvm-svn: 42624
 2007-10-05 01:34:55 +00:00
Evan Cheng
32766d3518 Not needed any more. 
llvm-svn: 42623
 2007-10-05 01:34:14 +00:00
Evan Cheng
d2ef8c689e Forgot these. 
llvm-svn: 42622
 2007-10-05 01:33:45 +00:00
Evan Cheng
f536e2f41e - Added a few target hooks to generate load / store instructions from / to any 
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.

llvm-svn: 42621
 2007-10-05 01:32:41 +00:00
Chris Lattner
4224151a44 add a note. 
llvm-svn: 42607
 2007-10-04 15:47:27 +00:00
Dan Gohman
30ba45b569 Use empty() member functions when that's what's being tested for instead 
of comparing begin() and end().

llvm-svn: 42585
 2007-10-03 19:26:29 +00:00
Chris Lattner
a31fa80185 add a note 
llvm-svn: 42579
 2007-10-03 17:10:03 +00:00
Chris Lattner
17feaa781c add a note 
llvm-svn: 42573
 2007-10-03 06:10:59 +00:00
Chris Lattner
dfcb750656 Bill's example is still not enough to repro this, but it has other issues that 
seem significant as well.

llvm-svn: 42564
 2007-10-03 03:40:24 +00:00
Bill Wendling
c5fbf331ff Another micro-opt. 
llvm-svn: 42554
 2007-10-02 21:49:31 +00:00
Bill Wendling
c4a53b617f Another missed optimization with LICM. 
llvm-svn: 42552
 2007-10-02 21:43:06 +00:00
Bill Wendling
36f033e53e Small label changes. 
llvm-svn: 42549
 2007-10-02 21:02:53 +00:00
Bill Wendling
a7d5c36215 Now with source code. 
llvm-svn: 42548
 2007-10-02 21:01:16 +00:00
Bill Wendling
0159f0c5ba Now with LL code! 
llvm-svn: 42547
 2007-10-02 20:54:32 +00:00
Bill Wendling
48c27bf598 Another missed optimization. 
llvm-svn: 42546
 2007-10-02 20:42:59 +00:00
Bill Wendling
5e50716a6b Micro-optimization -- missed LICM opportunity. 
llvm-svn: 42542
 2007-10-02 19:55:05 +00:00
Dale Johannesen
a4e3643cb3 Rewrite sqrt and powi to use anyfloat. By popular demand. 
llvm-svn: 42537
 2007-10-02 17:43:59 +00:00
Evan Cheng
3537dbbd1e Refactor code to add load / store folded instructions -> register only 
instructions reverse map.

llvm-svn: 42509
 2007-10-01 23:44:33 +00:00
Evan Cheng
c863779cd4 Typo. X86comi doesn't read / write chain's. 
llvm-svn: 42492
 2007-10-01 18:12:48 +00:00
Dale Johannesen
ef488c7b0e Add getABITypeSize, getABITypeSizeInBits 
llvm-svn: 42488
 2007-10-01 16:03:14 +00:00
Gordon Henriksen
9b5a117d01 AsmPrinters overriding getAnalysisUsage should call super. 
And not super's super, either.

llvm-svn: 42482
 2007-09-30 13:39:29 +00:00
Evan Cheng
f3c130a8b6 Enabling new condition code modeling scheme. 
llvm-svn: 42459
 2007-09-29 00:00:36 +00:00
Rafael Espindola
01b306e575 Refactor the memcpy lowering for the x86 target. 
The only generated code difference is that now we call memcpy when
the size of the array is unknown. This matches GCC behavior and is
better since the run time value can be arbitrarily large.

llvm-svn: 42433
 2007-09-28 12:53:01 +00:00
Evan Cheng
c2acb6f2e5 Stop inventing new words. :-) 
llvm-svn: 42429
 2007-09-28 01:35:02 +00:00
Evan Cheng
d3ff9d3ff7 Pessimisively assume ADJCALLSTACKDOWN / ADJCALLSTACKUP (which becomes sub / add) clobbers EFLAGS. 
llvm-svn: 42426
 2007-09-28 01:19:48 +00:00
Dan Gohman
50747737a5 TargetAsmInfo::getAddressSize() was incorrect for x86-64 and 64-bit targets 
other than PPC64. Instead of fixing it, just remove it and fix all the
places that use it to use TargetData::getPointerSize() instead, as there
aren't very many. Most of the references were in DwarfWriter.cpp.

llvm-svn: 42419
 2007-09-27 23:12:31 +00:00
Evan Cheng
d8ab90ae1f Use GR64 in 64-bit mode. 
llvm-svn: 42417
 2007-09-27 21:50:05 +00:00
Evan Cheng
826f0f94df Doh. Calls clobber EFLAGS. 
llvm-svn: 42413
 2007-09-27 19:01:55 +00:00
Dale Johannesen
089d2e760f Make temporaries explicit to avoid premature 
destruction of compiler-created ones.

llvm-svn: 42383
 2007-09-26 23:20:33 +00:00
Evan Cheng
29817845b3 - Move getPhysicalRegisterRegClass() from ScheduleDAG to MRegisterInfo. 
- Added ability to emit cross class register copies to the BBRU scheduler.
- More aggressive backtracking.

llvm-svn: 42375
 2007-09-26 21:36:17 +00:00
Evan Cheng
0f9e307353 - Added MRegisterInfo::getCrossCopyRegClass() hook. For register classes where reg to reg copies are not possible, this returns another register class which registers in the specified register class can be copied to (and copy back from). 
- X86 copyRegToReg() now supports copying between EFLAGS and GR32 / GR64 registers.

llvm-svn: 42372
 2007-09-26 21:31:07 +00:00
Evan Cheng
66eeb8440c Some assemblers do not recognize aliases pushfd, pushfq, popfd, and popfq. Just emit them as pushf and popf. 
llvm-svn: 42371
 2007-09-26 21:28:00 +00:00
Dale Johannesen
69595b587f Enable codegen for long double abs, sin, cos 
llvm-svn: 42368
 2007-09-26 21:10:55 +00:00
Evan Cheng
37ee6eba29 Typos: POPQ -> POPFQ, POPD -> POPFD. 
llvm-svn: 42348
 2007-09-26 06:38:29 +00:00
Chris Lattner
86e73ac224 move PR1160 here. 
llvm-svn: 42347
 2007-09-26 06:29:31 +00:00
Evan Cheng
5f9e291240 Allow copyRegToReg to emit cross register classes copies. 
Tested with "make check"!

llvm-svn: 42346
 2007-09-26 06:25:56 +00:00
Chris Lattner
2efd3899f2 move PR1264 here. 
llvm-svn: 42345
 2007-09-26 06:15:48 +00:00
Evan Cheng
5cb9dbaaa1 Add pushf{d|q}, popf{d|q} to push and pop EFLAGS register. 
llvm-svn: 42335
 2007-09-26 01:29:06 +00:00
Evan Cheng
38c7d5082a translateX86CC updates the last two operands. 
llvm-svn: 42333
 2007-09-26 00:45:55 +00:00
Anton Korobeynikov
8cd666b659 Correctly restore stack pointer after realignment in main() on Cygwin/Mingw32 
llvm-svn: 42332
 2007-09-26 00:13:34 +00:00
Evan Cheng
24c5a1a484 Missing load / store folding entries. 
llvm-svn: 42323
 2007-09-25 22:10:43 +00:00
Anton Korobeynikov
ca03aec919 Partly revert invalid r41774 
llvm-svn: 42322
 2007-09-25 21:52:30 +00:00
Dan Gohman
99e8e1ff08 More explicit keywords. 
llvm-svn: 42316
 2007-09-25 20:27:06 +00:00
Dan Gohman
a01dd49472 Fix a typo in a comment. 
llvm-svn: 42313
 2007-09-25 19:37:26 +00:00
Evan Cheng
a58633d67b New style x87 cmp instructions. 
llvm-svn: 42312
 2007-09-25 19:08:02 +00:00
Dan Gohman
1bb346f9f1 When both x/y and x%y are needed (x and y both scalar integer), compute 
both results with a single div or idiv instruction. This uses new X86ISD
nodes for DIV and IDIV which are introduced during the legalize phase
so that the SelectionDAG's CSE can automatically eliminate redundant
computations.

llvm-svn: 42308
 2007-09-25 18:23:27 +00:00
Dan Gohman
8385890394 Move the setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand) and 
the check to see if the assembler supports .loc from X86TargetLowering
into the superclass TargetLowering.

llvm-svn: 42297
 2007-09-25 15:10:49 +00:00
Evan Cheng
36b3babfde Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after 
all the kinks are worked out.

llvm-svn: 42285
 2007-09-25 01:57:46 +00:00
Evan Cheng
6bfaf13dd9 New temporary option -new-cc-modeling-scheme to test the new cc modeling scheme. 
llvm-svn: 42283
 2007-09-25 01:50:04 +00:00
Evan Cheng
0a3651a70d Rename keyword "modify" -> "implicit". 
llvm-svn: 42282
 2007-09-25 01:48:59 +00:00
Dale Johannesen
5ea6a9bc3a When mixing SSE and x87 codegen, it's possible to 
have situations where an SSE instruction turns into
multiple blocks, with the live range of an x87
register crossing them.  To do this correctly make
sure we examine all blocks when inserting
FP_REG_KILL.  PR 1697.  (This was exposed by my
fix for PR 1681, but the same thing could happen
mixing x87 long double with SSE.)

llvm-svn: 42281
 2007-09-24 22:52:39 +00:00
Dan Gohman
96d5f979bc Add support on x86 for having Legalize lower ISD::LOCATION to ISD::DEBUG_LOC 
instead of ISD::LABEL with a manual .debug_line entry when the assembler
supports .file and .loc directives.

llvm-svn: 42278
 2007-09-24 21:54:14 +00:00
Dan Gohman
b642a1ddf8 Merge hasDotLoc and hasDotFile into hasDotLocAndDotFile since .loc and .file 
aren't really usable without each other. 

llvm-svn: 42274
 2007-09-24 21:09:53 +00:00
Bruno Cardoso Lopes
23468a24c9 Added "LoadEffective" pattern to handle stack locations. 
Fixed some comments

llvm-svn: 42271
 2007-09-24 20:15:11 +00:00
Dan Gohman
a264777dc1 Fix the syntax for the .loc directive in preparation for using it. 
llvm-svn: 42268
 2007-09-24 19:25:06 +00:00
Dan Gohman
32b1df2aa3 The code that used the StartLabelId label was removed, so remove the 
code that creates the label too.

llvm-svn: 42265
 2007-09-24 16:44:26 +00:00
Chris Lattner
594d3aa066 claim that "st" is from the 80-bit register file. This causes x87-using inline 
asm to die with:

ScheduleDAG.cpp:269: failed assertion `false && "Couldn't find the register class"'

instead of:
failed assertion `RegMap->getRegClass(VReg) == RC && "Register class of operand and regclass of use don't agree!"'

yay.

llvm-svn: 42259
 2007-09-24 05:27:37 +00:00
Dale Johannesen
ea6ffa0b36 Fix PR 1681. When X86 target uses +sse -sse2, 
keep f32 in SSE registers and f64 in x87.  This
is effectively a new codegen mode.
Change addLegalFPImmediate to permit float and
double variants to do different things.
Adjust callers.

llvm-svn: 42246
 2007-09-23 14:52:20 +00:00
Chris Lattner
03d0e8d0ff Fix PR1679, by printing GEP indices as signed values instead of unsigned. 
llvm-svn: 42239
 2007-09-22 20:16:48 +00:00
Rafael Espindola
11ee0898b9 Don't add a default STACK_ALIGN (use the generic ABI alignment) 
Implement calls to functions with byval arguments on X86

llvm-svn: 42192
 2007-09-21 15:50:22 +00:00
Rafael Espindola
b0b536b597 small cleanup: use LowerMemArgument in LowerFastCCArguments also 
llvm-svn: 42189
 2007-09-21 14:55:38 +00:00
Evan Cheng
d675ed5400 Honor user-defined section specification of a global, ignores whether its initializer is null. 
llvm-svn: 42182
 2007-09-21 00:41:19 +00:00
Devang Patel
a6a6e699a1 Do not override user specified section. 
llvm-svn: 42179
 2007-09-20 23:07:37 +00:00
Dan Gohman
eb622df2ef Fix several more entries in the x86 reload/remat folding tables. 
llvm-svn: 42162
 2007-09-20 14:17:21 +00:00
Dale Johannesen
ab5a68edd5 another long double buglet 
llvm-svn: 42159
 2007-09-20 01:27:54 +00:00
Evan Cheng
267f595834 Enable if-conversion for ARM by default. 
llvm-svn: 42156
 2007-09-20 00:48:22 +00:00
Dale Johannesen
04682bdc81 More long double fixes. x86_64 should build now. 
llvm-svn: 42155
 2007-09-19 23:55:34 +00:00
Evan Cheng
9e2db47639 Avoid referencing deleted instruction. 
llvm-svn: 42153
 2007-09-19 21:48:07 +00:00
Evan Cheng
ec83699473 PSHUFDmi, etc. are actually folding a load, not a store. 
llvm-svn: 42147
 2007-09-19 19:02:47 +00:00
Evan Cheng
8e459700fe Set CCR (EFLAGS) copy cost to -1, i.e. extremely expensive to copy. 
llvm-svn: 42124
 2007-09-19 01:36:39 +00:00
Evan Cheng
859720c33b Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value 
between two registers in the specific class.

llvm-svn: 42123
 2007-09-19 01:35:01 +00:00
Dan Gohman
be3b005b2d Move the entries for 64-bit CMP, IMUL, and a few others into the correct 
tables so that they are eligible for reload/remat folding. And add
entries for JMP and CALL.

llvm-svn: 42094
 2007-09-18 14:59:14 +00:00
Dale Johannesen
46adce144c Remove RSTRegClass case from loadRegFromStackSlot 
and storeRegToStackSlot.  Evan and I concluded this
should never be needed and it appears to be true.
(It if is needed, adjustment would be needed for
long double to work.)

llvm-svn: 42049
 2007-09-17 20:15:38 +00:00
Chris Lattner
cc315726f7 Merge DenseMapKeyInfo & DenseMapValueInfo into DenseMapInfo 
Add a new DenseMapInfo::isEqual method to allow clients to redefine
the equality predicate used when probing the hash table.

llvm-svn: 42042
 2007-09-17 18:34:04 +00:00
Evan Cheng
d7742e7939 X86ISD::TEST is dead. 
llvm-svn: 42037
 2007-09-17 17:42:53 +00:00
Dan Gohman
b096221b3e Add 64-bit jmp instructions to the list of instructions that 
can terminate a block with no fall-through.

llvm-svn: 42029
 2007-09-17 15:19:08 +00:00
Dan Gohman
41a6dea029 Use xorl instead of xorq to enter a zero into a 64-bit register. 
llvm-svn: 42027
 2007-09-17 14:55:08 +00:00
Dan Gohman
1aeaeec570 Emit integer x<1 as x<=0, as comparisons with zero (now includeing 
64-bit) can use test instead of cmp with an immediate.

llvm-svn: 42026
 2007-09-17 14:49:27 +00:00
Dan Gohman
b9449c9118 Use "test reg,reg" in place of "cmp reg,0" for 64-bit operands. This was 
previously only done for 32-bit and smaller operands.

llvm-svn: 42024
 2007-09-17 14:35:24 +00:00
Dale Johannesen
0ea2cc2e51 Implement x86 long double (uses host long double, 
so only works on x86 target).

llvm-svn: 42019
 2007-09-17 00:38:27 +00:00
Bill Wendling
f1335f46d4 Follow-up to patch r41999. Make the conditional that emits the personality stub 
match the conditional that turns on exception handling emittion in the asm
printer.

llvm-svn: 42008
 2007-09-16 19:21:08 +00:00
Bill Wendling
7932341cef Only emit the personality function as a global value if the backend actually 
supports it. This solves this error on the Darwin x86-64 platform:

$ cat testcase.ii
struct A {
  A();
};

A *bork() {
  return new A;
}
$ llvm-g++ -arch x86_64 -c testcase.ii
/var/tmp//cc3U8fd8.s:52:unknown section type: non_lazy_symbol_pointers
/var/tmp//cc3U8fd8.s:52:Rest of line ignored. 1st junk character valued 76 (L).
/var/tmp//cc3U8fd8.s:53:Unknown pseudo-op: .indirect_symbol
/var/tmp//cc3U8fd8.s:53:Rest of line ignored. 1st junk character valued 95 (_).

llvm-svn: 41999
 2007-09-16 10:36:17 +00:00
Chris Lattner
1b622ad721 Fix PR1666, SPASS with the CBE and 254.gap with the CBE. 
GCC optimizes away things like ptr < NULL  to false.  To "fix" this,
have the CBE emit casts of pointers to intptr_t when doing relational
pointer comparisons.

llvm-svn: 41983
 2007-09-15 06:51:03 +00:00
Dan Gohman
df419c2b4f Add patterns for SHLD64* and SHRD64*. 
llvm-svn: 41975
 2007-09-14 23:17:45 +00:00
Dale Johannesen
575bd6070a Remove the assumption that FP's are either float or 
double from some of the many places in the optimizers
it appears, and do something reasonable with x86
long double.
Make APInt::dump() public, remove newline, use it to
dump ConstantSDNode's.
Allow APFloats in FoldingSet.
Expand X86 backend handling of long doubles (conversions
to/from int, mostly).

llvm-svn: 41967
 2007-09-14 22:26:36 +00:00
Evan Cheng
13797e4a74 Add implicit def of EFLAGS on those instructions that may modify flags. 
llvm-svn: 41962
 2007-09-14 21:48:26 +00:00
Dan Gohman
fb60c0dfed Remove isReg, isImm, and isMBB, and change all their users to use 
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.

llvm-svn: 41958
 2007-09-14 20:33:02 +00:00
Rafael Espindola
5d8b225881 Add support for functions with byval arguments on x86 
llvm-svn: 41953
 2007-09-14 15:48:13 +00:00
Evan Cheng
3aafca793b Fix comments. 
llvm-svn: 41947
 2007-09-14 01:57:02 +00:00
Evan Cheng
bd4b11cfa9 Initial support for multi-result patterns: 
1.
[(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 (modify EFLAGS)]
This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS.
2.
def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()>
Similar to #1 except this is used for def : Pat patterns.

llvm-svn: 41897
 2007-09-12 23:30:14 +00:00
Dale Johannesen
4784ee3431 Revise previous patch per review comments. 
Next round of x87 long double stuff.
Getting close now, basically works.

llvm-svn: 41875
 2007-09-12 03:30:33 +00:00
Bill Wendling
89ced2f9b1 Enable indirect encoding for the personality function 
llvm-svn: 41873
 2007-09-11 23:55:40 +00:00
Evan Cheng
b43255bc68 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
llvm-svn: 41863
 2007-09-11 19:55:27 +00:00
Evan Cheng
ce8087de3e Added status flags register: EFLAGS. 
llvm-svn: 41862
 2007-09-11 19:53:28 +00:00
Dale Johannesen
7bc3969cea Add APInt interfaces to APFloat (allows directly 
access to bits).  Use them in place of float and
double interfaces where appropriate.
First bits of x86 long double constants handling 
(untested, probably does not work).

llvm-svn: 41858
 2007-09-11 18:32:33 +00:00
Bill Wendling
74888e63e7 Add a bool to indicate if we should set the "indirect encoding" bit in the Dwarf 
information for EH.

llvm-svn: 41852
 2007-09-11 17:20:55 +00:00
Duncan Sands
c358890f73 Fold the adjust_trampoline intrinsic into 
init_trampoline.  There is now only one
trampoline intrinsic.

llvm-svn: 41841
 2007-09-11 14:10:23 +00:00
Duncan Sands
8640185d45 My compiler warns about the semicolon. 
llvm-svn: 41840
 2007-09-11 12:30:25 +00:00
Bill Wendling
3c6a8b2814 The personality function on Darwin needs a global stub. We then refer to 
that global stub instead of doing the ".set" thingy we were doing before.

llvm-svn: 41838
 2007-09-11 08:27:17 +00:00
Evan Cheng
24e8e4d6ef 80 col. 
llvm-svn: 41812
 2007-09-10 22:22:23 +00:00
Evan Cheng
b639648fc5 New entry. 
llvm-svn: 41810
 2007-09-10 22:16:37 +00:00
Chris Lattner
d4602cc0e7 Add some notes about better flag handling. 
llvm-svn: 41808
 2007-09-10 21:43:18 +00:00
Evan Cheng
4715ccb29c It's not safe to rematerialize MOV32r0 etc. by simply cloning the original 
instruction. These are implemented with xor which will modify the conditional
code. They should be rematerialized as move instructions.

llvm-svn: 41802
 2007-09-10 20:48:53 +00:00
Evan Cheng
65df926ced TableGen no longer emit CopyFromReg nodes for implicit results in physical 
registers. The scheduler is now responsible for emitting them.

llvm-svn: 41781
 2007-09-07 23:59:02 +00:00
Bill Wendling
04a6163921 Add missing index versions of instructions to the map. 
llvm-svn: 41776
 2007-09-07 22:01:02 +00:00
Dan Gohman
3bc1bc2590 Avoid storing and reloading zeros and other constants from stack slots 
by flagging the associated instructions as being trivially rematerializable.

llvm-svn: 41775
 2007-09-07 21:32:51 +00:00
Dale Johannesen
783215c630 Apply feedback from previous patch. 
llvm-svn: 41774
 2007-09-07 21:07:57 +00:00
Rafael Espindola
8c57e70f93 Add support for having different alignment for objects on call frames. 
The x86-64 ABI states that objects passed on the stack have
8 byte alignment. Implement that.

llvm-svn: 41768
 2007-09-07 14:52:14 +00:00
Owen Anderson
4b71e55287 Add lengthof and endof templates that hide a lot of sizeof computations. 
Patch by Sterling Stein!

llvm-svn: 41758
 2007-09-07 04:06:50 +00:00
Dale Johannesen
86f367a6b7 Next round of APFloat changes. 
Use APFloat in UpgradeParser and AsmParser.
Change all references to ConstantFP to use the
APFloat interface rather than double.  Remove
the ConstantFP double interfaces.
Use APFloat functions for constant folding arithmetic
and comparisons.
(There are still way too many places APFloat is
just a wrapper around host float/double, but we're
getting there.)

llvm-svn: 41747
 2007-09-06 18:13:44 +00:00
Evan Cheng
896c1ed385 Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen: 
leal    (,%rcx,8), %rcx
It should be
leal    (,%rcx,8), %ecx

llvm-svn: 41735
 2007-09-06 00:14:41 +00:00
Bill Wendling
46d5fb4e5d LVXL and STVXL are also a load and store resp. 
llvm-svn: 41733
 2007-09-05 23:47:12 +00:00
Bill Wendling
13549db795 Add the 64-bit versions of the DS* Altivec instructions. 
llvm-svn: 41717
 2007-09-05 04:05:20 +00:00
Evan Cheng
02c6081f2d Fix for PR1613: added 64-bit rotate left PPC instructions and patterns. 
llvm-svn: 41711
 2007-09-04 20:20:29 +00:00
Evan Cheng
4cae11d569 Mac OS X X86-64 ABI is same as the standard. 
llvm-svn: 41700
 2007-09-04 16:44:41 +00:00
Anton Korobeynikov
cf91be2c79 Reapply r41578 with proper fix 
llvm-svn: 41680
 2007-09-03 00:36:06 +00:00
Dale Johannesen
a79f7d4068 Revise per review of previous patch. 
llvm-svn: 41645
 2007-08-31 17:03:33 +00:00
Rafael Espindola
4ddaad4de0 Initial support for calling functions with byval arguments on x86-64 
llvm-svn: 41643
 2007-08-31 15:06:30 +00:00
Rafael Espindola
aa7930b4f0 Align i64 and f64 at 8 byte on x86-64. 
This is mandated table 3.1 at
http://www.x86-64.org/documentation/abi.pdf

llvm-svn: 41642
 2007-08-31 12:23:58 +00:00
Dale Johannesen
81d6ecb886 Enhance APFloat to retain bits of NaNs (fixes oggenc). 
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.

llvm-svn: 41632
 2007-08-31 04:03:46 +00:00
Raul Herbster
ffa8296e3f Instruction formats added used to generate multiply instructions of V5TE. 
llvm-svn: 41629
 2007-08-30 23:34:14 +00:00
Raul Herbster
7f1a7dc4e2 Unused relocation type reloc_arm_absolute removed. 
llvm-svn: 41628
 2007-08-30 23:31:35 +00:00
Raul Herbster
db2f42989b Comments added. It now generates V5TE multiply instructions. However, it is still necessary to model PUWLSH bits more clearly. 
llvm-svn: 41627
 2007-08-30 23:29:26 +00:00
Raul Herbster
49b44eae34 ARM instruction table was modified by adding information to generate multiply instruction of V5TE. 
llvm-svn: 41626
 2007-08-30 23:25:47 +00:00
Raul Herbster
26e15aed5c JITInfo now resolves function addrs and also relocations. It always emits a stub. 
llvm-svn: 41625
 2007-08-30 23:21:27 +00:00
Evan Cheng
cb317912b2 Added support to fold X86 load / store instructions. This allow rematerialized loads to be folded into their uses. 
llvm-svn: 41599
 2007-08-30 05:54:07 +00:00
Evan Cheng
58ea935f6f Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots. 
llvm-svn: 41597
 2007-08-30 05:52:20 +00:00
Evan Cheng
527fe7ab57 Mark load instructions with isLoad = 1. 
llvm-svn: 41595
 2007-08-30 05:49:43 +00:00
Bill Wendling
c65cf7849d Use i64 on a PPC64 machine 
llvm-svn: 41590
 2007-08-30 00:59:19 +00:00
Dale Johannesen
e91a908971 Change LegalFPImmediates to use APFloat. 
Add APFloat interfaces to ConstantFP, SelectionDAG.
Fix integer bit in double->APFloat conversion.
Convert LegalizeDAG to use APFloat interface in
ConstantFPSDNode uses.

llvm-svn: 41587
 2007-08-30 00:23:21 +00:00