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Commit Graph

61511 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
5af812b35b Fix typo, SSE1 should be used by XS, not SSE2
llvm-svn: 106357
2010-06-18 23:53:27 +00:00
Eric Christopher
10fa91df80 Remove isTwoAddress from 64-bit files.
llvm-svn: 106356
2010-06-18 23:51:21 +00:00
Evan Cheng
e9ba3241a3 Move ARM if-conversion before post-ra scheduling.
llvm-svn: 106355
2010-06-18 23:32:07 +00:00
Dan Gohman
823dff64cd Teach regular and fast isel to set dead flags on unused implicit defs
on calls and similar instructions.

llvm-svn: 106353
2010-06-18 23:28:01 +00:00
Bruno Cardoso Lopes
ec4b18a1cf Apply some refactor to packed instructions
llvm-svn: 106349
2010-06-18 23:13:35 +00:00
Evan Cheng
5e2c36c202 Update cmake list.
llvm-svn: 106348
2010-06-18 23:12:10 +00:00
Evan Cheng
f776ed836b Thumb2 hazard recognizer.
llvm-svn: 106347
2010-06-18 23:11:35 +00:00
Jakob Stoklund Olesen
7150b84292 Only run CoalesceExtSubRegs when we can expect LiveIntervalAnalysis to clean up
the inserted INSERT_SUBREGs after us.

llvm-svn: 106345
2010-06-18 23:10:20 +00:00
Evan Cheng
b5fadc47e0 Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.

llvm-svn: 106344
2010-06-18 23:09:54 +00:00
Jim Grosbach
b8c94667a8 back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)
llvm-svn: 106342
2010-06-18 23:03:10 +00:00
Eric Christopher
b04dbfd059 Another typo.
llvm-svn: 106340
2010-06-18 22:51:25 +00:00
Jim Grosbach
c599143b45 Enable Expand handling of atomics for subtargets that can't do them inline.
llvm-svn: 106336
2010-06-18 22:35:32 +00:00
Eric Christopher
9f949b1c6a Fix typo.
llvm-svn: 106335
2010-06-18 22:33:17 +00:00
Jakob Stoklund Olesen
3f0825f966 TwoAddressInstructionPass::CoalesceExtSubRegs can insert INSERT_SUBREG
instructions, but it doesn't really understand live ranges, so the first
INSERT_SUBREG uses an implicitly defined register.

Fix it in LiveVariableAnalysis by adding the <undef> flag.

llvm-svn: 106333
2010-06-18 22:29:44 +00:00
Evan Cheng
aa0ff1ae01 Fix an inverted condition.
llvm-svn: 106330
2010-06-18 22:17:13 +00:00
Bruno Cardoso Lopes
55fbcf678c Use the new 'defm' class inheritance in SSE
llvm-svn: 106327
2010-06-18 22:10:11 +00:00
Evan Cheng
9a97e1e7f7 Fix cross initialization compilation error.
llvm-svn: 106324
2010-06-18 22:01:37 +00:00
Evan Cheng
b60ce2d7b4 Teach iff-converter to properly count # of dups. It was not skipping over dbg_value's which resulted in non-duplicated instructions being deleted. rdar://8104384.
llvm-svn: 106323
2010-06-18 21:52:57 +00:00
Jim Grosbach
91aae1c534 Add Expand-to-libcall support for additional atomics. This covers the usual
entries used by llvm-gcc. *_[U]MIN and such can be added later if needed.

This enables the front ends to simplify handling of the atomic intrinsics by
removing the target-specific decision about which targets can handle the
intrinsics.

llvm-svn: 106321
2010-06-18 21:43:38 +00:00
Bob Wilson
e77d313369 Rewrite chained if's as switches and replace assertions with llvm_unreachable
(as suggested in radar 8104405).

llvm-svn: 106318
2010-06-18 21:32:42 +00:00
Dale Johannesen
3f9da2755d Fix ARM/Thumb reversal in previous attempt.
llvm-svn: 106314
2010-06-18 21:07:47 +00:00
Jakob Stoklund Olesen
a1d49fabaf When using ADDri to get the address of a stack object, 255 is a conservative
limit on the offset that can be materialized without using the register
scavenger.

llvm-svn: 106312
2010-06-18 20:59:25 +00:00
Dan Gohman
f85a514a9f Make this comment less specific.
llvm-svn: 106311
2010-06-18 20:45:41 +00:00
Dan Gohman
758ba8093d Fix X86FastISel's address-mode folding to stay within the
original basic block. This avoids trouble with examining
instructions in other basic blocks which haven't been
assigned registers yet.

llvm-svn: 106310
2010-06-18 20:44:47 +00:00
Dale Johannesen
81914dea4e An attempt to fix the problem Anton reported with
ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.

llvm-svn: 106309
2010-06-18 20:44:28 +00:00
Dan Gohman
b5ec637e57 Revert r106304 (105548 and friends), which are the SCEVComplexityCompare
optimizations. There is still some nondeterminism remaining.

llvm-svn: 106306
2010-06-18 19:54:20 +00:00
Bruno Cardoso Lopes
71ad64af39 Teach tablegen how to inherit from classes in 'defm' definitions.
The rule is simple: only inherit from a class list if they come
in the end, after the last multiclass.

llvm-svn: 106305
2010-06-18 19:53:41 +00:00
Dan Gohman
527b570925 Reapply 105540, 105542, and 105548, and revert r105732.
llvm-svn: 106304
2010-06-18 19:26:04 +00:00
Rafael Espindola
d7bfa3a0f7 Add a pass-through option to the plugin. The use case for this option is to
ask the linker to take another look into some library or object. The case when
one might want to do this is when codegen introduces a new undefined reference.
The canonical example is libgcc.

llvm-svn: 106303
2010-06-18 19:18:58 +00:00
Dan Gohman
75f6f94c48 Reapply 105546.
llvm-svn: 106302
2010-06-18 19:12:32 +00:00
Dan Gohman
ab895769a7 Reapply 105544.
llvm-svn: 106301
2010-06-18 19:09:27 +00:00
Dan Gohman
b220af45eb Add explicit keywords.
llvm-svn: 106300
2010-06-18 19:04:37 +00:00
Dale Johannesen
a441c8fd45 Enable tail calls on ARM by default, with some
basic tests.

This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
  B.W  <label in other function>
which it has not seen before, at least from llvm-based
compilers.  I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.

llvm-svn: 106299
2010-06-18 19:00:18 +00:00
Dan Gohman
f03db5dcc6 Don't leak RegClass2VRegMap, which is now a new[] array instead of a
std::vector.

llvm-svn: 106298
2010-06-18 18:54:05 +00:00
Dan Gohman
1ccf40774e Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.

llvm-svn: 106296
2010-06-18 18:13:55 +00:00
Dale Johannesen
9f18fc3fa2 Last round of changes for ARM tail calls.
Not turning them on yet.

llvm-svn: 106295
2010-06-18 18:13:11 +00:00
Jim Grosbach
60a3287950 Grammar.
llvm-svn: 106292
2010-06-18 17:40:42 +00:00
Bob Wilson
9af2272272 Fix PR7372: Conditional branches (at least on ARM) are treated as predicated,
so when IfConverter::CopyAndPredicateBlock checks to see if it should ignore
an instruction because it is a branch, it should not check if the branch is
predicated.

This case (when IgnoreBr is true) is only relevant from IfConvertTriangle,
where new branches are inserted after the block has been copied and predicated.
If the original branch is not removed, we end up with multiple conditional
branches (possibly conflicting) at the end of the block.  Aside from any
immediate errors resulting from that, this confuses the AnalyzeBranch functions
so that the branches are not analyzable.  That in turn causes the IfConverter to
think that the "Simple" pattern can be applied, and things go downhill fast
because the "Simple" pattern does _not_ apply if the block can fall through.

This is pretty fragile.  If there are other degenerate cases where AnalyzeBranch
fails, but where the block may still fall through, the IfConverter should not
perform its "Simple" if-conversion.  But, I don't know how to do that with the
current AnalyzeBranch interface, so for now, the best thing seems to be to
avoid creating branches that AnalyzeBranch cannot handle.

Evan, please review!

llvm-svn: 106291
2010-06-18 17:07:23 +00:00
Jakob Stoklund Olesen
6c387d99ca Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.

llvm-svn: 106289
2010-06-18 16:49:33 +00:00
Dan Gohman
0422fad3a6 Don't bother calling releaseMemory before destroying the DominatorTreeBase.
llvm-svn: 106287
2010-06-18 16:09:11 +00:00
Dan Gohman
07dc65e0b5 Minor code simplifications.
llvm-svn: 106286
2010-06-18 16:00:29 +00:00
Dan Gohman
6c6e9a45ff Give NamedRegionTimer an Enabled flag, allowing all its clients to
switch from this:

  if (TimePassesIsEnabled) {
    NamedRegionTimer T(Name, GroupName);
    do_something();
  } else {
    do_something(); // duplicate the code, this time without a timer!
  }

to this:

  {
    NamedRegionTimer T(Name, GroupName, TimePassesIsEnabled);
    do_something();
  }

llvm-svn: 106285
2010-06-18 15:56:31 +00:00
Dan Gohman
6670a7edea Don't replace the old Ordering object with a new one; just clear()
the old one.

llvm-svn: 106284
2010-06-18 15:40:58 +00:00
Dan Gohman
d3b13d1a68 Don't call clear() on DbgInfo when it's going to be deleted anyway.
Don't replace the old DbgInfo with a new one when clear() on the
old one is sufficient.

llvm-svn: 106283
2010-06-18 15:36:18 +00:00
Dan Gohman
e9dfb84007 Change UpdateNodeOperands' operand and return value from SDValue to
SDNode *, since it doesn't care about the ResNo value.

llvm-svn: 106282
2010-06-18 15:30:29 +00:00
Dan Gohman
e20e668c7e Remove getIntegerSCEV; it's redundant with getConstant, and getConstant
is more consistent with the ConstantInt API.

llvm-svn: 106281
2010-06-18 14:33:50 +00:00
Dan Gohman
9443053ec4 Delete unused variables.
llvm-svn: 106280
2010-06-18 14:32:32 +00:00
Dan Gohman
0b5b93b20d Eliminate unnecessary uses of getZExtValue().
llvm-svn: 106279
2010-06-18 14:22:04 +00:00
Dan Gohman
22ff84372b isValueValidForType can be a static member function.
llvm-svn: 106278
2010-06-18 14:01:07 +00:00
Eric Christopher
e60cfc56b0 Some assorted isTwoAddress -> Constraints cleanup.
llvm-svn: 106273
2010-06-18 02:41:19 +00:00