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68 Commits

Author SHA1 Message Date
Jyotsna Verma
a1b968ec45 Hexagon: Pass to replace tranfer/copy instructions into combine instruction 
where possible.

llvm-svn: 181817
 2013-05-14 18:54:06 +00:00
Jyotsna Verma
980fae33f3 Hexagon: Add patterns to generate 'combine' instructions. 
llvm-svn: 181805
 2013-05-14 17:16:38 +00:00
Jyotsna Verma
86beda7e47 Hexagon: ArePredicatesComplement should not restrict itself to TFRs. 
llvm-svn: 181803
 2013-05-14 16:36:34 +00:00
Jyotsna Verma
a892e02220 Hexagon: Test case to check if branch probabilities are properly reflected in 
the jump instructions in the form of taken/not-taken hint.

llvm-svn: 181799
 2013-05-14 15:50:49 +00:00
Jyotsna Verma
2dfc0b2d13 Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. 
llvm-svn: 181624
 2013-05-10 20:27:34 +00:00
Jyotsna Verma
15d448ba0c Hexagon: Use relation map for getMatchingCondBranchOpcode() and 
getInvertedPredicatedOpcode() functions instead of switch cases.

llvm-svn: 181530
 2013-05-09 18:25:44 +00:00
Jyotsna Verma
37863260ff Hexagon: Fix Small Data support to handle -G 0 correctly. 
llvm-svn: 181344
 2013-05-07 19:53:00 +00:00
Jyotsna Verma
5307666fe8 Reverting r181331. 
Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt.

llvm-svn: 181334
 2013-05-07 17:12:35 +00:00
Jyotsna Verma
af0c734e1b Hexagon: Fix Small Data support to handle -G 0 correctly. 
llvm-svn: 181331
 2013-05-07 16:42:15 +00:00
Pranav Bhandarkar
520d26e773 Hexagon - Add peephole optimizations for zero extends. 
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
	sequence of a pair of i32->i64 extensions followed by a "bitwise or"
	into COMBINE_rr.
	* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
	instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
	* test/CodeGen/Hexagon/union-1.ll: New test.
	* test/CodeGen/Hexagon/combine_ir.ll: Fix test.

llvm-svn: 180946
 2013-05-02 20:22:51 +00:00
Manman Ren
0b37dd0efc TBAA: remove !tbaa from testing cases if not used. 
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.

llvm-svn: 180796
 2013-04-30 17:52:57 +00:00
Jyotsna Verma
4a5d195942 Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions. 
llvm-svn: 180145
 2013-04-23 21:17:40 +00:00
Jyotsna Verma
624f2e0434 Hexagon: Remove assembler mapped instruction definitions. 
llvm-svn: 180133
 2013-04-23 19:15:55 +00:00
Jyotsna Verma
20903a7aba Hexagon: Remove duplicate instructions to handle global/immediate values 
for absolute/absolute-set addressing modes.

llvm-svn: 180120
 2013-04-23 17:11:46 +00:00
Jyotsna Verma
f28cc49519 Hexagon: Enable SupportDebugInfomation and DwarfInSection flags. 
llvm-svn: 178279
 2013-03-28 19:34:49 +00:00
Jyotsna Verma
8a524534a6 Hexagon: Use multiclass for gp-relative instructions. 
Remove noV4T gp-relative instructions.

llvm-svn: 178246
 2013-03-28 16:25:57 +00:00
Jyotsna Verma
665c66e6ea Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. 
llvm-svn: 178032
 2013-03-26 15:43:57 +00:00
Jyotsna Verma
fa7dec4e5b Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word. 
llvm-svn: 177747
 2013-03-22 18:41:34 +00:00
Jyotsna Verma
f2d3c71cf4 Hexagon: Removed asserts regarding alignment and offset. 
We are warning the user about the alignment, so we should not assert.

llvm-svn: 177103
 2013-03-14 19:08:03 +00:00
Jyotsna Verma
6ba1f8e0d8 Hexagon: Add patterns for zero extended loads from i1->i64. 
llvm-svn: 176689
 2013-03-08 14:15:15 +00:00
Jyotsna Verma
50e5f420d7 Hexagon: Handle i8, i16 and i1 Var Args. 
llvm-svn: 176647
 2013-03-07 20:28:34 +00:00
Jyotsna Verma
c3d8f08545 Hexagon: Add support to lower block address. 
llvm-svn: 176637
 2013-03-07 19:10:28 +00:00
Jyotsna Verma
e27b88fb08 reverting patch 176508. 
llvm-svn: 176513
 2013-03-05 20:29:23 +00:00
Jyotsna Verma
ef3cf2b345 Hexagon: Add support for lowering block address. 
llvm-svn: 176508
 2013-03-05 19:37:46 +00:00
Jyotsna Verma
baf7212bfe Hexagon: Expand addc, adde, subc and sube. 
llvm-svn: 176505
 2013-03-05 19:04:47 +00:00
Jyotsna Verma
c096fbaa7d Hexagon: Add encoding bits to the TFR64 instructions. 
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.

llvm-svn: 176499
 2013-03-05 18:42:28 +00:00
Jyotsna Verma
359daa8ad9 Hexagon: Add constant extender support framework. 
llvm-svn: 176358
 2013-03-01 17:37:13 +00:00
Anshuman Dasgupta
810cccb843 Hexagon: Expand cttz, ctlz, and ctpop for now. 
llvm-svn: 175783
 2013-02-21 19:39:40 +00:00
Jyotsna Verma
84136133e3 Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h. 
Add HexagonMCInst class which adds various Hexagon VLIW annotations.
In addition, this class also includes some APIs related to the
constant extenders.

llvm-svn: 175634
 2013-02-20 16:13:27 +00:00
Anshuman Dasgupta
a6322b9e0a Hexagon: add support for predicate-GPR copies. 
llvm-svn: 175102
 2013-02-13 22:56:34 +00:00
Jyotsna Verma
a382dbb48f Hexagon: Use absolute addressing mode loads/stores for global+offset 
instead of redefining separate instructions for them.

llvm-svn: 175086
 2013-02-13 21:38:46 +00:00
Jyotsna Verma
abd979fd30 Hexagon: Add support to generate predicated absolute addressing mode 
instructions.

llvm-svn: 174973
 2013-02-12 16:06:23 +00:00
Krzysztof Parzyszek
272abb00e0 Extend Hexagon hardware loop generation to handle various additional cases: 
- variety of compare instructions,
- loops with no preheader,
- arbitrary lower and upper bounds.

llvm-svn: 174904
 2013-02-11 21:37:55 +00:00
Jyotsna Verma
31124b1816 Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle 
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns.

llvm-svn: 174429
 2013-02-05 19:20:45 +00:00
Jyotsna Verma
a3fc230d1b Hexagon: Add testcase for post-increment store instructions. 
llvm-svn: 174419
 2013-02-05 18:23:51 +00:00
Jyotsna Verma
774837ab41 Hexagon: Use multiclass for absolute addressing mode stores. 
llvm-svn: 174412
 2013-02-05 18:15:34 +00:00
Jyotsna Verma
56ef42a2ac Hexagon: Add V4 compare instructions. Enable relationship mapping 
for the existing instructions.

llvm-svn: 174389
 2013-02-05 16:42:24 +00:00
Jyotsna Verma
e97a68f8b5 Hexagon: Add V4 combine instructions and some more Def Pats for V2. 
llvm-svn: 174331
 2013-02-04 15:52:56 +00:00
Jyotsna Verma
5e4467cefa Hexagon: Test case to confirm generation of indexed loads with zero offset. 
llvm-svn: 174196
 2013-02-01 16:40:06 +00:00
Jyotsna Verma
01c6fabba6 Add indexed load/store instructions for offset validation check. 
This patch fixes bug 14902 - http://llvm.org/bugs/show_bug.cgi?id=14902

llvm-svn: 172737
 2013-01-17 18:42:37 +00:00
Matthew Curtis
596e698b79 In hexagon convertToHardwareLoop, don't deref end() iterator 
In particular, check if MachineBasicBlock::iterator is end() before
using it to call getDebugLoc();

See also this thread on llvm-commits:
   http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121112/155914.html

llvm-svn: 169634
 2012-12-07 21:03:15 +00:00
Jyotsna Verma
c8d145f6f6 Use multiclass to define store instructions with base+immediate offset 
addressing mode and immediate stored value.

llvm-svn: 169408
 2012-12-05 19:32:03 +00:00
NAKAMURA Takumi
8adf86a12e test/CodeGen/Hexagon/postinc-load.ll: Suppress it for now. It triggered the failure on i686 hosts. 
llvm-svn: 167988
 2012-11-14 22:22:37 +00:00
Jyotsna Verma
a472ef54f3 Added multiclass for post-increment load instructions. 
llvm-svn: 167974
 2012-11-14 20:38:48 +00:00
Pranav Bhandarkar
876ff208b6 LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access the 
subreg_hireg of register pair Rp.

	* lib/Target/Hexagon/HexagonPeephole.cpp(PeepholeDoubleRegsMap): New
	 DenseMap similar to PeepholeMap that additionally records subreg info
	 too.
        (runOnMachineFunction): Record information in PeepholeDoubleRegsMap
        and copy propagate the high sub-reg of Rp0 in Rp1 = lsr(Rp0, #32) to
	the instruction Rx = COPY Rp1:logreg_subreg.
	* test/CodeGen/Hexagon/remove_lsr.ll: New test.
	

llvm-svn: 163214
 2012-09-05 16:01:40 +00:00
Sergei Larin
905bc1964f Porting Hexagon MI Scheduler to the new API. 
Change current Hexagon MI scheduler to use new converging
scheduler. Integrates DFA resource model into it.

llvm-svn: 163137
 2012-09-04 14:49:56 +00:00
Jakob Stoklund Olesen
93b4cf4daf Remove extra MayLoad/MayStore flags from atomic_load/store. 
These extra flags are not required to properly order the atomic
load/store instructions. SelectionDAGBuilder chains atomics as if they
were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on
the memory operands of all atomic operations.

The volatile bit is enough to order atomic loads and stores during and
after SelectionDAG.

This means we set mayLoad on atomic_load, mayStore on atomic_store, and
mayLoad+mayStore on the remaining atomic read-modify-write operations.

llvm-svn: 162733
 2012-08-28 03:11:32 +00:00
Jakob Stoklund Olesen
43f9c539ae Infer instruction properties from single-instruction patterns. 
Previously, instructions without a primary patterns wouldn't get their
properties inferred. Now, we use all single-instruction patterns for
inference, including 'def : Pat<>' instances.

This causes a lot of instruction flags to change.

- Many instructions no longer have the UnmodeledSideEffects flag because
  their flags are now inferred from a pattern.

- Instructions with intrinsics will get a mayStore flag if they already
  have UnmodeledSideEffects and a mayLoad flag if they already have
  mayStore. This is because intrinsics properties are linear.

- Instructions with atomic_load patterns get a mayStore flag because
  atomic loads can't be reordered. The correct workaround is to create
  pseudo-instructions instead of using normal loads. PR13693.

llvm-svn: 162614
 2012-08-24 22:46:53 +00:00
Arnold Schwaighofer
dbdb2581b8 [Hexagon] Don't mark callee saved registers as clobbered by a tail call 
This was causing unnecessary spills/restores of callee saved registers.

Fixes PR13572.

Patch by Pranav Bhandarkar!

llvm-svn: 161778
 2012-08-13 19:54:01 +00:00
Bob Wilson
b173ddc53e Add test triples to fix win32 failures. Revert workaround from r161292. 
I don't have a win32 system to test, so hopefully I got them all fixed here.

llvm-svn: 161519
 2012-08-08 20:31:37 +00:00