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Author SHA1 Message Date
Andrew Trick
efe8cdcf20 Removing indvars tests that directly test canonical IVs and nothing else. 
llvm-svn: 139518
 2011-09-12 18:33:08 +00:00
Andrew Trick
09cf4287c2 Rename -disable-iv-rewrite to -enable-iv-rewrite=false in preparation for default change. 
llvm-svn: 139517
 2011-09-12 18:28:44 +00:00
Devang Patel
c7a1210467 Add asserts to keep front-ends honest while encoding debug info into LLVM IR using DIBuilder. 
llvm-svn: 139515
 2011-09-12 18:26:08 +00:00
Eli Friedman
08926ecbfb Fix mistake in test runline. 
llvm-svn: 139505
 2011-09-12 17:32:58 +00:00
Andrew Trick
19f9e653cd Test case for r139453, WidenIV::GetExtendedOperandRecurrence. 
llvm-svn: 139504
 2011-09-12 17:20:57 +00:00
Devang Patel
484cb2a602 Add DW_ATE_UTF, which clang started using in my previous commit! 
llvm-svn: 139503
 2011-09-12 17:18:20 +00:00
Jakob Stoklund Olesen
a147642106 Remove the -compact-regions flag. 
It has been enabled by default for a while, it was only there to allow
performance comparisons.

llvm-svn: 139501
 2011-09-12 16:54:42 +00:00
Jakob Stoklund Olesen
e43edf1b4a Add an interface for SplitKit complement spill modes. 
SplitKit always computes a complement live range to cover the places
where the original live range was live, but no explicit region has been
allocated.

Currently, the complement live range is created to be as small as
possible - it never overlaps any of the regions.  This minimizes
register pressure, but if the complement is going to be spilled anyway,
that is not very important.  The spiller will eliminate redundant
spills, and hoist others by making the spill slot live range overlap
some of the regions created by splitting.  Stack slots are cheap.

This patch adds the interface to enable spill modes in SplitKit.  In
spill mode, SplitKit will assume that the complement is going to spill,
so it will allow it to overlap regions in order to avoid back-copies.
By doing some of the spiller's work early, the complement live range
becomes simpler.  In some cases, it can become much simpler because no
extra PHI-defs are required.  This will speed up both splitting and
spilling.

This is only the interface to enable spill modes, no implementation yet.

llvm-svn: 139500
 2011-09-12 16:49:21 +00:00
Jakob Stoklund Olesen
fed2345086 Update comments to reflect some (not so) recent changes. 
llvm-svn: 139498
 2011-09-12 16:03:26 +00:00
Richard Osborne
962b1ca071 Associate a MemOperand with LDWCP nodes introduced during ISel. 
This information is required if we want LDWCP to be hoisted out of loops.

llvm-svn: 139495
 2011-09-12 14:43:23 +00:00
Richard Osborne
05cda7958d Mark LDWCP as having no side effects. 
llvm-svn: 139494
 2011-09-12 14:41:31 +00:00
Nadav Rotem
06ce2ac074 Format patterns, remove unused X86blend patterns 
llvm-svn: 139491
 2011-09-12 08:41:50 +00:00
Craig Topper
5ffd0cb080 Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. 
llvm-svn: 139486
 2011-09-11 23:19:54 +00:00
Craig Topper
a9b27eecc9 Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. 
llvm-svn: 139485
 2011-09-11 21:41:45 +00:00
Craig Topper
8361de67b5 Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W. 
llvm-svn: 139484
 2011-09-11 20:23:20 +00:00
Nick Lewycky
1226a13418 s/SequeuentiallyConsistent/SequentiallyConsistent/g 
llvm-svn: 139481
 2011-09-11 15:50:05 +00:00
Nick Lewycky
9f071eb204 Fix verb tense agreement. 
llvm-svn: 139480
 2011-09-11 15:30:08 +00:00
Nadav Rotem
abb5bb41d4 CR fixes per Bruno's request. 
Undo the changes from r139285 which added custom lowering to vselect.
Add tablegen lowering for vselect.

llvm-svn: 139479
 2011-09-11 15:02:23 +00:00
Eli Friedman
2275f7612e Really un-XFAIL the testcase, like I said I would in r139458. 
llvm-svn: 139459
 2011-09-10 02:02:27 +00:00
Eli Friedman
c79e318f02 r139454 activates an assert in a case where we were doing the right thing anyway. Make that explicit, and un-XFAIL the testcase. 
llvm-svn: 139458
 2011-09-10 02:01:42 +00:00
Richard Trieu
8b6890f67e Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp and 
lib/ExecutionEngine/MCJIT/MCJIT.cpp from:

  assert("error");

to:

  assert(0 && "error");

llvm-svn: 139456
 2011-09-10 01:42:07 +00:00
Richard Trieu
0485e133f2 Fixed an assert from: 
assert("not implemented for target shuffle node");

to:

  assert(0 && "not implemented for target shuffle node");

This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.

llvm-svn: 139454
 2011-09-10 01:26:21 +00:00
Andrew Trick
cf4ef9bded [disable-iv-rewrite] Allow WidenIV to handle NSW/NUW operations 
better.

Don't immediately give up when an add operation can't be trivially
sign/zero-extended within a loop. If it has NSW/NUW flags, generate a
new expression with sign extended (non-recurrent) operand. As before,
if SCEV says that all sign extends are loop invariant, then we can
widen the operation.

llvm-svn: 139453
 2011-09-10 01:24:17 +00:00
Andrew Trick
8af62b87e4 Set NSW/NUW flags on SCEVAddExpr when the operation is flagged as 
such.

I'm doing this now for completeness because I can't think of/remember
any reason that it was left out. I'm not sure it will help anything,
but if we don't do it we need to explain why in comments.

llvm-svn: 139450
 2011-09-10 01:09:50 +00:00
Richard Trieu
43ea533a5e Fix asserts in CodeGen from: 
assert("error");

to:

  assert(0 && "error");

llvm-svn: 139449
 2011-09-10 01:07:54 +00:00
Jim Grosbach
52492b1cf3 Thumb2 parsing and encoding for MOV(immediate). 
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

llvm-svn: 139440
 2011-09-10 00:15:36 +00:00
Akira Hatanaka
a8f0f7babb Fix test cases. 
Generate code for Mips32r1 unless a Mips32r2 feature is tested.

llvm-svn: 139433
 2011-09-09 23:14:58 +00:00
Owen Anderson
9cd21ce8c9 LDM writeback is not allowed if Rn is in the target register list. 
llvm-svn: 139432
 2011-09-09 23:13:33 +00:00
Owen Anderson
ca4447e808 Fix an ambiguously nested if. 
llvm-svn: 139431
 2011-09-09 23:13:02 +00:00
Owen Anderson
58bb862098 Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB. 
llvm-svn: 139429
 2011-09-09 23:05:14 +00:00
Owen Anderson
dbe77fc5a1 Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. 
llvm-svn: 139422
 2011-09-09 22:24:36 +00:00
Akira Hatanaka
45bb471537 O64 will not be supported. 
llvm-svn: 139421
 2011-09-09 22:22:48 +00:00
Akira Hatanaka
da477aa5eb Make F31 and D15 non-reserved registers. 
llvm-svn: 139420
 2011-09-09 22:11:26 +00:00
Chris Lattner
a1676de9bd tidy up a bit 
llvm-svn: 139419
 2011-09-09 22:06:59 +00:00
Owen Anderson
a7838cb723 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. 
llvm-svn: 139415
 2011-09-09 21:48:23 +00:00
Douglas Gregor
6a808433ce Update Clang AST attribute reader tblgen generation to match with ASTReader change 
llvm-svn: 139414
 2011-09-09 21:37:29 +00:00
Akira Hatanaka
be07ce941b Mips32 does not reserve even-numbered floating point registers. 
llvm-svn: 139412
 2011-09-09 21:31:46 +00:00
Eli Friedman
4bae1c4f70 Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897. 
llvm-svn: 139407
 2011-09-09 21:04:06 +00:00
Akira Hatanaka
f65d050693 Drop support for Mips1 and Mips2. 
llvm-svn: 139405
 2011-09-09 20:45:50 +00:00
Nadav Rotem
ccb46031e6 Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type 
llvm-svn: 139400
 2011-09-09 20:29:17 +00:00
Jim Grosbach
6225a96bf5 Thumb2 assembly parsing and encoding for MLA and MLS. 
llvm-svn: 139399
 2011-09-09 20:24:45 +00:00
Duncan Sands
3311da4d79 Don't tack "Instruction not interpretable yet!" onto the end of 
the instruction.

llvm-svn: 139398
 2011-09-09 20:22:48 +00:00
Jim Grosbach
5f87c06a64 Thumb2 assembly parsing and encoding for MCR, MCR2, MCRR, MCRR2. 
llvm-svn: 139397
 2011-09-09 20:19:28 +00:00
Jim Grosbach
f310295150 Tidy up formatting a bit. 
llvm-svn: 139396
 2011-09-09 20:17:49 +00:00
Jim Grosbach
f7d8e569b3 Thumb2 assembly parsing and encoding for LSL. 
llvm-svn: 139395
 2011-09-09 20:05:38 +00:00
Jim Grosbach
69e67f206d Thumb2 assembly parsing and encoding for LDRT. 
llvm-svn: 139393
 2011-09-09 20:02:15 +00:00
Jim Grosbach
abd54fb32c Thumb2 assembly parsing and encoding for LDRSHT. 
llvm-svn: 139392
 2011-09-09 20:01:18 +00:00
Jim Grosbach
c6aa5be010 Thumb2 assembly parsing and encoding for LDRSH. 
llvm-svn: 139391
 2011-09-09 19:54:30 +00:00
Jim Grosbach
022da868a5 Thumb2 assembly parsing and encoding for LDRSBT. 
llvm-svn: 139390
 2011-09-09 19:49:06 +00:00
Jim Grosbach
915ba5189e Thumb2 assembly parsing and encoding for LDRSB. 
llvm-svn: 139389
 2011-09-09 19:42:40 +00:00